Re: [PATCH] virtio-gpu: Add definition for resource_uuid feature

Hi Manos, Thanks, for spotting that! On Sat, Oct 5, 2024 at 7:43 AM Manos Pitsidianakis < manos.pitsidiana...@linaro.org> wrote: > Hello Dorinda, > > On Fri, 04 Oct 2024 19:41, Dorinda Bassey wrote: > >Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment > >of resources UUIDs for

Re: [PATCH v2 23/25] target/s390x: Use explicit big-endian LD/ST API

On 04/10/2024 18.30, Philippe Mathieu-Daudé wrote: The S390X architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(

Re: [PATCH v2 22/25] hw/s390x: Use explicit big-endian LD/ST API

On 04/10/2024 18.30, Philippe Mathieu-Daudé wrote: The S390X architecture uses big endianness. Directly use the big-endian LD/ST API. Mechanical change using: $ end=be; \ for acc in uw w l q tul; do \ sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \ -e "s/st${acc}_p(

Re: [PATCH 03/16] linux-user/i386: Use explicit little-endian LD/ST API

On 04/10/2024 01.41, Philippe Mathieu-Daudé wrote: The x86 architecture uses little endianness. Directly use the little-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- linux-user/i386/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/i386

Re: [PATCH 02/16] exec/memop: Remove unused memop_big_endian() helper

On 04/10/2024 01.41, Philippe Mathieu-Daudé wrote: Last use of memop_big_endian() was removed in commit 592134617c9 ("accel/tcg: Reorg system mode store helpers"). Signed-off-by: Philippe Mathieu-Daudé --- include/exec/memop.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/include/

Re: [PATCH 01/16] qemu/bswap: Undefine CPU_CONVERT() once done

On 04/10/2024 01.41, Philippe Mathieu-Daudé wrote: Better undefined macros once we are done with them, like we do few lines later with DO_STN_LDN_P(). Signed-off-by: Philippe Mathieu-Daudé --- include/qemu/bswap.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/qemu/bswap.h b/i

Re: [PATCH 10/16] target/s390x: Use explicit big-endian LD/ST API

On 04/10/2024 01.42, Philippe Mathieu-Daudé wrote: The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- target/s390x/gdbstub.c | 4 ++-- target/s390x/ioinst.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) R

Re: [PATCH 09/16] hw/s390x: Use explicit big-endian LD/ST API

On 04/10/2024 01.42, Philippe Mathieu-Daudé wrote: The S390 architecture uses big endianness. Directly use the big-endian LD/ST API. Signed-off-by: Philippe Mathieu-Daudé --- hw/s390x/ipl.c | 4 +- hw/s390x/s390-pci-inst.c | 166 +++ 2 files c

[PATCH v1 6/7] target/riscv: Reset SXL and UXL according to sxl32

From: TANG Tiancheng When boot a 32-bit system, sxl and uxl should be set to 1 by OpenSBI. However, OpenSBI does not support this feature. We temporarily force QEMU reset SXL and UXL to MXL_RV32 when sxl32 is enabled. Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 13 +++-- 1

[PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU

From: TANG Tiancheng Enable with "-cpu rv64,sxl32=on". When sxl32 is enabled, RV64 can boot 32-bit Linux with 64-bit Opensbi while requiring to make minor modifications to the Linux kernel source code. How to patch linux: https://git Signed-off-by: TANG Tiancheng --- target/riscv/cpu.c | 1 +

[PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32

From: TANG Tiancheng Allow reading 32-bit only registers like timeh and stimecmph when booting a 32-bit Linux kernel on RV64 when sxl32 is true. Signed-off-by: TANG Tiancheng --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/tar

[PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on.

From: TANG Tiancheng RISC-V always requires 4MB alignment for RV32. Signed-off-by: TANG Tiancheng --- hw/riscv/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1a2c1ff9e0..7ce0d8f08f 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv

[PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW

From: TANG Tiancheng Satp and PTE are always SXLEN-bit. when SXLEN is 32, read PTE as 4 bytes, and treat satp as SATP32. Signed-off-by: TANG Tiancheng --- target/riscv/cpu_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/

[PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly.

From: TANG Tiancheng CSR satp is SXLEN bits in length and always has the $layout determined by the SXL configuration, regardless of the current XLEN. Only process CSR satp, as we still don't have a riscv_cpu_vsxl API currently. Added sxl32 property to control sxlen as 32 in s-mode for QEMU RV64

[PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU

From: TANG Tiancheng We have implemented UXL32 on QEMU already. It enables us to run RV32 applications on RV64 Linux on QEMU. Similarly, RISCV specification doesn't limit the SXLEN to be the same with MXLEN. In this patch set, we will go forward to implement SXL32 on RV64 CPU. SXL is one filed i

[PATCH v1 1/7] target/riscv: Fix sstatus read and write

From: TANG Tiancheng Sstatus is SXLEN bits in length and always has the layout determined by the SXL configuration, regardless of the current XLEN. Signed-off-by: TANG Tiancheng Fixes: b550f89457 (target/riscv: Compute mstatus.sd on demand) Fixes: f310df58bd (target/riscv: Enable uxl field writ

[PATCH v5 12/12] tcg/riscv: Enable native vector support for TCG host

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.h | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e6d66cd1b9..d27007f2e6 100644

[PATCH v5 11/12] tcg/riscv: Implement vector roti/v/x ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 6 +++--- 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tc

[PATCH v5 10/12] tcg/riscv: Implement vector shi/s/v ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 + tcg/riscv/tcg-target.c.inc | 76 ++ tcg/riscv/tcg-target.h | 6 +-- 3 files changed, 80 insertions(

[PATCH v5 09/12] tcg/riscv: Implement vector min/max ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 29 + tcg/riscv/tcg-target.h | 2 +- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.

[PATCH v5 08/12] tcg/riscv: Implement vector sat/mul ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 36 tcg/riscv/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/t

[PATCH v5 07/12] tcg/riscv: Implement vector neg ops

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 7 +++ tcg/riscv/tcg-target.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-tar

[PATCH v5 06/12] tcg/riscv: Implement vector cmp/cmpsel ops

From: TANG Tiancheng 1.Address immediate value constraints in RISC-V Vector Extension 1.0 for comparison instructions. 2.Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_ve

[PATCH v5 05/12] tcg/riscv: Add support for basic vector opcodes

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 ++ tcg/riscv/tcg-target.c.inc | 52 ++ tcg/riscv/tcg-target.h | 2 +- 3 files changed, 55 insertions(

[PATCH v5 04/12] tcg/riscv: Implement vector mov/dup{m/i}

From: TANG Tiancheng Signed-off-by: TANG Tiancheng Reviewed-by: Liu Zhiwei Reviewed-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 73 -- 1 file changed, 71 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-targe

[PATCH v5 03/12] tcg/riscv: Add vset{i}vli and ld/st vec ops

From: TANG Tiancheng In RISC-V, vector operations require initial vtype and vl using the vset{i}vl{i} instruction. This instruction: 1. Sets the vector length (vl) in bytes 2. Configures the vtype register, which includes: SEW (Single Element Width) LMUL (vector register group multip

[PATCH v5 02/12] tcg/riscv: Add basic support for vector

From: Huang Shiyuan The RISC-V vector instruction set utilizes the LMUL field to group multiple registers, enabling variable-length vector registers. This implementation uses only the first register number of each group while reserving the other register numbers within the group. In TCG, each VE

[PATCH v5 00/12] tcg/riscv: Add support for vector

From: TANG Tiancheng This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets. v5: 1. Improve the signature of co-authors 2. Add probe for fractional LMUL setting. 3. Fix bug of INDEX_op_rotlv_vec. 4. Modify the author's alias swung0x48 to hi

[PATCH v5 01/12] util: Add RISC-V vector extension probe in cpuinfo

From: TANG Tiancheng Add support for probing RISC-V vector extension availability in the backend. This information will be used when deciding whether to use vector instructions in code generation. Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means we can convert all of the divisio

[PATCH v1 1/2] ui/sdl2: Don't disable scanout when display is refreshed

Display refreshment is invoked by a timer and it erroneously disables the active scanout if it happens to be invoked after scanout has been enabled. This offending scanout-disable race condition with a timer can be easily hit when Qemu runs with a disabled vsync by using SDL or GTK displays (with v

[PATCH v1 0/2] GTK/SDL fixes for a black screen displayed by virtio-gpu

Hi, This patchset fixes black screen displayed by Qemu using virtio-gpu. There is a race condition bug with a timer that disables display output after it has been enabled by virtio-gpu. The problem is reproducible by running Qemu with a disabled GL vsync. Note vsync is disabled for SDL display by

[PATCH v1 2/2] ui/gtk: Don't disable scanout when display is refreshed

Display refreshment is invoked by a timer and it erroneously disables the active scanout if it happens to be invoked after scanout has been enabled. This offending scanout-disable race condition with a timer can be easily hit when Qemu runs with a disabled vsync by using SDL or GTK displays (with v

[PATCH v1 2/6] ui/sdl2: Implement dpy dmabuf functions

From: Pierre-Eric Pelloux-Prayer If EGL is used, we can rely on dmabuf to import textures without doing copies. To get this working on X11, we use the existing SDL hint: SDL_HINT_VIDEO_X11_FORCE_EGL (because dmabuf can't be used with GLX). Signed-off-by: Pierre-Eric Pelloux-Prayer Signed-off-b

[PATCH v1 0/6] Support virtio-gpu DRM native context

This patchset adds DRM native context support to VirtIO-GPU on Qemu. It's based on the pending Venus v17 patches [1] that bring host blobs support to virtio-gpu-gl device. [1] https://lore.kernel.org/qemu-devel/20240822185110.1757429-1-dmitry.osipe...@collabora.com/ Contarary to Virgl and Venus

[PATCH v1 4/6] virtio-gpu: Handle virgl fence creation errors

Print out error messages when virgl fence creation fails to aid debugging of the fence-related bugs. Signed-off-by: Dmitry Osipenko --- hw/display/virtio-gpu-virgl.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/display/virtio-gpu-virgl.c b/hw/display/virtio-gpu-v

[PATCH v1 5/6] virtio-gpu: Support asynchronous fencing

Support asynchronous fencing feature of virglrenderer. It allows Qemu to handle fence as soon as it's signalled instead of periodically polling the fence status. This feature is required for enabling DRM context support in Qemu because legacy fencing mode isn't supported for DRM contexts in virglre

[PATCH v1 6/6] virtio-gpu: Support DRM native context

Add support for DRM native contexts to VirtIO-GPU. DRM context is enabled using a new virtio-gpu-gl device option "drm=true". Unlike Virgl and Venus contexts that operate on application API level, DRM native contexts work on a kernel UAPI level. This lower level results in a lightweight context im

[PATCH v1 3/6] linux-headers: Update to Linux v6.12-rc1

Update kernel headers to bring new VirtIO-GPU DRM capset. Signed-off-by: Dmitry Osipenko --- include/standard-headers/drm/drm_fourcc.h | 43 include/standard-headers/linux/const.h| 17 ++ include/standard-headers/linux/ethtool.h | 226 ++ include/standard-

[PATCH v1 1/6] ui/sdl2: Restore original context after new context creation

SDL API changes GL context to a newly created GL context, which differs from other GL providers that don't switch context. Change SDL backend to restore the original GL context. This allows Qemu's virtio-gpu to support new virglrenderer async-fencing feature for Virgl context, otherwise it's imposs

Re: [PATCH 1/2] hw/ppc: Consolidate e500 initial mapping creation functions

On Thu, 15 Aug 2024, Bernhard Beschow wrote: Am 16. Juli 2024 12:07:57 UTC schrieb BALATON Zoltan : Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines. Signed-off-by: BALATON Zoltan --- hw/ppc/e500.c | 41 +++

Re: [PATCH v2 09/23] hw/ppc/mpc8544_guts: Populate POR PLL ratio status register

On Sat, 5 Oct 2024, Bernhard Beschow wrote: Populate this read-only register with some arbitrary values which avoids U-Boot's get_clocks() to hang(). Signed-off-by: Bernhard Beschow I think the register fields are overkill, a value with a comment or some or'ed shift'ed values with a comment

Re: [PATCH v2 08/23] hw/ppc/ppce500_ccsr: Log access to unimplemented registers

On Sat, 5 Oct 2024, Bernhard Beschow wrote: The CCSR space is just a container which is meant to be covered by platform device memory regions. However, QEMU only implements a subset of these devices. Add some logging to see which devices a guest attempts to access. Signed-off-by: Bernhard Bescho

Re: [PATCH v2 01/23] hw/ppc/e500: Do not leak struct boot_info

On Sat, 5 Oct 2024, Bernhard Beschow wrote: The struct is allocated once with g_new0() but never free()'d. Fix the leakage by adding an attribute to struct PPCE500MachineState which avoids the allocation. While at it remove the obsolete /*< private >*/ markers. Signed-off-by: Bernhard Beschow

[PATCH 2/2] log: Suggest using -d guest_error,memaccess instead of guest_errors

Rename guest_errors to guest_error to match the log constant and print a warning for -d guest_errors to remind using guest_error,memaccess instead but preserve previous behaviour for convenience. Signed-off-by: BALATON Zoltan --- As this is a debug switch I think no formal deprecation is needed b

[PATCH 1/2] log: Add separate debug option for logging invalid memory accesses

Currently -d guest_errors enables logging of different invalid actions by the guest such as misusing hardware, accessing missing features or invalid memory areas. The memory access logging can be quite verbose which obscures the other messages enabled by this debug switch so separate it by adding a

[PATCH 0/2] Separate memory access logs from guest_errors

Originally memory access logs were a debug define that then were converted to log messages but were classified as guest_errors which already logs misc errors. As invalid memory access logs can come from accessing not emulated peripherals or memory areas, these often generate a lot of messages that

Re: [PATCH v2 2/4] linux-user/flatload: Take mmap_lock in load_flt_binary()

On 10/6/24 01:51, Michael Tokarev wrote: 22.08.2024 12:50, Philippe Mathieu-Daudé wrote: load_flt_binary() calls load_flat_file() -> page_set_flags(). page_set_flags() must be called with the mmap_lock held, otherwise it aborts:    $ qemu-arm -L stm32/lib/ stm32/bin/busybox    qemu-arm: ../acc

Re: [PATCH v3 1/2] xilink_zynq: Add various missing unimplemented devices

On Sat, 5 Oct 2024 at 17:06, Chao Liu wrote: > > Add xilinx zynq board memory mapping is implemented in the device. > > Remove a ignore_memory_transaction_failures concurrently. > > Source: Zynq-7000 SoC Data Sheet: Overview, Chapter: Memory Map > > See: > https://www.mouser.com/datasheet/2/903/d

Re: [PULL 00/23] Misc patches for 2024-10-04

On Fri, 4 Oct 2024 at 17:34, Paolo Bonzini wrote: > > The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855: > > Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into > staging (2024-10-01 11:34:07 +0100) > > are available in the Git repository at: > >

Re: [PATCH v3 01/14] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Thu, 3 Oct 2024 at 09:09, Akihiko Odaki wrote: > On 2024/10/02 22:33, Phil Dennis-Jordan wrote: > > > > > > > +#include "apple-gfx.h" > > > +#include "monitor/monitor.h" > > > +#include "hw/sysbus.h" > > > +#include "hw/irq.h" > > > +#include "trace.h" > > > +#imp

Re: [PATCH v2 2/4] linux-user/flatload: Take mmap_lock in load_flt_binary()

22.08.2024 12:50, Philippe Mathieu-Daudé wrote: load_flt_binary() calls load_flat_file() -> page_set_flags(). page_set_flags() must be called with the mmap_lock held, otherwise it aborts: $ qemu-arm -L stm32/lib/ stm32/bin/busybox qemu-arm: ../accel/tcg/user-exec.c:505: page_set_flags: As

Re: [PATCH] tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr

06.10.2024 01:15, Richard Henderson wrote: In tcg_out_qemu_ldst_i128, we need a non-zero index register, which we then use as a base register in several address modes. Since we always have TCG_REG_TMP2 available, use that. In tcg_out_qemu_st, in the fallback when STDBRX is not available, avoid c

Re: [PATCH] meson: fix machine option for x86_version

Queued, thanks. Paolo

[PATCH net-next v7] ptp: Add support for the AMZNC10C 'vmclock' device

From: David Woodhouse The vmclock device addresses the problem of live migration with precision clocks. The tolerances of a hardware counter (e.g. TSC) are typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that counter against an external source of 'real' time, and track the pre