From: TANG Tiancheng <tangtiancheng....@alibaba-inc.com> This patch set introduces support for the RISC-V vector extension in TCG backend for RISC-V targets.
v5: 1. Improve the signature of co-authors 2. Add probe for fractional LMUL setting. 3. Fix bug of INDEX_op_rotlv_vec. 4. Modify the author's alias swung0x48 to his real name Huang Shiyuan and add signed-off tag. 5. Add vtype initialization in tcg_out_call_int() and prepare_host_addr(). v4: https://lists.gnu.org/archive/html/qemu-riscv/2024-09/msg00284.html v3: https://lists.gnu.org/archive/html/qemu-riscv/2024-09/msg00060.html v2: https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00679.html v1: https://lists.gnu.org/archive/html/qemu-riscv/2024-08/msg00205.html Huang Shiyuan (1): tcg/riscv: Add basic support for vector TANG Tiancheng (11): util: Add RISC-V vector extension probe in cpuinfo tcg/riscv: Add vset{i}vli and ld/st vec ops tcg/riscv: Implement vector mov/dup{m/i} tcg/riscv: Add support for basic vector opcodes tcg/riscv: Implement vector cmp/cmpsel ops tcg/riscv: Implement vector neg ops tcg/riscv: Implement vector sat/mul ops tcg/riscv: Implement vector min/max ops tcg/riscv: Implement vector shi/s/v ops tcg/riscv: Implement vector roti/v/x ops tcg/riscv: Enable native vector support for TCG host host/include/riscv/host/cpuinfo.h | 2 + include/tcg/tcg.h | 7 + tcg/riscv/tcg-target-con-set.h | 7 + tcg/riscv/tcg-target-con-str.h | 3 + tcg/riscv/tcg-target.c.inc | 1016 ++++++++++++++++++++++++++--- tcg/riscv/tcg-target.h | 80 ++- tcg/riscv/tcg-target.opc.h | 12 + util/cpuinfo-riscv.c | 24 +- 8 files changed, 1031 insertions(+), 120 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h -- 2.43.0
