On 03/10/2024 23.40, Philippe Mathieu-Daudé wrote:
On 3/10/24 23:34, Pierrick Bouvier wrote:
On 10/3/24 14:31, Pierrick Bouvier wrote:
On 10/3/24 13:48, Philippe Mathieu-Daudé wrote:
On 3/10/24 18:04, Pierrick Bouvier wrote:
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, T
On 2024/09/28 17:57, Phil Dennis-Jordan wrote:
From: Alexander Graf
VMApple contains an "aes" engine device that it uses to encrypt and
decrypt its nvram. It has trivial hard coded keys it uses for that
purpose.
Add device emulation for this device model.
Signed-off-by: Alexander Graf
Co-aut
LGTM, thanks for the update
Reviewed-by: Clément Mathieu--Drif
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Add an new element scalable_mode in IntelIOMMUState to mark scalable
> modern
On 2024/09/28 17:57, Phil Dennis-Jordan wrote:
From: Alexander Graf
Some boards such as vmapple don't do real legacy PCI IRQ swizzling.
Instead, they just keep allocating more board IRQ lines for each new
legacy IRQ. Let's support that mode by giving instantiators a new
"nr_irqs" property they
On 2024/09/28 17:57, Phil Dennis-Jordan wrote:
This change adds a property 'display_modes' on the graphics device
which permits specifying a list of display modes. (screen resolution
and refresh rate)
PCI variant of apple-gfx only for the moment.
Signed-off-by: Phil Dennis-Jordan
---
hw/disp
- Am 30. Sep 2024 um 17:16 schrieb Peter Maydell peter.mayd...@linaro.org:
> On Mon, 23 Sept 2024 at 04:57, Sebastian Huber
> wrote:
>>
>> In arm_load_kernel(), use the secondary boot hooks provided by the
>> platform if PSCI is disabled also while booting a non-Linux kernel.
>> While booting
On Thu, Oct 03, 2024 at 11:33:35AM -0700, Deepak Gupta wrote:
`check_zicbom_access` (`cbo.clean/flush/inval`) may probe shadow stack
memory and must always raise store/AMO access fault because it has store
semantics.
For non-shadow stack memory even though `cbo.clean/flush/inval` have
store sema
The 32-bit PPC architecture uses big endianness. Directly use
the big-endian LD/ST API for the E500 hardware.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/ppce500_spin.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/ppce500_spin.c b/hw/
The S390 architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/s390x/ipl.c | 4 +-
hw/s390x/s390-pci-inst.c | 166 +++
2 files changed, 85 insertions(+), 85 deletions(-)
diff --git a/
Better undefined macros once we are done with them,
like we do few lines later with DO_STN_LDN_P().
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/bswap.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h
index ad22910a5d1..b915835bead 1006
The SPARC architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sparc/leon3.c | 42 +-
hw/sparc/sun4m.c | 6 +++---
hw/sparc64/sun4u.c | 6 +++---
3 files changed, 27 insertions(+), 27 d
The SPARC architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index ec0036e9ef6..da72a7d3f
The M68K architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/m68k/bootinfo.h | 28 ++--
hw/m68k/mcf5208.c | 2 +-
hw/m68k/next-cube.c | 2 +-
hw/m68k/q800.c | 4 ++--
4 files changed, 18 insertio
The S390 architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/gdbstub.c | 4 ++--
target/s390x/ioinst.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/i386/signal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/i386/signal.c b/linux-user/i386/signal.c
index cb90711834f.
The M68K architecture uses big endianness. Directly use
the big-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/gdbstub.c | 2 +-
target/m68k/helper.c | 10 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/m68k/gdbstub.c b/target/m68k/gdb
For targets (or HW) which are only built for a particular
endianness, the generic LD/ST helpers are defined as the
target endianness variant. For example, on big-endian
targets, stl_p() is equivalent of stl_be_p().
This series replaces in bulk these LD/ST calls.
This is helpful for the single bin
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/gdbstub.c| 26 +++---
target/i386/tcg/sysemu/excp_helper.c | 4 ++--
target/i386/xsave_helper.c | 32 +++
The x86 architecture uses little endianness. Directly use
the little-endian LD/ST API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/multiboot.c | 36 ++--
hw/i386/x86-common.c | 26 +-
2 files changed, 31 insertions(+), 31 deletions(-
Last use of memop_big_endian() was removed in commit 592134617c9
("accel/tcg: Reorg system mode store helpers").
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/memop.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index f881fe7af4e..
On 10/2/24 08:47, Peter Maydell wrote:
There's also something curious going on here -- this patch
says "we check alignment before permissions, and that's wrong
on PARISC". But there's a comment in target/arm/ptw.c that
says "we check permissions before alignment, and that's
wrong on Arm":
On 9/30/24 02:11, Philippe Mathieu-Daudé wrote:
Since all code creating vCPUs now set the 'cpu-big-endian' property,
we can remove the target-specific #ifdef'ry in mips_cpu_reset_hold():
the CP0C0_BE bit is set using the property cpu->is_big_endian value.
Signed-off-by: Philippe Mathieu-Daudé
-
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c | 9 -
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/mips/tcg/translat
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/mips16e_translate.c.inc | 101 +---
1 file changed, 53 insertions(+), 48
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote:
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as cpu_is_bigendian_env().
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h| 6 ++
target/mips/tcg/ldst_helper.c | 15 +
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote:
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
net/l2tpv3.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/net/l2tpv3.c b/net/l2tpv3.c
index b5547cb917..7a0d5dcfe9
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote:
Directly call ldn_be_p once instead of ldl_be_p / ldq_be_p.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_vof.c | 27 +--
1 file changed, 9 insertions(+), 18 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/27/24 14:50, Philippe Mathieu-Daudé wrote:
ldn/stn methods handle the access size, no need for the switch case.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/spapr_nvdimm.c | 47 ---
1 file changed, 4 insertions(+), 43 deletions(-)
Reviewed-by
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Refactor to use the recently introduced ld/st_endian_pci_dma()
API. No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/tulip.c | 32 ++--
1 file changed, 10 insertions(+), 22 deletions(-)
d
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_pci_dma() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_pci_dma() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/hw/pci/pci_device.h | 24
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_phys() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_phys() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/exec/memory_ldst_phys.h.inc | 66 ++
On 3/10/24 23:37, Richard Henderson wrote:
On 10/3/24 14:34, Philippe Mathieu-Daudé wrote:
On 3/10/24 23:28, Richard Henderson wrote:
On 10/3/24 13:50, Philippe Mathieu-Daudé wrote:
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
Alte
On Thu, Oct 03, 2024 at 04:26:27PM -0500, Michael Galaxy wrote:
> What about the testing solution that I mentioned?
>
> Does that satisfy your concerns? Or is there still a gap here that needs to
> be met?
I think such testing framework would be helpful, especially if we can kick
it off in CI whe
On 3/10/24 23:34, Pierrick Bouvier wrote:
On 10/3/24 14:31, Pierrick Bouvier wrote:
On 10/3/24 13:48, Philippe Mathieu-Daudé wrote:
On 3/10/24 18:04, Pierrick Bouvier wrote:
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mat
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_phys() API, which takes an extra
boolean argument to dispatch to ld/st_{be,le}_phys() methods.
Signed-off-by: Philippe Mathieu-Daudé
---
TODO: Update docstring regexp
---
include/exec/memory_ldst_phys.h.inc | 66 ++
On 10/3/24 14:34, Philippe Mathieu-Daudé wrote:
On 3/10/24 23:28, Richard Henderson wrote:
On 10/3/24 13:50, Philippe Mathieu-Daudé wrote:
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
Alternatively we could use ld/st_te_p() since we
On 9/30/24 00:34, Philippe Mathieu-Daudé wrote:
Move code evaluation from preprocessor to compiler so
both if() ladders are processed. Mostly style change.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --
On 3/10/24 23:28, Richard Henderson wrote:
On 10/3/24 13:50, Philippe Mathieu-Daudé wrote:
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
Alternatively we could use ld/st_te_p() since we already
have ld/st_he_p() for host endianness.
On 10/3/24 14:31, Pierrick Bouvier wrote:
On 10/3/24 13:48, Philippe Mathieu-Daudé wrote:
On 3/10/24 18:04, Pierrick Bouvier wrote:
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote:
Replace a pair of memcpy
On 1/10/24 15:01, Peter Maydell wrote:
On Mon, 30 Sept 2024 at 21:05, Jan Lübbe wrote:
On Mon, 2024-09-30 at 15:18 +0100, Peter Maydell wrote:
On Fri, 6 Sept 2024 at 17:51, Jan Luebbe wrote:
The enable bits in the EXT_CSD_PART_CONFIG ext_csd register do *not*
specify whether the boot parti
On 10/3/24 13:48, Philippe Mathieu-Daudé wrote:
On 3/10/24 18:04, Pierrick Bouvier wrote:
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote:
Replace a pair of memcpy() + tswap32() by stl_endian_p(),
which als
On 10/3/24 13:50, Philippe Mathieu-Daudé wrote:
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
Alternatively we could use ld/st_te_p() since we already
have ld/st_he_p() for host endianness.
That's what ld/st_p are -- target-specific,
On 9/30/24 14:47, Peter Xu wrote:
!---|
This Message Is From an External Sender
This message came from outside your organization.
|---!
On Mon, Sep 30, 2024 at 07
On Thu, Oct 03, 2024 at 10:34:28PM +0200, Maciej S. Szmigiero wrote:
> To be clear, these loading threads are mostly blocking I/O threads, NOT
> compute threads.
> This means that the usual "rule of thumb" that the count of threads should
> not exceed the total number of logical CPUs does NOT apply
On 19/9/24 01:47, d...@treblig.org wrote:
From: "Dr. David Alan Gilbert"
pcie_chassis_find_slot has been unused since it was added.
Remove it.
Signed-off-by: Dr. David Alan Gilbert
---
hw/pci/pcie_port.c | 10 --
include/hw/pci/pcie_port.h | 1 -
2 files changed, 11 dele
On 18/9/24 16:41, d...@treblig.org wrote:
From: "Dr. David Alan Gilbert"
serial_set_frequnecy has been unused since it was added in 2009:
038eaf82c8 ("serial: Add interface to set reference oscillator frequency")
It looks like the 'baudbase' is now a property anyway so the wrapper
isn't nee
On 2/10/24 16:37, Thomas Huth wrote:
The cris target has recently been removed (see commit 44e4075bf4 -
"target/cris: Remove the deprecated CRIS target"), but apparently this
line has been forgotten. So clean it up now.
Crossed pull request ¯\_(ツ)_/¯
Thanks for cleaning.
Reviewed-by: Philippe
On 2/10/24 17:01, Daniel Henrique Barboza wrote:
On 10/2/24 11:44 AM, Mark Cave-Ayland wrote:
On 02/10/2024 15:17, Daniel Henrique Barboza wrote:
Phil, this patch breaks 'make check-avocado' in my env:
On 9/30/24 9:48 AM, Philippe Mathieu-Daudé wrote:
Hold the target endianness in HTIFSta
On 2/10/24 20:06, Daniel Henrique Barboza wrote:
On 9/27/24 7:50 AM, Daniel P. Berrangé wrote:
Markus: QAPI design Qs for you at the bottom
On Wed, Sep 25, 2024 at 10:19:33AM -0300, Daniel Henrique Barboza wrote:
On 9/19/24 9:22 AM, Daniel P. Berrangé wrote:
On Thu, Sep 19, 2024 at 08:20:5
On 30/9/24 09:34, Philippe Mathieu-Daudé wrote:
Introduce the ld/st_endian_p() API, which takes an extra
Alternatively we could use ld/st_te_p() since we already
have ld/st_he_p() for host endianness.
boolean argument to dispatch to ld/st_{be,le}_p() methods.
Signed-off-by: Philippe Mathieu-
On 3/10/24 18:04, Pierrick Bouvier wrote:
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote:
Replace a pair of memcpy() + tswap32() by stl_endian_p(),
which also swap the value using target endianness.
Signed
On 2.10.2024 23:25, Peter Xu wrote:
On Wed, Oct 02, 2024 at 10:11:33PM +0200, Maciej S. Szmigiero wrote:
On 1.10.2024 23:30, Peter Xu wrote:
On Tue, Oct 01, 2024 at 10:41:14PM +0200, Maciej S. Szmigiero wrote:
On 30.09.2024 23:57, Peter Xu wrote:
On Mon, Sep 30, 2024 at 09:25:54PM +0200, Maci
On 10/1/24 08:03, Ilya Leoshkevich wrote:
commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before translation")
fixed cross-modifying code handling, but did not add a test. The
changed code was further improved recently [1], and I was not sure
whether these modifications were safe (spoiler: they
On 9/26/24 03:21, Philippe Mathieu-Daudé wrote:
We were including the "exec/tswap.h" header to get
target_words_bigendian() declaration, but since commit a276ec8e26
("hw/audio/virtio-snd: Always use little endian audio format")
removed this method call, we don't need this header anymore.
Signed-
From: "Edgar E. Iglesias"
Enable PCI support for the ARM Xen PVH machine.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xen-pvh.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 28af3910ea..33f0dd5982
From: "Edgar E. Iglesias"
Add a way to enable/disable buffered IOREQs for PVH machines
and disable them for ARM. ARM does not support buffered
IOREQ's nor the legacy way to map IOREQ info pages.
See the following for more details:
https://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=2fbd7e60
From: "Dr. David Alan Gilbert"
xen_be_copy_grant_refs is unused since 2019's
19f87870ba ("xen: remove the legacy 'xen_disk' backend")
xen_config_dev_console is unused since 2018's
6d7c06c213 ("Remove broken Xen PV domain builder")
Remove them.
Signed-off-by: Dr. David Alan Gilbert
Acked-b
From: "Edgar E. Iglesias"
Acked-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
hw/xen/xen-pvh-common.c | 36
1 file changed, 36 insertions(+)
diff --git a/hw/xen/xen-pvh-common.c b/hw/xen/xen-pvh-common.c
index 76a9b2b945..218ac851cf 100644
--
From: "Edgar E. Iglesias"
Expose handle_bufioreq in xen_register_ioreq().
This is to allow machines to enable or disable buffered ioreqs.
No functional change since all callers still set it to
HVM_IOREQSRV_BUFIOREQ_ATOMIC.
Reviewed-by: Stefano Stabellini
Signed-off-by: Edgar E. Iglesias
---
From: "Edgar E. Iglesias"
The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
into staging (2024-10-03 10:32:54 +0100)
are available in the Git repository at:
https://gitlab.com/edgar.iglesi
On Thu, Oct 03, 2024 at 06:07:00PM +0100, Peter Maydell wrote:
> On Thu, 3 Oct 2024 at 15:31, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
> >
> > Merge tag 'warn-pull-request' of https://gitla
On 9/24/24 23:17, Heinrich Schuchardt wrote:
The status and mstatus CSRs contain bit field FS, which control if the
floating point unit of RISC-V hart is enabled.
There seems to be no specification prescribing the value of the field when
entering S-mode from M-mode. But OpenSBI, as the leading S
sspush and sspopchk have equivalent compressed encoding taken from zcmop.
cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
for both rs1 and rs2 from space bitfield, this required a new codec.
Signed-off-by: Deepak Gupta
Acked-by: Alistair Francis
---
disas/riscv.c | 19 +
Signed-off-by: Deepak Gupta
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac5ad6fa9d..0751d08d85 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1473,6 +1473,7 @@ const RISCVCPUM
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> >> +/*
> >> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> >> + *
> >> + * Note: Code i
zicfiss [1] riscv cpu extension enables backward control flow integrity.
This patch sets up space for zicfiss extension in cpuconfig. And imple-
ments dependency on A, zicsr, zimop and zcmop extensions.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Sh
Shadow stack instructions can be decoded as zimop / zcmop or shadow stack
instructions depending on whether shadow stack are enabled at current
privilege. This requires a TB flag so that correct TB generation and correct
TB lookup happens. `DisasContext` gets a field indicating whether bcfi is
enab
v15 for riscv zicfilp and zicfiss extensions support in qemu.
I've rebased again on
https://github.com/alistair23/qemu/blob/riscv-to-apply.next
(tag: pull-riscv-to-apply-20241002)
There is an additional patch in this with comment title
"target/riscv: disallow probe accesses to shadow stack"
cac
Signed-off-by: Deepak Gupta
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 05f727222e..135559fc95 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1469,6 +1469,7 @@ const RISCVCPUM
`check_zicbom_access` (`cbo.clean/flush/inval`) may probe shadow stack
memory and must always raise store/AMO access fault because it has store
semantics.
For non-shadow stack memory even though `cbo.clean/flush/inval` have
store semantics, it will not fault if read is allowed (probably to follow
sw check exception support was recently added. This patch further augments
sw check exception by providing support for additional code which is
provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever
sw check exception is raised *tval gets the value deposited in
`sw_check_code`.
Si
sspush/sspopchk have compressed encodings carved out of zcmops.
compressed sspush is designated as c.mop.1 while compressed sspopchk
is designated as c.mop.5.
Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly
c.sspopchk x5 exists while c.sspopchk x1 doesn't.
Signed-off-by: Deepak
Implements setting lp expected when `jalr` is encountered and implements
`lpad` instruction of zicfilp. `lpad` instruction is taken out of
auipc x0, . This is an existing HINTNOP space. If `lpad` is
target of an indirect branch, cpu checks for 20 bit value in x7 upper
with 20 bit value embedded in
Extra word 2 is stored during tcg compile and `decode_save_opc` needs
additional argument in order to pass the value. This will be used during
unwind to get extra information about instruction like how to massage
exceptions. Updated all callsites as well.
Resolves: https://gitlab.com/qemu-project/
zicfilp protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpad`. If
target of an indirect call or jmp is not `lpad` then cpu/hart must raise
a sw check exception with tval = 2.
This patch implements the mechanism using TCG. Ta
This patch adds one more word for tcg compile which can be obtained during
unwind time to determine fault type for original operation (example AMO).
Depending on that, fault can be promoted to store/AMO fault.
Signed-off-by: Deepak Gupta
Suggested-by: Richard Henderson
Reviewed-by: Richard Hende
zicfiss introduces a new state ssp ("shadow stack register") in cpu.
ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds
virtual address for shadow stack as programmed by software.
Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs.
Shadow stack can be enabled for a m
zicfiss protects shadow stack using new page table encodings PTE.W=1,
PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
implemented or if shadow stack are not enabled.
Loads on shadow stack memory are allowed while stores to shadow stack
memory leads to access faults. Shadow stack ac
zicfiss has following instructions
- sspopchk: pops a value from shadow stack and compares with x1/x5.
If they dont match, reports a sw check exception with tval = 3.
- sspush: pushes value in x1/x5 on shadow stack
- ssrdp: reads current shadow stack
- ssamoswap: swaps contents of shadow sta
zicfilp [1] riscv cpu extension enables forward control flow integrity.
If enabled, all indirect calls must land on a landing pad instruction.
This patch sets up space for zicfilp extension in cpuconfig. zicfilp
is dependend on zicsr.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepa
Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap.
Disasembly is only enabled if zimop and zicfiss ext is set to true.
Signed-off-by: Deepak Gupta
Acked-by: Alistair Francis
---
disas/riscv.c | 40 +++-
disas/riscv.h | 1 +
2 files changed, 40 inser
Execution environment config CSR controlling user env and current
privilege state shouldn't be limited to qemu-system only. *envcfg
CSRs control enabling of features in next lesser mode. In some cases
bits *envcfg CSR can be lit up by kernel as part of kernel policy or
software (user app) can choos
Signed-off-by: Deepak Gupta
Co-developed-by: Jim Shu
Co-developed-by: Andy Chiu
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
---
disas/riscv.c | 18 +-
disas/riscv.h | 2 ++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/r
zicfilp introduces a new state elp ("expected landing pad") in cpu.
During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
LP_EXPECTED, only a subsquent landing pad instruction can set state back
to NO_LP_EXPECTED
elp state is recorded in *status on trap entry (less privilege to higher
privilege) and restored in elp from *status on trap exit (higher to less
privilege).
Additionally this patch introduces a forward cfi helper function to
determine if current privilege has forward cfi is enabled or not based o
On 9/24/24 12:14, Philippe Mathieu-Daudé wrote:
Hi Peter,
(patch merged as commit 6087df574400659226861fa5ba47970f1fbd277b).
On 12/9/23 16:04, Peter Maydell wrote:
The FEAT_MOPS SETG* instructions are very similar to the SET*
instructions, but as well as setting memory contents they also
set t
On Thu, Feb 29, 2024 at 01:37:10AM -0500, Xiaoyao Li wrote:
> From: Isaku Yamahata
>
> Add property "quote-generation-socket" to tdx-guest, which is a property
> of type SocketAddress to specify Quote Generation Service(QGS).
>
> On request of GetQuote, it connects to the QGS socket, read reques
On 20/9/24 10:06, Yoshinori Sato wrote:
On Wed, 18 Sep 2024 04:43:50 +0900,
Thomas Huth wrote:
Commit 0ea0538fae516f9b4 removed the default machine of the sh4
binaries, so a lot of iotests are failing now without such a default
machine. Teach the iotest harness to use the "r2d" machine instead
On 9/25/24 20:05, Michael Kowal wrote:
From: Frederic Barrat
These XIVE tests include:
- General interrupt IRQ tests that:
- enable and trigger an interrupt
- acknowledge the interrupt
- end of interrupt processing
- Test the Pull Thread Context to Odd Thread Reporting Line
- Test the
On Thu, 3 Oct 2024 at 15:31, Edgar E. Iglesias wrote:
>
> From: "Edgar E. Iglesias"
>
> The following changes since commit 423be09ab9492735924e73a2d36069784441ebc6:
>
> Merge tag 'warn-pull-request' of https://gitlab.com/marcandre.lureau/qemu
> into staging (2024-10-03 10:32:54 +0100)
>
> are
On Mon, Sep 30, 2024 at 12:40:32PM -0700, Steve Sistare wrote:
> Allocate anonymous memory using mmap MAP_ANON or memfd_create depending
> on the value of the anon-alloc machine property. This option applies to
> memory allocated as a side effect of creating various devices. It does
> not apply to
On 26/9/24 09:59, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
MAINTAINERS | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 10/3/24 09:02, Philippe Mathieu-Daudé wrote:
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote:
Replace a pair of memcpy() + tswap32() by stl_endian_p(),
which also swap the value using target endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/
On 3/10/24 16:34, Peter Maydell wrote:
Accessing another device in a post_load hook is a bad idea, because
the order of device save/restore is not fixed, and so this
cross-device access makes the save/restore non-deterministic.
We previously only flagged up this requirement in the
record-and-rep
On 30/9/24 16:32, Thomas Huth wrote:
On 30/09/2024 09.34, Philippe Mathieu-Daudé wrote:
Replace a pair of memcpy() + tswap32() by stl_endian_p(),
which also swap the value using target endianness.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/xtensa/xtfpga.c | 6 ++
1 file changed, 2 ins
On 21/9/24 12:47, Inès Varhol wrote:
It has been a learning experience to contribute to QEMU for our
end-of-studies project. For a few months now, Arnaud and I aren't
actively involved anymore as we lack time and access to the hardware.
Therefore it's high time to update the maintainers file: fro
On 27/9/24 09:10, Ard Biesheuvel wrote:
From: Ard Biesheuvel
target_ulong is typedef'ed as a 32-bit integer when building the
qemu-system-arm target, and this is smaller than the size of an
intermediate physical address when LPAE is being used.
Given that Linux may place leaf level user page t
On 3/10/24 16:00, Peter Maydell wrote:
The DSCM-1 microdrive device model was used only by the
XScale-based Zaurus machine types. Now they have been removed, we
can delete this device too.
Signed-off-by: Peter Maydell
---
include/hw/pcmcia.h | 3 -
hw/ide/microdrive.c | 644 --
On 3/10/24 16:00, Peter Maydell wrote:
The ecc.c code was used only by the PXA2xx and OMAP2 SoC devices,
which we have removed, so it is now completely unused.
Note that hw/misc/eccmemctl.c does not in fact use any of the
code frome ecc.c, so that KConfig dependency was incorrect.
Signed-off-by
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