RISC-V virt is currently missing default type for block devices. Without
this being set, proper backend is not created when option like -cdrom
is used. So, make the virt board's default block device type be
IF_VIRTIO similar to other architectures.
We also need to set no_cdrom to avoid getting a d
Recent changes made sbsa-ref crash when more than 1 cpu core was used.
We handle it in firmware now so one patch updates it to the working
snapshot (TF-A 2.11 + EDK2 snapshot + EDK2-platforms snapshot).
Other change drops "-smp 1" from CI to make sure we test default setup
of sbsa-ref.
I have no
I was wondering why avocado tests passed with firmware which crashes
when anyone else is using it.
Turned out that amount of cores matters. Have to find out why still.
Signed-off-by: Marcin Juszkiewicz
---
tests/avocado/machine_aarch64_sbsaref.py | 2 --
1 file changed, 2 deletions(-)
diff --g
240528-140808/edk2/SBSA_FLASH0.fd.xz"
+"20240619-148232/edk2/SBSA_FLASH0.fd.xz"
)
-fs0_xz_hash =
"fa6004900b67172914c908b78557fec4d36a5f784f4c3dd08f49adb75e1892a9"
+fs0_xz_hash =
"0c954842a590988f526984de22e21ae0ab9cb351a0c99
On 6/19/24 8:36 PM, Zheyu Ma wrote:
ASan detected a global-buffer-overflow error in the aspeed_gpio_read()
function. This issue occurred when reading beyond the bounds of the
reg_table.
To enhance the safety and maintainability of the Aspeed GPIO code, this commit
introduces a reg_table_size mem
in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240619
for you to fetch changes up to 521d7fb3ebdf88112ed13556a93e3037742b9eb8:
tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers (2024-06-19
13:5
On 6/13/24 10:51, Max Chou wrote:
In the vector unit-stride load/store helper functions. the vext_ldst_us
& vext_ldst_whole functions corresponding most of the execution time.
Inline the functions can avoid the function call overhead to improve the
helper function performance.
Signed-off-by: Max
On 6/13/24 10:51, Max Chou wrote:
+#define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \
+static void NAME##_tlb(CPURISCVState *env, abi_ptr addr,\
+ uint32_t byte_off, void *vd, uintptr_t retaddr) \
+{
On 6/13/24 10:51, Max Chou wrote:
The vector unmasked unit-stride and whole register load/store
instructions will load/store continuous memory. If the endian of both
the host and guest architecture are the same, then we can group the
element load/store to load/store more data at a time.
Signed-o
On 6/13/24 10:51, Max Chou wrote:
This commit references the sve_ldN_r/sve_stN_r helper functions in ARM
target to optimize the vector unmasked unit-stride load/store
instructions by following items:
* Get the loose bound of activate elements
* Probing pages/resolving host memory address/handlin
On 6/13/24 10:51, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
accel/tcg/ldst_common.c.inc | 8 ++--
1 file changed, 6 insertions(
On Mon, Jun 17, 2024 at 02:09:34PM +0200, Stefan Weil wrote:
> [EXTERNAL MAIL]
>
> Am 12.06.24 um 05:17 schrieb Ethan Chen via:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
>
On Mon, Jun 17, 2024 at 07:28:33PM +0800, LIU Zhiwei wrote:
>
> On 2024/6/12 11:17, Ethan Chen wrote:
> > Support basic functions of IOPMP specification v0.9.1 rapid-k model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
> >
> > IOPMP check memory
On 6/19/24 03:22, Philippe Mathieu-Daudé wrote:
On 19/6/24 00:45, Roman Kiryanov wrote:
to use the QEMU headers with a C++ compiler.
Google-Bug-Id: 331190993
Change-Id: Ic4e49b9c791616bb22c973922772b0494706092c
Signed-off-by: Roman Kiryanov
---
include/exec/memory.h | 4 ++--
1 file changed
On Wed, 2024-06-19 at 20:36 +0200, Zheyu Ma wrote:
> ASan detected a global-buffer-overflow error in the aspeed_gpio_read()
> function. This issue occurred when reading beyond the bounds of the
> reg_table.
>
> To enhance the safety and maintainability of the Aspeed GPIO code, this commit
> introd
This patch adds a migration state on src called "postcopy-recover-setup".
The new state will describe the intermediate step starting from when the
src QEMU received a postcopy recovery request, until the migration channels
are properly established, but before the recovery process take place.
The r
Libvirt should always enable it, so it'll be nice qtest also cover that for
all tests on both sides. migrate_incoming_qmp() used to enable it only on
dst, now we enable them on both, as we'll start to sanity check events even
on the src QEMU.
We'll need to leave the one in migrate_incoming_qmp(),
Most of them are not needed, we can stick with one ifdef inside
postcopy_recover_fail() so as to cover the scm right tricks only.
The tests won't run on windows anyway due to has_uffd always false.
Reviewed-by: Fabiano Rosas
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 10 ++--
Making sure the postcopy-recover-setup status is present in the postcopy
failure unit test. Note that it only applies to src QEMU not dest.
This also introduces the tiny but helpful migration_event_wait() helper.
Signed-off-by: Peter Xu
---
tests/qtest/migration-test.c | 6 ++
1 file chang
Destination QEMU can setup incoming ports for two purposes: either a fresh
new incoming migration, in which QEMU will switch to SETUP for channel
establishment, or a paused postcopy migration, in which QEMU will stay in
POSTCOPY_PAUSED until kicking off the RECOVER phase.
Now the state machine wor
QEMU uses "int" in most cases even if it stores MigrationStatus. I don't
know why, so let's try to do that right and see what blows up..
Reviewed-by: Fabiano Rosas
Signed-off-by: Peter Xu
---
migration/migration.h | 9 +
migration/migration.c | 24 +++-
2 files cha
Firstly, the "Paused" state was added in the wrong place before. The state
machine section was describing PostcopyState, rather than MigrationStatus.
Drop the Paused state descriptions.
Then in the postcopy recover session, add more information on the state
machine for MigrationStatus in the lines
We always do the flush when finishing one round of scan, and during
complete() phase we should scan one more round making sure no dirty page
existed. In that case we shouldn't need one explicit FLUSH at the end of
complete(), as when reaching there all pages should have been flushed.
Reviewed-by:
Make sure there will be an event for postcopy recovery, irrelevant of
whether the reconnect will success, or when the failure happens.
The added new case is to fail early in postcopy recovery, in which case it
didn't even reach RECOVER stage on src (and in real life it'll be the same
to dest, but
Based-on: <20240617185731.9725-1-faro...@suse.de>
v3:
- Added one comment in patch 8 explaining why migrate_incoming_qmp() needs
to keep enabling "events" capability.
- Split patch 9 into two patches, which makes migration_event_wait() to be
used also in migrate_incoming_qmp()
- Rename the tes
Introduce a small helper to wait for a migration event, generalized from
the incoming migration path. Make the helper easier to use by allowing it
to keep waiting until the expected event is received.
Signed-off-by: Peter Xu
---
tests/qtest/migration-helpers.h | 2 ++
tests/qtest/migration-hel
The postcopy thread names on dest QEMU are slightly confusing, partly I'll
need to blame myself on 36f62f11e4 ("migration: Postcopy preemption
preparation on channel creation"). E.g., "fault-fast" reads like a fast
version of "fault-default", but it's actually the fast version of
"postcopy/listen"
Hi Chalapathi,
I can't say I have a great understanding of this IBM SPI controller,
but I did find some places for improvement, mostly dealing with the use
of "magic numbers" throughout the code. Please see comments below.
Thanks,
Glenn
On Mon, 2024-06-17 at 11:54 -0500, Chalapathi V wrote:
>
Split out host/bufferiszero.h.inc for x86, aarch64 and generic
in order to avoid an overlong ifdef ladder.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 191 +--
host/include/aarch64/host/bufferiszero.c.in
From: Ilya Leoshkevich
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the
calling thread, and not the entire process. Therefore, implement it
using a syscall, and not a libc call.
Cc: qemu-sta...@nongnu.org
Fixes: 19b84f3c35d7 ("added setgroups and getgroups syscalls")
Signed-off-
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-targ
From: Anton Johansson
For TBs crossing page boundaries, the 2nd page will never be
recorded/removed, as the index of the 2nd page is computed from the
address of the 1st page. This is due to a typo, fix it.
Cc: qemu-sta...@nongnu.org
Fixes: deba78709a ("accel/tcg: Always lock pages before transl
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 9
Use inline assembly because no release compiler allows
per-function selection of the ISA.
Tested-by: Bibo Mao
Signed-off-by: Richard Henderson
---
.../loongarch64/host/bufferiszero.c.inc | 143 ++
1 file changed, 143 insertions(+)
create mode 100644 host/include/loongarch
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 119 ---
1 file changed, 63 insertions(+), 56 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 652aa261a3..8f5f38aa0a 100644
--- a/tcg/loongarch6
Each element size has a different encoding, so code cannot
be shared in the same way as with tcg_out_dup_vec.
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff -
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 1e721b
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 8f5f38aa0a..4ead3bedef 100644
--- a/tcg/loongarch64/tcg-t
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index b1d652355d..cc54bc4a53 100644
--- a/tcg/loongarch64
From: Clément Chigot
The result has to be done with the signed denominator (b32) instead of
the unsigned value passed in argument (b).
Cc: qemu-sta...@nongnu.org
Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319
Signed-off-by: Clé
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
host/include/loongarch64/host/cpuinfo.h | 1 +
util/cpuinfo-loongarch.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/host/include/loongarch64/host/cpuinfo.h
b/host/include/loo
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 9a8f67cf3e..c7d0c7839b 100644
--- a/tcg/loongarch64/tcg-
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 223 +++
1 file changed, 137 insertions(+), 86 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index ab1b67e028..dff966c395 100
0/qemu.git tags/pull-tcg-20240619
for you to fetch changes up to 521d7fb3ebdf88112ed13556a93e3037742b9eb8:
tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers (2024-06-19 13:50:22
-0700)
tcg/loongarch64: Support 64- a
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index c7d0c7839b..47011488dd 100644
Simplify the logic for two-part, 32-bit pc-relative addresses.
Rather than assume all such fit in int32_t, do some arithmetic
and assert a result, do some arithmetic first and then check
to see if the pieces are in range.
Cc: qemu-sta...@nongnu.org
Fixes: dacc51720db ("tcg/loongarch64: Implement t
Fixes a bug in the immediate shifts, because the exact
encoding depends on the element size.
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 58 ++--
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/tcg/loo
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index b9078ac793..de5369536e 100644
--- a/tc
Use TCG_VEC_TMP0 directly.
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.
We can implement this with fld_d, fst_d for load and store,
and then use the normal v128 operations in registers.
This will improve support for guests which use v64.
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.h
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 36 +---
1 file changed, 10 insertions(+), 26 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 06ca1ab11c..b9078ac793 1006
Reviewed-by: Song Gao
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 36 ++--
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 47011488dd..652aa261a3 1006
On Mon, Jun 17, 2024 at 05:23:24PM -0400, Peter Xu wrote:
> On Mon, Jun 17, 2024 at 04:51:32PM -0300, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> > > Libvirt should always enable it, so it'll be nice qtest also cover that
> > > for
> > > all tests. Though this patch only enables it, no extr
This commit adds a re-implementation of hw/char/pl011.c in Rust.
It uses generated Rust bindings (produced by `ninja
aarch64-softmmu-generated.rs`) to
register itself as a QOM type/class.
How to build:
1. Make sure rust, cargo and bindgen (cargo install bindgen-cli) are
installed
2. Configure
Add mechanism to generate rust hw targets that depend on a custom
bindgen target for rust bindings to C.
This way bindings will be created before the rust crate is compiled.
The bindings will end up in BUILDDIR/{target}-generated.rs and have the same
name
as a target:
ninja aarch64-softmmu-gene
Add options for Rust in meson_options.txt, meson.build, configure to
prepare for adding Rust code in the followup commits.
`rust` is a reserved meson name, so we have to use an alternative.
`with_rust` was chosen.
A cargo_wrapper.py script is added that is heavily based on the work of
Marc-André
Deploy the generated rustdocs for my personal rust qemu fork on gitlab.
The URL is:
https://rust-for-qemu-epilys-aebb06ca9f9adfe6584811c14ae44156501d935ba4.gitlab.io/pl011/index.html
Signed-off-by: Manos Pitsidianakis
---
.gitlab-ci.d/buildtest.yml | 64 +++---
Convenience patch for testing the rust device.
Signed-off-by: Manos Pitsidianakis
---
hw/arm/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3c93c0c0a6..f33b58ae0d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -912,7 +912,11 @@ static void c
Changes from v2->v3:
- Addressed minor mistakes (thanks Stefan)
- Setup supported version checks for cargo, rustc and bindgen (thanks
everyone who pointed it out / suggested it)
- Fixed problem with bindgen failing if certain system headers where
needed by defining an allowlist for headers in
in the Git repository at:
https://github.com/philmd/qemu.git tags/misc-20240619
for you to fetch changes up to fc0870c180872d0f40e63507cc6bf8565ffd8d98:
exec: Make the MemOp enum cast explicit (2024-06-19 12:52:21 +0200)
Spurious warning (3 times):
WARNING: added, moved or deleted fil
It's observed that Linux kernel booting with the VM reports a "conflicting
mapping for input ID" FW_BUG.
The IORT doc defines "Number of IDs" to be "the number of IDs in the range
minus one", while virt-acpi-build.c simply stores the number of IDs in the
id_count without the "minus one". Meanwhile
On Wed, Jun 19, 2024 at 04:15:35PM +0200, Eric Auger wrote:
> > @@ -209,12 +209,20 @@ static void acpi_dsdt_add_tpm(Aml *scope,
> > VirtMachineState *vms)
> > #define ROOT_COMPLEX_ENTRY_SIZE 36
> > #define IORT_NODE_OFFSET 48
> >
> > +/*
> > + * Input Output Remapping Table (IORT) -- Table 4 ID
On Tue, Jun 18, 2024 at 4:27 AM Clément Léger wrote:
>
> When icount is enabled, rather than returning the virtual CPU time, we
> should return the instruction count itself. Add an instructions bool
> parameter to get_ticks() to correctly return icount_get_raw() when
> icount_enabled() == 1 and in
The num_threads field reports the total number of threads in the
process. In QEMU, this is equal to the number of CPU instances.
Signed-off-by: Fabio D'Urso
---
linux-user/syscall.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index
Hi Philippe,
On Wed, Jun 19, 2024 at 6:29 PM Philippe Mathieu-Daudé
wrote:
> On 19/6/24 08:49, Zheyu Ma wrote:
> > Hi Andrew,
> >
> > On Wed, Jun 19, 2024 at 1:58 AM Andrew Jeffery
> > mailto:and...@codeconstruct.com.au>>
> wrote:
> >
> > Hello Zheyu Ma,
> >
> > On Tue, 2024-06-18 at 15:
ASan detected a global-buffer-overflow error in the aspeed_gpio_read()
function. This issue occurred when reading beyond the bounds of the
reg_table.
To enhance the safety and maintainability of the Aspeed GPIO code, this commit
introduces a reg_table_size member to the AspeedGPIOClass structure.
On Wed, Jun 19, 2024 at 12:12:50PM +0200, Igor Mammedov wrote:
> On Fri, 24 May 2024 11:44:10 +0530
> Sunil V L wrote:
>
> > Add basic ACPI table test case for RISC-V.
> >
> > Signed-off-by: Sunil V L
> > ---
> > tests/qtest/bios-tables-test.c | 27 +++
> > 1 file chang
On Wed, Jun 19, 2024 at 05:20:50AM -0400, Michael S. Tsirkin wrote:
> On Wed, Jun 19, 2024 at 11:17:43AM +0200, Igor Mammedov wrote:
> > On Mon, 27 May 2024 20:46:29 +0530
> > Sunil V L wrote:
> >
> > > On Mon, May 27, 2024 at 12:12:10PM +0200, Philippe Mathieu-Daudé wrote:
> > > > Hi Sunil,
> >
On Wed, Jun 19, 2024 at 8:40 PM Nir Soffer wrote:
> - Need to run all block tests
>
Stale note, make check pass
On 19/06/2024 15.34, Paolo Bonzini wrote:
On Wed, Jun 19, 2024 at 2:49 PM Thomas Huth wrote:
On 19/06/2024 13.46, Paolo Bonzini wrote:
Treat it as a MIPS64 machine.
...
diff --git a/configure b/configure
index d0703ea279d..3669eec86e5 100755
--- a/configure
+++ b/configure
@@ -452,7 +452,7
Tested using:
$ cat test-unmap.sh
#!/bin/sh
qemu=${1:?Usage: $0 qemu-executable}
img=/tmp/test.raw
echo
echo "defaults - write zeroes"
fallocate -l 1m $img
echo -e 'qemu-io none0 "write -z 0 1m"\nquit' | $qemu -monitor stdio \
-drive if=none,file=$img,format=raw >/dev/null
du -sh $img
echo
On Wed, 19 Jun 2024 06:31, Richard Henderson
wrote:
On 6/11/24 03:33, Manos Pitsidianakis wrote:
If `cargo` and `bindgen` is installed in your system, you should be able
to build qemu-system-aarch64 with configure flag --enable-rust and
launch an arm virt VM. One of the patches hardcodes the d
When opening an image with discard=off, we punch hole in the image when
writing zeroes, making the image sparse. This breaks users that want to
ensure that writes cannot fail with ENOSPACE by using fully allocated
images.
bdrv_co_pwrite_zeroes() correctly disable BDRV_REQ_MAY_UNMAP if we
opened th
Hi,
On 3/7/23 15:24, Cédric Le Goater wrote:
The parameters mimick a real 4GB eMMC, but it can be set to various
sizes. Initially from Vincent Palatin
Signed-off-by: Cédric Le Goater
---
hw/sd/sdmmc-internal.h | 97
include/hw/sd/sd.h | 1 +
hw/
Dmitry Osipenko writes:
> Hello,
>
> This series enables Vulkan Venus context support on virtio-gpu.
>
> All virglrender and almost all Linux kernel prerequisite changes
> needed by Venus are already in upstream. For kernel there is a pending
> KVM patchset that fixes mapping of compound pages ne
On Wed, 19 Jun 2024 19:52, Richard Henderson
wrote:
On 6/11/24 03:33, Manos Pitsidianakis wrote:
+++ b/scripts/cargo_wrapper.py
@@ -0,0 +1,211 @@
+#!/usr/bin/env python3
+# Copyright (c) 2020 Red Hat, Inc.
+# Copyright (c) 2023 Linaro Ltd.
+#
+# Authors:
+# Manos Pitsidianakis
+# Marc-André
On Wed, Jun 19, 2024, 9:20 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Eliminate the "Example" sections in QAPI doc blocks, converting them
> > into QMP example code blocks. This is generally done in this patch by
> > converting "Example:" or "Examples:" lines into ".. code-block:: QMP
Il mer 19 giu 2024, 18:54 Daniel P. Berrangé ha
scritto:
> >build/
> > rust/
> >.cargo/
> > config.toml # generated by configure or meson.build
> >Cargo.toml # workspace generated by configure or meson.build
> >Cargo.lock # can be either linke
On Wed, Jun 19, 2024, 2:28 AM Markus Armbruster wrote:
> John Snow writes:
>
> > In a forthcoming series that adds a new QMP documentation generator, it
> > will be helpful to have a linting baseline. However, there's no need to
> > shuffle around the deck chairs too much, because most of this c
On Wed, Jun 19, 2024 at 06:43:01PM +0200, Paolo Bonzini wrote:
> On 6/19/24 07:34, Richard Henderson wrote:
> > First silly question: how much of this is boiler plate that gets moved
> > the moment that the second rust subdirectory is added?
>
> If my suggestion at
> https://lore.kernel.org/qemu-
On 6/11/24 03:33, Manos Pitsidianakis wrote:
+++ b/scripts/cargo_wrapper.py
@@ -0,0 +1,211 @@
+#!/usr/bin/env python3
+# Copyright (c) 2020 Red Hat, Inc.
+# Copyright (c) 2023 Linaro Ltd.
+#
+# Authors:
+# Manos Pitsidianakis
+# Marc-André Lureau
+#
+# This work is licensed under the terms of t
On 6/19/24 07:34, Richard Henderson wrote:
First silly question: how much of this is boiler plate that gets moved
the moment that the second rust subdirectory is added?
If my suggestion at
https://lore.kernel.org/qemu-devel/CABgObfaP7DRD8dbSKNmUzhZNyxeHWO0MztaW3_EFYt=vf6s...@mail.gmail.com/
w
Hello Cedric,
Thank You for reviewing this patch series.
Regards,
Chalapathi
On 18-06-2024 21:18, Cédric Le Goater wrote:
Hello Chalapathi,
On 6/17/24 6:54 PM, Chalapathi V wrote:
SPI controller device model supports a connection to a single SPI
responder.
This provide access to SPI seeprom
On 19/6/24 08:49, Zheyu Ma wrote:
Hi Andrew,
On Wed, Jun 19, 2024 at 1:58 AM Andrew Jeffery
mailto:and...@codeconstruct.com.au>> wrote:
Hello Zheyu Ma,
On Tue, 2024-06-18 at 15:09 +0200, Zheyu Ma wrote:
> Added bounds checking in the aspeed_gpio_read() and
aspeed_gpio_write(
On 19/6/24 13:46, Paolo Bonzini wrote:
Treat it as a MIPS64 machine.
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
16.06.2024 12:23, Akihiko Odaki пишет:
...
>> #endif
>> +#if VIRGL_VERSION_MAJOR >= 1
>> +typedef enum {
>> + HOSTMEM_MR_MAPPED,
>
> HOSTMEM_MR_MAPPED is no longer used.
Good catch
--
Best regards,
Dmitry
19.06.2024 18:27, Alex Bennée пишет:
> Dmitry Osipenko writes:
>
>> From: Antonio Caggiano
>>
>> Support BLOB resources creation, mapping and unmapping by calling the
>> new stable virglrenderer 0.10 interface. Only enabled when available and
>> via the blob config. E.g. -device virtio-vga-gl,bl
This commit adds support for [m|s|vs]ctrcontrol, sctrstatus and
sctrdepth CSRs handling.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h | 5 ++
target/riscv/cpu_cfg.h | 2 +
target/riscv/csr.c | 128 +
3 files changed, 135 insertions(+)
CTR extension adds a new instruction sctrclr to quickly
clear the recorded entries buffer.
Signed-off-by: Rajnesh Kanwal
---
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 7
target/riscv/helper.h | 1 +
target
CTR entries are accessed using ctrsource, ctrtarget and ctrdata
registers using smcsrind/sscsrind extension. This commits extends
the csrind extension to support CTR registers.
ctrsource is accessible through xireg CSR, ctrtarget is accessible
through xireg1 and ctrdata is accessible through xireg
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depends on couple of other extensions:
1. S[m|s]csrind : The ind
This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.
This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and counter overflow interrupts.
Signed-off-by: Rajnesh Kanwal
---
t
The Control Transfer Records (CTR) extension provides a method to
record a limited branch history in register-accessible internal chip
storage.
This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here
https://github.com/ri
Signed-off-by: Rajnesh Kanwal
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.c.inc | 5 -
2 files changed, 6 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f22df04cfd..
Dmitry Osipenko writes:
> From: Antonio Caggiano
>
> Support BLOB resources creation, mapping and unmapping by calling the
> new stable virglrenderer 0.10 interface. Only enabled when available and
> via the blob config. E.g. -device virtio-vga-gl,blob=true
>
>
> #if VIRGL_VERSION_MAJOR >= 1
On 6/19/24 02:49, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/18/24 02:53, Alex Bennée wrote:
Pierrick Bouvier writes:
On 6/17/24 13:56, Dr. David Alan Gilbert wrote:
* Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote:
On 6/14/24 15:00, Dr. David Alan Gilbert wrote:
* Pierrick
On 19/06/2024 16.49, Zhao Liu wrote:
Hi maintainers,
Per my communication with Markus, it seems this renaming matches the
"local consistency" principle in (include/hw/boards.h). :-)
So do you think this change is acceptable?
I don't care too much, both ways of naming look acceptable to me...
Migration of a s390x guest with TCG was long known to be very unstable,
so the tests in tests/qtest/migration-test.c are disabled if running
with TCG instead of KVM.
Nicholas Piggin did a great analysis of the problem:
"The flic pending state is not migrated, so if the machine is migrated
while
Hi maintainers,
Per my communication with Markus, it seems this renaming matches the
"local consistency" principle in (include/hw/boards.h). :-)
So do you think this change is acceptable?
Thanks,
Zhao
On Mon, May 27, 2024 at 09:18:37PM +0800, Zhao Liu wrote:
> Date: Mon, 27 May 2024 21:18:37 +0
Hexadecimal mask is more intuitive comparing to decimal.
Therefore convert the mask of bits 00-04 to hexadecimal value.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 365852cb99e1..c4d
1 - 100 of 173 matches
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