Hi Peter
On Fri, May 10, 2024 at 9:33 PM Peter Xu wrote:
>
> Hi, Marc-André,
>
> On Fri, May 10, 2024 at 12:39:34PM +0400, Marc-André Lureau wrote:
> > Since we don't have per VMSD version information on the wire, nested
> > struct versioning is quite limited and cumbersome. I am not sure it
> >
On 2024/5/11 12:58, Yangyu Chen wrote:
This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.
Signed-off-by: Yangyu Chen
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto extensions to
riscv_cpu_extensions")
---
t
On Fri, May 10, 2024 at 3:16 PM Eugenio Perez Martin
wrote:
>
> On Fri, May 10, 2024 at 6:29 AM Jason Wang wrote:
> >
> > On Thu, May 9, 2024 at 3:10 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Thu, May 9, 2024 at 8:27 AM Jason Wang wrote:
> > > >
> > > > On Thu, May 9, 2024 at 1:16 AM E
Migration test case is added for loongarch64 here. Since compat machine
type is required for migration test case, also compat machine qemu 9.1
is added for loongarch virt machine.
Migration test case passes to run in both tcg and kvm mode with the
patch, 54 migration subtests passes in 188 seconds
This patch adds migration test support for loongarch64. The test code
comes from aarch64 mostly, only that it booted as bios in qemu since
kernel requires elf format and bios uses binary format.
In addition to providing the binary, this patch also includes the source
code and the build script in t
Some qtest test cases such as numa use default memory size of generic
machine class, which is 128M by fault.
Here generic default memory size is used, and also remove minimum memory
size which is 1G originally.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 5 -
1 file changed, 5 deletio
Since migration test case requires compat machine type support,
compat machine is added for qemu 9.1 here.
Signed-off-by: Bibo Mao
---
hw/loongarch/virt.c | 61 +++--
1 file changed, 48 insertions(+), 13 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/
> -Original Message-
> From: Li Zhijian
> Sent: Thursday, May 9, 2024 11:31 AM
> To: Peter Xu ; Fabiano Rosas
> Cc: Zhang, Hailiang ; qemu-
> de...@nongnu.org; Zhang, Chen ; Li Zhijian
>
> Subject: [PATCH 1/3] migration/colo: Minor fix for colo error message
>
> - Explicitly show the
> -Original Message-
> From: Li Zhijian
> Sent: Thursday, May 9, 2024 11:31 AM
> To: Peter Xu ; Fabiano Rosas
> Cc: Zhang, Hailiang ; qemu-
> de...@nongnu.org; Zhang, Chen ; Li Zhijian
> ; Michael Tokarev
> Subject: [PATCH 3/3] migration/colo: Tidy up bql_unlock() around
> bdrv_activa
> -Original Message-
> From: Li Zhijian
> Sent: Thursday, May 9, 2024 11:31 AM
> To: Peter Xu ; Fabiano Rosas
> Cc: Zhang, Hailiang ; qemu-
> de...@nongnu.org; Zhang, Chen ; Li Zhijian
>
> Subject: [PATCH 2/3] migration/colo: make colo_incoming_co() return void
>
> Currently, it alwa
On 2024/5/10 18:18, Michael S. Tsirkin wrote:
> On Tue, Apr 16, 2024 at 03:01:26PM +0800, Jiqian Chen wrote:
>> Fix bug imported by 27ce0f3afc9dd25d21b43bbce505157afd93d111
>> (fix Power Management Control Register for PCI Express virtio devices)
>
>
> should be:
>
> 27ce0f3afc9dd ("fix Power Ma
This function just does two assignments and and unnecessary check that
is always true so inline it in the only caller left and remove it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 +++---
1 file changed, 3 insertions(+), 23 d
mmu40x_get_physical_address() only uses the raddr and prot fields from
mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 37 +++--
1 file changed, 15 insertions(+
Pass it as a parameter instead. Also use constant instead of hex value
when extracting bit from SR.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_comm
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 146 ++--
1 file changed, 96 insertions(+), 50 deletions(-)
diff --
Add a new mmu-booke.c file for BookE and related MMU bits from
mmu_common.c.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/cpu.h| 4 -
target/ppc/meson.build | 1 +
target/ppc/mmu-booke.c | 531
target/ppc/mmu-booke
Repurpose get_segment_6xx_tlb() to do the whole address translation
for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
renaming it to match other similar functions. These are only called
once together so no need to keep these separate functions and
combining them simplifies the ca
The ptev variable in ppc6xx_tlb_pte_check() is used only once and just
obfuscates an otherwise clear value. Get rid of it.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_c
BookE does not have real mode so split off and handle it first in
get_physical_address_wtlb() before checking for real mode for other
MMU models.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 14 +++---
1 file changed, 7 insertions(+), 7 deleti
In ppc6xx_tlb_pte_check() the pp variable is used only once to pass it
to a function parameter with the same name. Remove the local and
inline the value. Also use named constant for the hex value to make it
clearer.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 6 +++---
1 file cha
Return directly, which is simpler than dragging a return value through
multpile if and else blocks.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 84 +++--
1 file changed, 39 insertions(+), 45 deletions(-)
diff --gi
mmubooke_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 30 ++
1 file changed, 10 insertions(+), 20
In mmu6xx_get_physical_address() ds is used as bool, declare it as
such. Also use constant instead of hex value.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
i
Move the debug logging within ppc6xx_tlb_check() from after its only
call to simplify the caller.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 54 ++---
1 file changed, 24 insertions(+), 30 deletions(-)
diff --git
Move setting error_code that appears in every case out in front and
hoist the common fall through case for BOOKE206 as well which allows
removing the nested switches.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 41
In ppc_hash32_xlate() the value of need_prop is checked in two places
but precalculating it does not help because when we reach the first
check we always return and not reach the second place so the value
will only be used once. We can drop the local variable and calculate
it when needed, which mak
In mmu6xx_get_physical_address() tagtet_page_bits local is declared to
use TARGET_PAGE_BITS only once. Drop the unneeded variable.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc
Several 4xx CPUs and e200 share the same TLB settings enclosed in an
ifdef. Split it off in a common function to reduce code duplication
and the number of ifdefs.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 46 --
Add ppc_real_mode_xlate() to handle real mode translation and allow
removing this case from ppc_jumbo_xlate().
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 46 -
1 file changed, 27 insertions(+), 19 deletions(-)
diff --git a/target/ppc/mmu_
Invert conditions to avoid deep nested ifs and return early instead.
Remove some obvious comments that don't add more clarity.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 44 ++---
1 file changed, 19 insertions(+), 25 deletions(-)
diff --git a
Remove mmu_ctx_t definition from internal.h as this type is only used
within mmu_common.c.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/internal.h | 12
target/ppc/mmu_common.c | 11 +++
2 files changed, 11 insertions(+), 12 deletions(-)
diff
Checking if a page protection bit is set for a given access type is a
common operation. Add a function to avoid repeating the same check at
multiple places. As this relies on access type and page protection bit
values having certain relation also add an assert to ensure that this
assumption holds.
mmubooke206_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 32 ++--
1 file changed, 10 insertions(+
The value is only used once so no need to introduce a local variable
for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu-radix64.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index
The eaddr field of mmu_ctx_t is set once but never used so can be
removed.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 564fcc7cfb..07c127d673 100644
--- a/target/ppc/mmu_com
Now that only 6xx cases left in ppc_jumbo_xlate() we can change it
to ppc_6xx_xlate() also removing get_physical_address_wtlb().
Signed-off-by: BALATON Zoltan
---
target/ppc/internal.h | 5 +
target/ppc/mmu_common.c | 38 --
2 files changed, 13 insertio
Instead of using a local ret variable return directly and remove the
local.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 0c7cbab2bc..a035cefcad 1006
This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
hw/ppc/pegasos2.c| 2 +-
target/ppc/cpu.h | 5 -
target/ppc/c
The real mode handling is identical in the remaining switch cases.
Split off these common real mode cases into a separate conditional to
leave only the else branches in the switch that are different.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 34 +++
Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx
in ppc_jumbo_xlate() now.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 150 +---
1 file changed, 93 insertions(+), 57 deletions(-)
diff --git a/target/ppc/mmu_common.c b/targ
Merge the code fetch and data access cases in a common switch.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 52 -
1 file changed, 20 insertions(+), 32 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/
The "2" in booke206_update_mas_tlb_miss() call corresponds to
MMU_INST_FETCH which is the value of access_type in this branch;
mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
code access so using MMU_DATA_LOAD here seems wrong so replace it with
access_type here as well that y
The ptem variable in ppc6xx_tlb_pte_check() is used only once,
simplify by removing it as the value is already clear itself without
adding a local name for it.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/
The mmask local variable is a less descriptive local name for a
constant. Drop it and use the constant directly in the two places it
is needed.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common
Return hash value via a parameter and remove it from mmu_ctx.t.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 07c127d673..ccacc70ba6 100644
In mmu6xx_get_physical_address() the switch handles all cases so the
default is never reached and can be dropped. Also group together cases
which just return -4.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
In mmu6xx_get_physical_address() we have a large if block with a two
line else branch that effectively returns. Invert the condition and
move the else there to allow deindenting the large if block to make
the flow easier to follow.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
Fix several qemu_log_mask() calls that are misindented.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 42 -
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_co
This series does some further clean up mostly around BookE MMU to
untangle it from other MMU models. It also contains some other changes
that I've come up with while working on this. The Simplify
ppc_booke_xlate() part 1 and part 2 patches could be squashed together
but left them separate for easie
The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
pp_check() in mmu_common.c, merge these to remove duplicated code.
Define the common function in internal.h as static lnline otherwise
exporting the function from mmu-hash32.c would stop the compiler
inlining it which results in sligh
In ppc6xx_tlb_pte_check() the pteh variable is used only once to
compare to the h parameter of the function. Inline its value and use
pteh name for the function parameter which is more descriptive.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 7 +++
1 file changed, 3 insertion
As BookE never returns -4 we can drop BookE from the direct store case
in ppc_jumbo_xlate().
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 319
1 file changed, 159 insertions(+),
In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
value of prot2 directly to the destination, no need to have a separate
local variable for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 30 +-
1 file
From: "Dr. David Alan Gilbert"
I think it's use was removed by
Commit 5883d8b296 ("mmu-hash*: Don't use full ppc_hash{32,
64}_translate() path for get_phys_page_debug()")
Signed-off-by: Dr. David Alan Gilbert
Reviewed-by: BALATON Zoltan
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu-hash32
In get_physical_address_wtlb() the real_mode flag depends on either
the MSR[IR] or MSR[DR] bit depending on access_type. Extract just the
needed bit in a more straight forward way instead of doing unnecessary
computation.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
---
target/ppc
This function is used only once, its return value is ignored and one
of its parameter is a return value from a previous call. It is better
to inline it in the caller and remove it.
Signed-off-by: BALATON Zoltan
---
target/ppc/mmu_common.c | 41 +
1 file ch
In mmubooke_check_tlb() and mmubooke206_check_tlb() prot2 is
calculated first but only used after an unrelated check that can
return before tha value is used. Move the calculation after the check,
closer to where it is used, to keep them together and avoid computing
it when not needed.
Signed-off-
Drop MPC8xx cases from get_physical_address_wtlb() and ppc_jumbo_xlate().
The default case would still catch this and abort the same way and
there is still a warning about it in ppc_tlb_invalidate_all() which is
called in ppc_cpu_reset_hold() so likely we never get here but to make
sure add a case
The helper_rac function is defined but not used, remove it.
Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
Signed-off-by: BALATON Zoltan
Reviwed-by: Nicholas Piggin
---
target/ppc/helper.h | 2 --
target/ppc/mmu_helper.c | 24
2 files changed, 26 deletions
Yuan Liu writes:
> the qpl initialization includes memory allocation for compressed
> data and the qpl job initialization.
>
> the qpl job initialization will check if the In-Memory Analytics
> Accelerator(IAA) device is available and use the IAA device first.
> If the platform does not have IAA
Yuan Liu writes:
> the qpl initialization includes memory allocation for compressed
> data and the qpl job initialization.
>
> the qpl job initialization will check if the In-Memory Analytics
> Accelerator(IAA) device is available and use the IAA device first.
> If the platform does not have IAA
Yuan Liu writes:
> Different compression methods may require different numbers of IOVs.
> Based on streaming compression of zlib and zstd, all pages will be
> compressed to a data block, so two IOVs are needed for packet header
> and compressed data block.
>
> Signed-off-by: Yuan Liu
> Reviewed-
Hi Daniel,
On 5/10/2024 3:10 AM, Daniel P. Berrangé wrote:
On Fri, May 10, 2024 at 11:05:44AM +0300, Michael Tokarev wrote:
09.05.2024 17:11, Daniel P. Berrangé wrote:
On Thu, May 09, 2024 at 04:54:16PM +0300, Michael Tokarev wrote:
03.05.2024 20:46, Babu Moger wrote:
diff --git a/hw/i386/
On 4/24/24 21:00, Andrey Drobyshev wrote:
> Hi everyone,
>
> When making an external snapshot, we end up in a situation when 2 block
> graph nodes related to the same image file (format and storage nodes)
> have different RO flags set on them.
>
> E.g.
>
> # ls -la /proc/PID/fd
> lrwx-- 1 ro
Hi, Marc-André,
On Fri, May 10, 2024 at 12:39:34PM +0400, Marc-André Lureau wrote:
> Since we don't have per VMSD version information on the wire, nested
> struct versioning is quite limited and cumbersome. I am not sure it
> can be changed without breaking the stream format, and whether it's
> wo
On 10/5/24 19:16, Philippe Mathieu-Daudé wrote:
On 2/3/24 06:16, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/cpu.c | 3 +++
1 file changed, 3 insertions(+)
@@ -882,6 +883,8 @@ static Property sparc_cpu_properties[] = {
CPU_FEATURE_BIT_
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 11 +++
target/sparc/insns.decode | 1 +
2 files changed, 12 insertions(+)
+static void gen_op_pdistn(TCGv dst, TCGv_i64 src1, TCGv_i64 src2)
+{
+#ifdef TARGET_SPARC64
+
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 18 ++
target/sparc/insns.decode | 1 +
2 files changed, 19 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, 9 May 2024 16:35:34 +0800
Yuquan Wang wrote:
> On Wed, May 08, 2024 at 01:02:52PM +0100, Jonathan Cameron wrote:
> >
> > > [0.00] ACPI: SRAT: Node 0 PXM 0 [mem 0x4000-0xbfff]
> > > [0.00] ACPI: SRAT: Node 1 PXM 1 [mem 0xc000-0x13fff]
> > > [0.00]
On 2/3/24 06:16, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/cpu.c | 3 +++
1 file changed, 3 insertions(+)
@@ -882,6 +883,8 @@ static Property sparc_cpu_properties[] = {
CPU_FEATURE_BIT_VIS3, false),
DEFINE_PROP_BIT("ima", S
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 14 ++
target/sparc/insns.decode | 14 ++
2 files changed, 28 insertions(+)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 5f1982cecc..8
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 1 +
target/sparc/cpu.c | 3 +++
target/sparc/translate.c | 24
target/sparc/cpu-feature.h.inc | 1 +
target/sparc/insns.decode
On 2/3/24 06:15, Richard Henderson wrote:
The manual separates VIS 3 and VIS 3B, even though they are both
present in all extant cpus. For clarity, let the translator
match the manual but otherwise leave them on the same feature bit.
Signed-off-by: Richard Henderson
---
target/sparc/translat
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 2 ++
target/sparc/cpu-feature.h.inc | 1 +
2 files changed, 3 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:16, Richard Henderson wrote:
Ignore the "monitor" portion and treat them the same
as their base asis.
s/asis/ASIs/
Signed-off-by: Richard Henderson
---
target/sparc/asi.h | 4
target/sparc/ldst_helper.c | 4
target/sparc/translate.c | 8
3 files
On 5/10/24 19:12, Dmitry Osipenko wrote:
> On 5/10/24 13:56, Akihiko Odaki wrote:
>> On 2024/05/09 21:39, Dmitry Osipenko wrote:
>>> On 5/5/24 09:37, Akihiko Odaki wrote:
On 2024/05/02 4:02, Dmitry Osipenko wrote:
> On 4/27/24 08:48, Akihiko Odaki wrote:
>>>
>>> The VIRTIO_GPU_FILL
On 5/10/24 13:46, Alex Bennée wrote:
...
>> cp_portable "$tmpdir/include/asm/kvm_para.h"
>> "$output/include/standard-headers/asm-$arch"
>> +cp_portable "$tmpdir/include/asm/setup_data.h"
>> "$output/include/standard-headers/asm-$arch"
>
> is there a portable setup_data.h? why i
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 14 ++
target/sparc/insns.decode | 2 ++
2 files changed, 16 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 11 +++
target/sparc/insns.decode | 9 +
2 files changed, 20 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 3 +++
target/sparc/insns.decode | 2 ++
2 files changed, 5 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 14 ++
target/sparc/insns.decode | 3 +++
2 files changed, 17 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
On 5/10/24 13:56, Akihiko Odaki wrote:
> On 2024/05/09 21:39, Dmitry Osipenko wrote:
>> On 5/5/24 09:37, Akihiko Odaki wrote:
>>> On 2024/05/02 4:02, Dmitry Osipenko wrote:
On 4/27/24 08:48, Akihiko Odaki wrote:
>>
>> The VIRTIO_GPU_FILL_CMD() macro returns void and this macro is
>
On 2/3/24 06:15, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:15, Richard Henderson wrote:
Replace with tcg_temp_new_i64.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 2/3/24 06:15, Richard Henderson wrote:
Form the proper register decoding from the start.
Because we're removing the translation from the inner-most
gen_load_fpr_* and gen_store_fpr_* routines, this must be
done for all insns at once.
Signed-off-by: Richard Henderson
---
target/sparc/trans
07.05.2024 11:45, Michael Tokarev wrote:
07.05.2024 11:41, Michael Tokarev wrote:
The following patches are queued for QEMU stable v8.2.4:
https://gitlab.com/qemu-project/qemu/-/commits/staging-8.2
The release is planned for 2024-05-12, to address a few issues
encountered with v8.2.3 releas
Before switching to GArray/g_string_printf we used fixed size arrays for
output buffers and instructions arguments among other things.
Macros defining the sizes of these buffers were left behind, remove
them.
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
---
target/hexagon/idef-pa
Was running idef-parser with valgrind and noticed we were leaking the
init_list GArray, which is used to hold instruction arguments that may
need initialization. This patchset fixes the leak, removes unused
macros and undefined functions, and simplifies gen_inst_init_args() to
only handle predicat
Only predicate instruction arguments need to be initialized by
idef-parser. This commit removes registers from the init_list and
simplifies gen_inst_init_args() slightly.
Signed-off-by: Anton Johansson
---
target/hexagon/idef-parser/idef-parser.y| 2 --
target/hexagon/idef-parser/parser-hel
Signed-off-by: Anton Johansson
Reviewed-by: Taylor Simpson
---
target/hexagon/idef-parser/parser-helpers.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/target/hexagon/idef-parser/parser-helpers.h
b/target/hexagon/idef-parser/parser-helpers.h
index 7c58087169..2087d534a9 100
gen_inst_init_args() is called for instructions using a predicate as an
rvalue. Upon first call, the list of arguments which might need
initialization init_list is freed to indicate that they have been
processed. For instructions without an rvalue predicate,
gen_inst_init_args() isn't called and in
Cc'ing Helge & Sven as I'm going to skip this series.
Suggestion:
-- >8 --
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b79767d61..be7535b55e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -254,6 +254,8 @@ F: target/hexagon/gen_idef_parser_funcs.py
HPPA (PA-RISC) TCG CPUs
M: Richard Henderson
On 8/5/24 12:46, Salil Mehta wrote:
Hi Phillipe,
Sorry, I missed this mail earlier.
From: Philippe Mathieu-Daudé
Sent: Friday, May 3, 2024 7:23 PM
To: Salil Mehta ; qemu-devel@nongnu.org;
qemu-...@nongnu.org
On 3/5/24 17:57, Salil Mehta wrote:
> Hi Philippe,
>
>> From: P
The POWER8 LPC ISA device irqs all get combined and reported to the line
connected the PSI LPCHC irq. POWER9 changed this so only internal LPC
host controller irqs use that line, and the device irqs get routed to
4 new lines connected to PSI SERIRQ0-3.
POWER9 also introduced a new feature that aut
> -Original Message-
> From: Fabiano Rosas
> Sent: Friday, May 10, 2024 10:12 PM
> To: Liu, Yuan1 ; pet...@redhat.com
> Cc: qemu-devel@nongnu.org; Liu, Yuan1 ; Zou, Nanhai
>
> Subject: Re: [PATCH v6 4/7] migration/multifd: add qpl compression method
>
> Yuan Liu writes:
>
> > add the Q
Four mailbox properties are implemented as follows:
1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP
2. Device-specific private key: GET_PRIVATE_KEY and
SET_PRIVATE_KEY.
The customer OTP is located in the rows 36-43. The device-specific private key
is located in the rows 56-63.
The customer
All BCM2835 boards have on-board OTP memory with 66 32-bit rows. Usually,
its contents are accessible via mailbox commands.
Rayhan Faizel (3):
hw/nvram: Add BCM2835 OTP device
hw/arm: Connect OTP device to BCM2835
hw/misc: Implement mailbox properties for customer OTP and device
specific
The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.
Signed-off-by: Rayhan Faizel
---
hw/nvram/bcm2835_otp.c | 187 +
hw/nvram/meson.build | 1 +
include/h
Signed-off-by: Rayhan Faizel
---
hw/arm/bcm2835_peripherals.c | 13 -
include/hw/arm/bcm2835_peripherals.h | 3 ++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index 1695d8b453..7d735bb56c 100644
1 - 100 of 190 matches
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