Now that the log_global*() handlers take an Error** parameter and
return a bool, do the same for memory_global_dirty_log_start() and
memory_global_dirty_log_stop(). The error is reported in the callers
for now and it will be propagated in the call stack in the next
changes.
To be noted a functiona
The purpose is to record a potential error in the migration stream if
qemu_savevm_state_setup() fails. Most of the current .save_setup()
handlers can be modified to use the Error argument instead of managing
their own and calling locally error_report().
Cc: Nicholas Piggin
Cc: Harsh Prateek Bora
This prepares ground for the changes coming next which add an Error**
argument to the .save_setup() handler. Callers of qemu_savevm_state_setup()
now handle the error and fail earlier setting the migration state from
MIGRATION_STATUS_SETUP to MIGRATION_STATUS_FAILED.
In qemu_savevm_state(), move t
Hello,
The motivation behind these changes is to improve error reporting to
the upper management layer (libvirt) with a more detailed error, this
to let it decide, depending on the reported error, whether to try
migration again later. It would be useful in cases where migration
fails due to lack o
This will prepare ground for future changes adding an Error** argument
to the save_setup() handler. We need to make sure that on failure,
block_save_setup() always sets a new error.
Cc: Stefan Hajnoczi
Reviewed-by: Fabiano Rosas
Signed-off-by: Cédric Le Goater
---
Changes in v5:
- Rebased o
We will use it in ram_init_bitmaps() to clear the allocated bitmaps when
support for error reporting is added to memory_global_dirty_log_start().
Signed-off-by: Cédric Le Goater
---
migration/ram.c | 22 +++---
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/migrat
This will be useful to report errors at a higher level, mostly in VFIO
today.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
Signed-off-by: Cédric Le Goater
---
include/migration/register.h | 3 ++-
hw/vfio/migration.c | 9 +++--
migration/ram.c | 3 ++-
The .save_setup() handler has now an Error** argument that we can use
to propagate errors reported by the .log_global_start() handler. Do
that for the RAM. The caller qemu_savevm_state_setup() will store the
error under the migration stream for later detection in the migration
sequence.
Signed-off
Modify all .log_global_start() handlers to take an Error** parameter
and return a bool. Adapt memory_global_dirty_log_start() to interrupt
on the first error the loop on handlers. In such case, a rollback is
performed to stop dirty logging on all listeners where it was
previously enabled.
Cc: Stef
This will prepare ground for future changes adding an Error** argument
to qemu_savevm_state_setup().
Reviewed-by: Prasad Pandit
Signed-off-by: Cédric Le Goater
---
migration/savevm.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/migration/savev
Since the return value (-ENOMEM) is not exploited, follow the
recommendations of qapi/error.h and change it to a bool
Signed-off-by: Cédric Le Goater
---
migration/ram.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
This will prepare ground for future changes adding an Error** argument
to the save_setup() handler. We need to make sure that on failure,
set_migrationmode() always sets a new error. See the Rules section in
qapi/error.h.
Cc: Halil Pasic
Cc: Christian Borntraeger
Cc: Thomas Huth
Reviewed-by: Fa
Since the return value not exploited, follow the recommendations of
qapi/error.h and change it to a bool
Signed-off-by: Cédric Le Goater
---
migration/ram.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index
bade3e928
This will prepare ground for future changes adding an Error** argument
to the save_setup() handler. We need to make sure that on failure,
vfio_save_setup() always sets a new error.
Reviewed-by: Fabiano Rosas
Reviewed-by: Eric Auger
Signed-off-by: Cédric Le Goater
---
hw/vfio/migration.c | 15 +
This will prepare ground for future changes adding an Error** argument
to the save_setup() handler. We need to make sure that on failure,
ram_save_setup() sets a new error.
Reviewed-by: Fabiano Rosas
Signed-off-by: Cédric Le Goater
---
migration/ram.c | 11 ++-
1 file changed, 10 insert
On 19/03/2024 16.42, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/s390x-internal.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 825252d728..559c9f561d 100644
--- a/target/s390x
The current implementation treats emulated memory devices, such as
CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
(E820_TYPE_RAM). However, these emulated devices have different
characteristics than traditional DRAM, making it important to
distinguish them. Thus, we mod
Abstract `kmem_put_memory_types()` into `mt_put_memory_types()` to
accommodate various memory types and enhance flexibility,
similar to `mt_find_alloc_memory_type()`.
Signed-off-by: Ho-Ren (Jack) Chuang
---
drivers/dax/kmem.c | 7 +--
include/linux/memory-tiers.h | 6 ++
mm/m
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable
from normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes
to the same DRAM t
Tao Su writes:
> monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
> may have a parameter with NULL monitor pointer. Check the monitor pointer
> before calling monitor_puts().
>
> Fixes: bf0c50d4aa85 (monitor: expose monitor_puts to rest of code)
> Reviwed-by: Xiaoyao Li
On 3/19/24 23:56, Richard Henderson wrote:
On 3/19/24 03:32, Pierrick Bouvier wrote:
static void plugin_gen_inject(struct qemu_plugin_tb *plugin_tb)
{
- TCGOp *op;
+ TCGOp *op, *next;
int insn_idx = -1;
pr_ops();
- QTAILQ_FOREACH(op, &tcg_ctx->ops, link) {
+ /*
+
On 3/20/24 01:30, Richard Henderson wrote:
On 3/19/24 03:18, Pierrick Bouvier wrote:
On 3/16/24 05:57, Richard Henderson wrote:
The out-of-line function pointer is mutually exclusive
with inline expansion, so move it into the union.
Wrap the pointer in a structure named 'regular' to match
PLUGI
On 3/19/24 23:51, Richard Henderson wrote:
On 3/19/24 03:12, Pierrick Bouvier wrote:
On 3/16/24 05:57, Richard Henderson wrote:
TCGHelperInfo includes the ABI for every function call.
Signed-off-by: Richard Henderson
---
include/qemu/plugin.h | 1 +
plugins/core.c | 51 ++
monitor_puts() doesn't check the monitor pointer, but do_inject_x86_mce()
may have a parameter with NULL monitor pointer. Check the monitor pointer
before calling monitor_puts().
Fixes: bf0c50d4aa85 (monitor: expose monitor_puts to rest of code)
Reviwed-by: Xiaoyao Li
Signed-off-by: Tao Su
---
On 20/03/24 3:27 am, Peter Xu wrote:
On Tue, Mar 19, 2024 at 08:48:39PM +, Het Gala wrote:
'object' can return NULL if there is no socket-address, such as with a
file migration. Then the visitor code below fails and the test crashes.
Ignore and return NULL when socket-address is missing in
On Fri Mar 15, 2024 at 11:09 PM AEST, Philippe Mathieu-Daudé wrote:
> Factor ppc_add_alias_definitions() out of qmp_query_cpu_definitions()
> to clearly see the generic pattern used in all targets.
Looks equivalent.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On Fri Mar 15, 2024 at 4:44 PM AEST, Chinmay Rath wrote:
> This patch merges the definitions of the following set of fpu helper methods,
> which are similar, using macros :
>
> 1. f{add, sub, mul, div}(s)
> 2. fre(s)
> 3. frsqrte(s)
>
Reviewed-by: Nicholas Piggin
> Signed-off-by: Chinmay Rath
>
Thanks, I can put this in the ppc tree.
Thanks,
Nick
On Tue Mar 19, 2024 at 4:30 PM AEST, Philippe Mathieu-Daudé wrote:
> +Anton
>
> On 19/3/24 06:10, Philippe Mathieu-Daudé wrote:
> > 'mask', 'nlb' and 'base_addr' are all uin64_t types.
> > Use the corresponding PRIx64 format.
> >
> > Fixes: d2
On Wed Mar 20, 2024 at 1:42 AM AEST, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state(),
> unifying with the method declared in target/ppc/helper_regs.c.
Looks okay AFAIKS.
Reviewed-by: Nicholas Piggin
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
On Fri, Mar 15, 2024 at 3:59 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> The series was renamed to reflect that at this point we're fixing more
> things than just vstart management.
>
> In this new version a couple fixes were added:
>
> - patch 3 (new) fixes the memcpy endianess in 'vmvr_v', as
On Thu, Mar 7, 2024 at 7:26 PM Atish Patra wrote:
>
>
> On 3/4/24 22:47, LIU Zhiwei wrote:
> >
> > On 2024/2/29 2:51, Atish Patra wrote:
> >> Privilege mode filtering can also be emulated for cycle/instret by
> >> tracking host_ticks/icount during each privilege mode switch. This
> >> patch implem
Acked-by: Nicholas Piggin
On Wed Mar 20, 2024 at 1:42 AM AEST, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/ppc/cpu_init.c | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target
On Wed Mar 20, 2024 at 6:40 AM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > Migration reads host clocks when not holding the replay_mutex, which
> > asserts when recording a trace. It seems that these migration times
> > should be host times like other statistics in MigrationState.
>
>
On Fri, Mar 15, 2024 at 3:59 AM Daniel Henrique Barboza
wrote:
>
> We're going to make changes that will required each helper to be
> responsible for the 'vstart' management, i.e. we will relieve the
> 'vstart < vl' assumption that helpers have today.
>
> Helpers are usually able to deal with vsta
On Thu, Mar 7, 2024 at 7:22 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 3/7/24 00:45, Sunil V L wrote:
> > On Thu, Mar 07, 2024 at 11:33:25AM +1000, Alistair Francis wrote:
> >> On Thu, Mar 7, 2024 at 4:59 AM Daniel Henrique Barboza
> >> wrote:
> >>>
> >>> Hi,
> >>>
> >>> This patch break check-
On Wed Mar 20, 2024 at 3:57 AM AEST, Alex Bennée wrote:
> Nicholas Piggin writes:
>
> > replay_linux tests with virtio on aarch64 gciv3 and x86-64 q35 machines
> > seems to be more reliable now, so timeouts are no longer expected.
> > pc_i440fx, gciv2, and non-virtio still have problems, so mark t
On Wed, 2024-03-20 at 14:31 +1000, Nicholas Piggin wrote:
> On Wed Mar 20, 2024 at 11:50 AM AEST, Benjamin Gray wrote:
> > The DEXCR emulation was recently changed to a 32-bit register,
> > possibly
> > because it does have a 32-bit read-only view. It is a full 64-bit
> > SPR though, so use the cor
On Wed Mar 20, 2024 at 11:50 AM AEST, Benjamin Gray wrote:
> The GDB server protocol assigns an arbitrary numbering of the SPRs.
> We track this correspondence on each SPR with gdb_id, using it to
> resolve any SPR requests GDB makes.
>
> Early on we generate an XML representation of the SPRs to gi
On Wed Mar 20, 2024 at 11:50 AM AEST, Benjamin Gray wrote:
> The DEXCR emulation was recently changed to a 32-bit register, possibly
> because it does have a 32-bit read-only view. It is a full 64-bit
> SPR though, so use the corresponding 64-bit write functions.
>
Thanks, paper bag for me.
> Fix
On Mon, Mar 18, 2024 at 4:27 PM Stefano Garzarella wrote:
>
> On Mon, Mar 18, 2024 at 12:31:59PM +0800, Jason Wang wrote:
> >On Fri, Mar 15, 2024 at 4:23 PM Stefano Garzarella
> >wrote:
> >>
> >> On Thu, Mar 14, 2024 at 11:17:01AM +0800, Jason Wang wrote:
> >> >On Wed, Feb 7, 2024 at 5:27 PM Ste
From: Dongwon Kim
It is safer to create, initialize, and access all the parameters
in QemuDmaBuf from a central location, ui/console, instead of
hw/virtio-gpu or hw/vfio modules.
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
hw/display/virtio-gpu-udmabuf.c | 27 +++
On Wed, Mar 20, 2024 at 11:33 AM Akihiko Odaki wrote:
>
> Hi Jason,
>
> I have this and a few other network-related patches not reviewed. Can
> you review them?
> I have the following patches ready for review:
>
> https://patchew.org/QEMU/20240212-tap-v2-1-94e2ee18b...@daynix.com/
> ("[PATCH v2] t
Hi Jason,
I have this and a few other network-related patches not reviewed. Can
you review them?
I have the following patches ready for review:
https://patchew.org/QEMU/20240212-tap-v2-1-94e2ee18b...@daynix.com/
("[PATCH v2] tap-win32: Remove unnecessary stubs")
https://patchew.org/QEMU/20230
On Tue, Mar 19, 2024 at 6:16 AM Si-Wei Liu wrote:
>
>
>
> On 3/17/2024 8:22 PM, Jason Wang wrote:
> > On Sat, Mar 16, 2024 at 2:45 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 3/14/2024 9:03 PM, Jason Wang wrote:
> >>> On Fri, Mar 15, 2024 at 5:39 AM Si-Wei Liu wrote:
> On setups with one or more
On Tue, Mar 19, 2024 at 6:06 AM Si-Wei Liu wrote:
>
>
>
> On 3/17/2024 8:20 PM, Jason Wang wrote:
> > On Sat, Mar 16, 2024 at 2:33 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 3/14/2024 8:50 PM, Jason Wang wrote:
> >>> On Fri, Mar 15, 2024 at 5:39 AM Si-Wei Liu wrote:
> There could be a mix of bo
On 2024/3/20 1:30, Peter Maydell wrote:
> On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
>>
>> Support ALLINT msr access as follow:
>> mrs , ALLINT// read allint
>> msr ALLINT, // write allint with imm
>>
>> Signed-off-by: Jinjie Ruan
>> Reviewed-by: Richard H
On 2024/03/19 17:29, Marc-André Lureau wrote:
Hi Akihiko
On Tue, Mar 19, 2024 at 7:09 AM Akihiko Odaki wrote:
ui/console has a concept of "active" console; the active console is used
when NULL is set for DisplayListener::con, and console_select() updates
the active console state. However, the
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 9.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-9.0.0-rc0.tar.xz
http://download.qemu.
On 2024/3/20 0:45, Peter Maydell wrote:
> On Mon, 18 Mar 2024 at 09:37, Jinjie Ruan wrote:
>>
>> Support ALLINT msr access as follow:
>> mrs , ALLINT// read allint
>> msr ALLINT, // write allint with imm
>>
>> Signed-off-by: Jinjie Ruan
>> Reviewed-by: Richard H
How to compile QEMU with glib source code? But not with the glib library
I want to debug QEMU by stepping into glib internally.
Thanks.
On 3/18/2024 11:53 PM, Gerd Hoffmann wrote:
Query kvm for supported guest physical address bits, in cpuid
function 8008, eax[23:16]. Usually this is identical to host
physical address bits. With NPT or EPT being used this might be
restricted to 48 (max 4-level paging address space size) eve
I will rewrite the patch, and send a new version soon.
Thanks,
Huang Tao
On 2024/3/20 07:32, Richard Henderson wrote:
On 3/19/24 11:57, Daniel Henrique Barboza wrote:
This seems correct but a bit over complicated at first glance. I
wonder if we have
something simpler already done somewhere.
From: Xianglai Li
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super huge page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating syste
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Reviewed-by: Richard Henderson
Suggested-by: Richard Henderson
Signed-off-
The following changes since commit c62d54d0a8067ffb3d5b909276f7296d7df33fa7:
Update version for v9.0.0-rc0 release (2024-03-19 19:13:52 +)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240320
for you to fetch changes up to 77642f92c0b7
From: Bibo Mao
Interrupt number in loop sentence should be base irq plus
loop index, it is missing on checking whether the irq
is pending.
Fixes: 428a6ef4396 ("Add vmstate post_load support")
Signed-off-by: Bibo Mao
Reviewed-by: Song Gao
Signed-off-by: Song Gao
Message-Id: <20240313093932.265
According to table 1-2 in Intel Architecture Instruction Set Extensions and
Future Features (rev 051) [1], SierraForest has the following new features
which have already been virtualized:
- CMPCCXADD CPUID.(EAX=7,ECX=1):EAX[bit 7]
- AVX-IFMA CPUID.(EAX=7,ECX=1):EAX[bit 23]
- AVX-VNNI-INT8 CPUID.(E
1. The g_pattern_match_string() is deprecated when glib2 version >= 2.70.
Use g_pattern_spec_match_string() instead to avoid this problem.
2. The type of second parameter in g_ptr_array_add() is
'gpointer' {aka 'void *'}, but the type of reg->name is 'const char*'.
Cast the type of reg->n
The DEXCR emulation was recently changed to a 32-bit register, possibly
because it does have a 32-bit read-only view. It is a full 64-bit
SPR though, so use the corresponding 64-bit write functions.
Fixes: c9de140c2171 ("target/ppc: Fix width of some 32-bit SPRs")
Signed-off-by: Benjamin Gray
---
The GDB server protocol assigns an arbitrary numbering of the SPRs.
We track this correspondence on each SPR with gdb_id, using it to
resolve any SPR requests GDB makes.
Early on we generate an XML representation of the SPRs to give GDB,
including this numbering. However the XML is cached globally
On 3/19/24 15:39, Song Gao wrote:
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Suggested-by: Richard Henderson
Signed-o
On gen_ll, if a->imm is zero, make_address_x return src1,
but the load to destination may clobber src1. We use a new
destination to fix this problem.
Fixes: c5af6628f4be (target/loongarch: Extract make_address_i() helper)
Suggested-by: Richard Henderson
Signed-off-by: Song Gao
---
target/loonga
在 2024/3/13 下午5:39, Bibo Mao 写道:
Interrupt number in loop sentence should be base irq plus
loop index, it is missing on checking whether the irq
is pending.
Fixes: 428a6ef4396 ("Add vmstate post_load support")
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_extioi.c | 2 +-
1 file changed, 1 i
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Reported-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 7 ---
target/hppa/translate.c | 23 +--
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/target/hppa/insns.deco
Reported-by: Sven Schnelle
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 15 +--
target/hppa/translate.c | 22 ++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/i
The following changes since commit c62d54d0a8067ffb3d5b909276f7296d7df33fa7:
Update version for v9.0.0-rc0 release (2024-03-19 19:13:52 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-pa-20240319
for you to fetch changes up to
From: Sven Schnelle
stdby,e,m was writing data from the wrong half of the register
into memory for cases 0-3.
Fixes: 25460fc5a71 ("target/hppa: Implement STDBY")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Message-Id: <20240319161921.487080-7-sv...@stackframe.org>
Signed-off-by
From: Sven Schnelle
When the guest modifies the tb it is currently executing from,
it executes a fic instruction. Exit the tb on such instruction,
otherwise we might execute stale code.
Signed-off-by: Sven Schnelle
Message-Id: <20240319161921.487080-5-sv...@stackframe.org>
Signed-off-by: Richar
From: Sven Schnelle
Fixes: 96d6407f363 ("target-hppa: Implement loads and stores")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Message-Id: <20240319161921.487080-2-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 2 +-
1 file changed, 1 inse
From: Sven Schnelle
PA2.0 provides 8 instead of 4 PID registers.
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Message-Id: <20240319161921.487080-4-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 80 +++-
From: Sven Schnelle
mfia should return only the iaoq bits without privilege
bits.
Fixes: 98a9cb792c8 ("target-hppa: Implement system and memory-management insns")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Reviewed-by: Helge Deller
Message-Id: <20240319161921.487080-6-sv...@s
Tested-by: Helge Deller
Reported-by: Sven Schnelle
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 27 ---
target/hppa/translate.c | 17 +
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/hppa/insns.decode b/target/
From: Sven Schnelle
Fixes: f7b775a9c075 ("target/hppa: Implement SHRPD")
Signed-off-by: Sven Schnelle
Reviewed-by: Richard Henderson
Reviewed-by: Helge Deller
Message-Id: <20240319161921.487080-3-sv...@stackframe.org>
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 4 ++--
1 f
On Wed, Mar 20, 2024 at 08:23:39AM +0800, Xiaoyao Li wrote:
> On 3/19/2024 11:08 PM, Pawan Gupta wrote:
> > On Tue, Mar 19, 2024 at 12:22:08PM +0800, Xiaoyao Li wrote:
> > > On 3/13/2024 10:53 PM, Pawan Gupta wrote:
> > > > Register File Data Sampling (RFDS) is a CPU side-channel vulnerability
> >
On 3/19/2024 11:08 PM, Pawan Gupta wrote:
On Tue, Mar 19, 2024 at 12:22:08PM +0800, Xiaoyao Li wrote:
On 3/13/2024 10:53 PM, Pawan Gupta wrote:
Register File Data Sampling (RFDS) is a CPU side-channel vulnerability
that may expose stale register value. CPUs that set RFDS_NO bit in MSR
IA32_ARCH
On 3/19/24 11:57, Daniel Henrique Barboza wrote:
This seems correct but a bit over complicated at first glance. I wonder if we
have
something simpler already done somewhere.
Richard, does ARM (or any other arch) do anything of the sort? Aside from more
trivial
byte swaps using bswap64() I didn
On Tue, Mar 19, 2024 at 06:09:41PM -0300, Fabiano Rosas wrote:
> This reverts commit decdc76772c453ff1444612e910caa0d45cd8eac in full
> and also the relevant migration-tests from
> 7a09f092834641b7a793d50a3a261073bbb404a6.
>
> After the addition of the new QAPI-based migration address API in 8.2
>
On Tue, Mar 19, 2024 at 08:48:39PM +, Het Gala wrote:
> 'object' can return NULL if there is no socket-address, such as with a
> file migration. Then the visitor code below fails and the test crashes.
>
> Ignore and return NULL when socket-address is missing in the reply so
> we don't break fu
(--- CCing Richard ---)
On 3/6/24 06:20, Huang Tao wrote:
We add vext_set_elems_1s to set agnostic elements to 1s in both big
and little endian situation.
In the function vext_set_elems_1s. We using esz argument to get the first
element to set. 'cnt' is just idx * esz.
Signed-off-by: Huang Tao
On Tue, Mar 19, 2024 at 08:48:40PM +, Het Gala wrote:
> Signed-off-by: Het Gala
> ---
> tests/qtest/migration-helpers.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/qtest/migration-helpers.c b/tests/qtest/migration-helpers.c
> index fb7156f09a..651c6c555a 10
On 3/6/24 06:20, Huang Tao wrote:
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. We rename the
function, addi
On 3/19/24 03:18, Pierrick Bouvier wrote:
On 3/16/24 05:57, Richard Henderson wrote:
The out-of-line function pointer is mutually exclusive
with inline expansion, so move it into the union.
Wrap the pointer in a structure named 'regular' to match
PLUGIN_CB_REGULAR.
Signed-off-by: Richard Hender
On 3/19/24 12:42, Philippe Mathieu-Daudé wrote:
Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
Note, now riscv_get_cpu_state() is restricted to TCG, and
is declared with static scope.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Daniel Henrique Barboza
targe
Hi all!
From fuzzing I've got a fuzz-data, which produces the following crash:
qemu-fuzz-x86_64: ../hw/net/virtio-net.c:134: void
flush_or_purge_queued_packets(NetClientState *): Assertion
`!virtio_net_get_subqueue(nc)->async_tx.elem' failed.
==2172308== ERROR: libFuzzer: deadly signal
#0
On 3/19/24 04:04, Alex Bennée wrote:
Richard Henderson writes:
Allow operations to be emitted via normal expanders
into the middle of the opcode stream.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 14 --
2 files changed, 13 insertions(+)
Hi Jason,
Care to re-send please? The patches don't apply to neither riscv-to-apply.next
nor master.
Thanks,
Daniel
On 3/19/24 13:23, Jason Chien wrote:
Ping. Can anyone review the patches please?
Jason Chien mailto:jason.ch...@sifive.com>> 於
2024年3月7日 週四 上午1:09寫道：
Add support for Zve
On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (27):
accel/tcg: Ensure frontends define restore_state_to_opc handler
accel/tcg: Introduce TCGCPUOps::get_cpu_state() handler
target/alpha: Convert to TCGCPUOps::get_cpu_state()
target/arm: Restrict TCG-specific de
On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
Signed-off-by: Philippe Mathieu-Daudé
---
target/sparc/cpu.h | 37 ++---
target/sparc/cpu.c | 1 +
target/sparc/translate.c | 33
This reverts commit decdc76772c453ff1444612e910caa0d45cd8eac in full
and also the relevant migration-tests from
7a09f092834641b7a793d50a3a261073bbb404a6.
After the addition of the new QAPI-based migration address API in 8.2
we've been converting an "fd:" URI into a SocketAddress, missing the
fact
On Tue, Mar 19, 2024 at 07:28:55AM +0100, Philippe Mathieu-Daudé wrote:
> The Exception Address Register is 64-bit wide.
> User emulation only access the 32 lower bits.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microblaze/cpu.h | 2 +-
> li
On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
Note, now s390x_get_cpu_state() is restricted to TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cpu.h| 30 --
target/s390x/s390x-
On 3/19/24 05:42, Philippe Mathieu-Daudé wrote:
+static inline void x86_get_cpu_state(CPUX86State *env, vaddr *pc,
Remove inline.
r~
On Tue, Mar 19, 2024 at 07:28:54AM +0100, Philippe Mathieu-Daudé wrote:
> MMU helpers are only used during system emulation,
> move them to sys_helper.c.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microblaze/op_helper.c | 48 -
On Tue, Mar 19, 2024 at 07:28:53AM +0100, Philippe Mathieu-Daudé wrote:
> helper.c only contains system emulation helpers,
> rename it as sys_helper.c.
> Adapt meson and remove pointless #ifdef'ry.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microb
On Tue, Mar 19, 2024 at 07:28:51AM +0100, Philippe Mathieu-Daudé wrote:
> cpu_pc and jmp_dest are 32-bit.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microblaze/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/t
On Tue, Mar 19, 2024 at 07:28:50AM +0100, Philippe Mathieu-Daudé wrote:
> Use 'vaddr' type for virtual addresses.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microblaze/mmu.h | 2 +-
> target/microblaze/mmu.c | 2 +-
> 2 files changed, 2 insertion
On 20/03/24 12:33 am, Fabiano Rosas wrote:
Het Gala writes:
On 18/03/24 7:46 pm, Fabiano Rosas wrote:
Het Gala writes:
On 15/03/24 6:28 pm, Fabiano Rosas wrote:
Het Galawrites:
Refactor migrate_get_socket_address to internally utilize 'socket-address'
parameter, reducing redundanc
FYI: This 2 patches are rebased on top of another
(tests/qtest/migration: Add tests for introducing 'channels' argument in
migrate QAPIs) series.
Can find the build for both the patches here:
https://gitlab.com/galahet/Qemu/-/pipelines/1219841944
On 20/03/24 2:18 am, Het Gala wrote:
'object'
Nicholas Piggin writes:
> The x86-64 pc machine has a problem with record/replay. q35 seems
> to work well. Add a new q35 test and update the flaky message for
> pc.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @
Nicholas Piggin writes:
> An error path missed setting *errp, which can cause a NULL deref.
>
> Signed-off-by: Nicholas Piggin
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
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