On Wed, 2024-03-20 at 14:31 +1000, Nicholas Piggin wrote:
> On Wed Mar 20, 2024 at 11:50 AM AEST, Benjamin Gray wrote:
> > The DEXCR emulation was recently changed to a 32-bit register,
> > possibly
> > because it does have a 32-bit read-only view. It is a full 64-bit
> > SPR though, so use the corresponding 64-bit write functions.
> >
>
> Thanks, paper bag for me.
>
> > Fixes: c9de140c2171 ("target/ppc: Fix width of some 32-bit SPRs")
>
> Should that hash be fbda88f7abdee?
>
Oops, yeah, somehow pasted the local commit hash for this patch itself
> Reviewed-by: Nicholas Piggin <npig...@gmail.com>
>
> > Signed-off-by: Benjamin Gray <bg...@linux.ibm.com>
> > ---
> > target/ppc/cpu_init.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> > index 7e65f08147..22fdea093b 100644
> > --- a/target/ppc/cpu_init.c
> > +++ b/target/ppc/cpu_init.c
> > @@ -5820,7 +5820,7 @@ static void
> > register_power10_dexcr_sprs(CPUPPCState *env)
> > {
> > spr_register(env, SPR_DEXCR, "DEXCR",
> > SPR_NOACCESS, SPR_NOACCESS,
> > - &spr_read_generic, &spr_write_generic32,
> > + &spr_read_generic, &spr_write_generic,
> > 0);
> >
> > spr_register(env, SPR_UDEXCR, "UDEXCR",
> > @@ -5831,7 +5831,7 @@ static void
> > register_power10_dexcr_sprs(CPUPPCState *env)
> > spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
> > SPR_NOACCESS, SPR_NOACCESS,
> > SPR_NOACCESS, SPR_NOACCESS,
> > - &spr_read_generic, &spr_write_generic32,
> > + &spr_read_generic, &spr_write_generic,
> > 0);
> >
> > spr_register(env, SPR_UHDEXCR, "UHDEXCR",
>
