On 3/6/24 21:48, Philippe Mathieu-Daudé wrote:
> On 6/3/24 21:32, Eric Auger wrote:
>> Document the new aw-bits option.
>>
>> Signed-off-by: Eric Auger
>> Reviewed-by: Cédric Le Goater
>>
>> ---
>>
>> v4 -> v5
>> - tweek the aw-bits option description according to Cédric's
>> suggestion
>>
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical
in
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super large page (page size is 1G) to create the page
table,
it is found that the content of the corresponding address space is abnormal,
resulting in the bios can not start the operating system and graphical
in
On 3/6/2024 9:26 PM, Wu, Fei wrote:
> On 3/5/2024 1:58 PM, Wu, Fei wrote:
>> On 3/5/2024 3:43 AM, Daniel Henrique Barboza wrote:
>>>
>>>
>>> On 3/4/24 07:25, Fei Wu wrote:
The harts requirements of RISC-V server platform [1] require RVA23 ISA
profile support, plus Sv48, Svadu, H, Sscofmpf
On 3/6/24 21:45, Philippe Mathieu-Daudé wrote:
> On 6/3/24 21:32, Eric Auger wrote:
>> aw-bits is a new option that allows to set the bit width of
>> the input address range. This value will be used as a default for
>> the device config input_range.end. By default it is set to 64 bits
>> which i
Hi Philippe,
On 3/6/24 21:44, Philippe Mathieu-Daudé wrote:
> On 6/3/24 21:32, Eric Auger wrote:
>> We are missing an entry for the virtio-iommu-pci device. Add the
>> information on which machine it is currently supported and document
>> the new granule option.
>>
>> Signed-off-by: Eric Auger
>>
On 3/6/24 21:51, Philippe Mathieu-Daudé wrote:
On 6/3/24 14:34, Cédric Le Goater wrote:
It will simplify the changes coming after.
Signed-off-by: Cédric Le Goater
---
hw/vfio/common.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/vfio/common.
Hi Philippe,
> In a previous community call, Zhao asked us how his work will scale
> in the heterogeneous context.
>
> My first idea is CPUs must belong to a cluster.
Thank you for considering this!
At present, cluster is a arch-specific topology level used by ARM.
So maybe we need call this ab
On Thu, Mar 07, 2024 at 07:22:10AM +0100, Thomas Huth wrote:
> Date: Thu, 7 Mar 2024 07:22:10 +0100
> From: Thomas Huth
> Subject: Re: [PATCH 02/14] hw/core/machine-smp: Deprecate unsupported
> "parameter=1" SMP configurations
>
> On 06/03/2024 10.53, Zhao Liu wrote:
> > From: Zhao Liu
> >
> >
Hi Thomas,
> > /*
> > - * config: -smp 512
> > + * config: -smp 4096
> >* The test machine should tweak the supported max CPUs to
> > - * 511 (MAX_CPUS - 1) for testing.
> > + * 4095 (MAX_CPUS - 1) for testing.
> >*/
> > -.c
> -Original Message-
> From: Fabiano Rosas
> Sent: Wednesday, March 6, 2024 7:56 PM
> To: Liu, Yuan1 ; pet...@redhat.com
> Cc: qemu-devel@nongnu.org; hao.xi...@bytedance.com;
> bryan.zh...@bytedance.com; Zou, Nanhai
> Subject: RE: [PATCH v4 3/8] configure: add --enable-qpl build option
>
On 3/5/2024 5:10 PM, Isaku Yamahata wrote:
On Thu, Feb 29, 2024 at 01:36:29AM -0500,
Xiaoyao Li wrote:
From: Chao Peng
When geeting KVM_EXIT_MEMORY_FAULT exit, it indicates userspace needs to
do the memory conversion on the RAMBlock to turn the memory into desired
attribute, i.e., private/sh
On 3/7/2024 8:48 AM, Alistair Francis wrote:
> On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra wrote:
>>
>> On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
>>>
>>> On 3/6/2024 8:19 AM, Alistair Francis wrote:
On Mon, Mar 4, 2024 at 8:28 PM Fei Wu wrote:
>
> The RISC-V Server Platform
On 06/03/2024 10.53, Zhao Liu wrote:
From: Zhao Liu
Currentlt, it was allowed for users to specify the unsupported
s/Currentlt/Currently/
topology parameter as "1". For example, x86 PC machine doesn't
support drawer/book/cluster topology levels, but user could specify
"-smp drawers=1,books=
On 06/03/2024 10.54, Zhao Liu wrote:
From: Zhao Liu
The support for "parameter=0" SMP configurations is removed, and QEMU
returns error for those cases.
So add the related test cases to ensure parameters can't accept 0.
Signed-off-by: Zhao Liu
---
tests/unit/test-smp-parse.c | 92 +
On 06/03/2024 10.54, Zhao Liu wrote:
From: Zhao Liu
Since s390 machine supports both "drawers" and "books" in -smp, add the
"drawers" and "books" combination test case to match the actual topology
usage scenario.
Signed-off-by: Zhao Liu
Tested-by: Xiaoling Song
---
tests/unit/test-smp-pars
On 06/03/2024 10.54, Zhao Liu wrote:
From: Zhao Liu
The q35 machine is trying to support up to 4096 vCPUs [1], so it's
necessary to bump max_cpus in test-smp-parse to 4096 to cover the
topological needs of future machines.
[1]:
https://lore.kernel.org/qemu-devel/20240228143351.3967-1-anisi...
> On 06-Mar-2024, at 12:11, Ani Sinha wrote:
>
>
>
> On Tue, 5 Mar 2024, Igor Mammedov wrote:
>
>> currently smbios_entry_add() preserves internally '-smbios type='
>> options but tables provided with '-smbios file=' are stored directly
>> into blob that eventually will be exposed to VM. An
On Thu, Mar 07, 2024 at 11:33:25AM +1000, Alistair Francis wrote:
> On Thu, Mar 7, 2024 at 4:59 AM Daniel Henrique Barboza
> wrote:
> >
> > Hi,
> >
> > This patch break check-qtest, most specifically 'bios-table'test', for
> > aarch64.
> > I found this while running riscv-to-apply.next in the Git
On Thu, Mar 07, 2024 at 02:41:37AM +, Zhijian Li (Fujitsu) via wrote:
> Yu,
>
>
> On 07/03/2024 00:30, Philippe Mathieu-Daudé wrote:
> > Cc'ing RDMA migration reviewers/maintainers:
> >
> > $ ./scripts/get_maintainer.pl -f migration/rdma.c
> > Li Zhijian (reviewer:RDMA Migration)
> > Peter
Check that the value matches opcode_reginfo/opcode_wregs
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 1 +
target/hexagon/decode.c | 2 ++
target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
target/hexagon/gen_trans_funcs.py | 6 ++
4 files ch
This data structure is not used
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.c| 7
target/hexagon/README | 1 -
target/hexagon/gen_shortcode.py | 63 -
target/hexagon/meson.build | 10 --
4 files changed, 81 deletions(
Check that the value matches opcode_reginfo
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 3 ++-
target/hexagon/decode.c | 2 ++
target/hexagon/mmvec/decode_ext_mmvec.c | 2 ++
target/hexagon/gen_trans_funcs.py | 15 ++-
4 files
The attribinfo data structure is not used
Adjust the command-line arguments to the python scripts
Add hex_common.read_common_files for TCG/helper generation scripts
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_analyze_funcs.py | 21 ++-
target/hexagon/gen_helper_funcs.py
Signed-off-by: Taylor Simpson
Reviewed-by: Philippe Mathieu-Daudé
---
target/hexagon/hex_common.py | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py
index 195620c7ec..4bacef223f 100755
--- a/target/hexag
Check that the value matches opcode_wregs
Signed-off-by: Taylor Simpson
---
target/hexagon/insn.h | 1 +
target/hexagon/decode.c | 3 +++
target/hexagon/gen_trans_funcs.py | 5 +
3 files changed, 9 insertions(+)
diff --git a/target/hexagon/insn.h b/target/hexagon/insn.
Make sure the decoding of HVX .new is correctly handling this case
Signed-off-by: Taylor Simpson
---
tests/tcg/hexagon/hvx_misc.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c
index b45170acd1..1fe
During .new decode, there are several places where strchr is used.
We remove these by generating the values that are needed.
Once we have generated the proper values, we no longer need
op_regs_generated.h.inc. We remove the script that generates it as
well as the code in meson.build
We also remo
Signed-off-by: Taylor Simpson
---
target/hexagon/opcodes.h| 4 --
target/hexagon/decode.c | 57 +++--
target/hexagon/mmvec/decode_ext_mmvec.c | 34 +++
target/hexagon/opcodes.c| 28
4 files changed, 13 i
Signed-off-by: Taylor Simpson
---
target/hexagon/README | 1 -
target/hexagon/gen_op_regs.py | 125 --
target/hexagon/meson.build| 14 +---
3 files changed, 2 insertions(+), 138 deletions(-)
delete mode 100755 target/hexagon/gen_op_regs.py
diff --g
>>
>> [1] ACPI Spec 6.3, Section 5.2.16.6
>> [2] ACPI Spec 6.3, Table 5.80
>>
>> Cc: Jonathan Cameron
>> Cc: Alex Williamson
>> Cc: Cedric Le Goater
>> Signed-off-by: Ankit Agrawal
>
> I guess we gloss over the bisection breakage due to being able to add
> these nodes and have them used in HMAT
>> -object acpi-generic-initiator,id=gi14,pci-dev=dev1,node=16 \
>> -object acpi-generic-initiator,id=gi15,pci-dev=dev1,node=17 \
>>
>> The performance benefits can be realized by providing the NUMA node distances
>> appropriately (through libvirt tags or Qemu params). The admin can get the
>> dis
Yu,
On 07/03/2024 00:30, Philippe Mathieu-Daudé wrote:
> Cc'ing RDMA migration reviewers/maintainers:
>
> $ ./scripts/get_maintainer.pl -f migration/rdma.c
> Li Zhijian (reviewer:RDMA Migration)
> Peter Xu (maintainer:Migration)
> Fabiano Rosas (maintainer:Migration)
>
> On 5/3/24 22:32, Yu
On Wed, Feb 28, 2024 at 10:14 PM Hiroaki Yamamoto wrote:
>
> G-stage translation should be considered to be user-level access in
> riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().
>
> This fixes a bug that prevents gdb from reading memory while the VM is
> running in VS-
Hi Alistair,
Please also take a look at this series, I guess it is ready to be applied,
thanks!
BRs,
Alvin
> -Original Message-
> From: Alvin Che-Chia Chang(張哲嘉)
> Sent: Tuesday, February 27, 2024 9:24 AM
> To: qemu-ri...@nongnu.org; qemu-devel@nongnu.org
> Cc: alistair.fran...@wdc.co
On Wed, Feb 28, 2024 at 10:14 PM Hiroaki Yamamoto wrote:
>
> G-stage translation should be considered to be user-level access in
> riscv_cpu_get_phys_page_debug(), as already done in riscv_cpu_tlb_fill().
>
> This fixes a bug that prevents gdb from reading memory while the VM is
> running in VS-
On Wed, Mar 6, 2024 at 7:57 PM Anup Patel wrote:
>
> Few fixes for RISC-V APLIC discovered during Linux AIA patch reviews.
>
> These patches can also be found in the apatel_aplic_fixes_v1 branch at:
> https://github.com/avpatel/qemu.git
>
> Anup Patel (2):
> hw/intc/riscv_aplic: Fix setipnum_le
> -Original Message-
> From: Alistair Francis
> Sent: Thursday, March 7, 2024 9:33 AM
> To: Daniel Henrique Barboza
> Cc: JeeHeng Sia ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org; qemu-ri...@nongnu.org;
> m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com;
> peter.mayd...@lin
Hi huacai:
Hi, Xianglai,
How to pass the BIOS file to qemu after this patch? With the old
cmdline I get an RCU stall and freeze the kvm host.
The bios also has the corresponding code modification,
you can update the code from the UEFI community to recompile UEFI,
or you can directly obtain
On Thu, Mar 7, 2024 at 4:59 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This patch break check-qtest, most specifically 'bios-table'test', for
> aarch64.
> I found this while running riscv-to-apply.next in the Gitlab pipeline.
>
>
> Here's the output:
>
> $ make -j && QTEST_QEMU_BINARY=./qemu-s
On Mon, Feb 26, 2024 at 3:42 AM demin.han wrote:
>
> The result of (8 - 3 - vlmul) is negative when vlmul >= 6,
> and results in wrong vill.
>
> Signed-off-by: demin.han
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> Changes in v2:
> - Add vlen var
>
> Changes in v3:
> - Fix commit m
Thanks a lot for you respond me soon!
The exact instruction is mrc, and the exception happended in early boot
process. I have no idea to how to debug this error because it happended in
code_gen_prologue.
I need to comform that whether QEMU A55 fully supports aarch32 mode. If it
need me to add addit
From: Huai-Cheng Kuo
SPDM enables authentication, attestation and key exchange to assist in
providing infrastructure security enablement. It's a standard published
by the DMTF [1].
SPDM supports multiple transports, including PCIe DOE and MCTP.
This patch adds support to QEMU to connect to an ex
From: Wilfred Mallawa
Setup Data Object Exchance (DOE) as an extended capability for the NVME
controller and connect SPDM to it (CMA) to it.
Signed-off-by: Wilfred Mallawa
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
Acked-by: Klaus Jensen
---
docs/specs/index.rst|
The Security Protocol and Data Model (SPDM) Specification defines
messages, data objects, and sequences for performing message exchanges
over a variety of transport and physical media.
-
https://www.dmtf.org/sites/default/files/standards/documents/DSP0274_1.3.0.pdf
SPDM currently supports PCIe D
Add all of the defined protocols/features from the PCIe-SIG r6.0
"Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
table.
Signed-off-by: Alistair Francis
Reviewed-by: Jonathan Cameron
---
include/hw/pci/pcie_doe.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/hw
On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra wrote:
>
> On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
> >
> > On 3/6/2024 8:19 AM, Alistair Francis wrote:
> > > On Mon, Mar 4, 2024 at 8:28 PM Fei Wu wrote:
> > >>
> > >> The RISC-V Server Platform specification[1] defines a standardized set
>
On Thu, Mar 7, 2024 at 3:20 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This version is rebased on top of alistair/riscv-to-apply.next, fixing
> onflicts with the Ztso changes in ldst_us_trans().
>
> No other changes made. All patches acked.
>
> v6 link:
> https://lore.kernel.org/qemu-riscv/202
On Tue, Mar 05, 2024 at 04:56:29PM -0300, Fabiano Rosas wrote:
> Commit bc38feddeb ("io: fsync before closing a file channel") added a
> fsync/fdatasync at the closing point of the QIOChannelFile to ensure
> integrity of the migration stream in case of QEMU crash.
>
> The decision to do the sync a
Yes, you’re right, QEMU >=6.0.0 works well, I failed test because I did it on
QEMU 4.2.1
From: Daniel P. Berrangé
Date: Wednesday, March 6, 2024 at 22:43
To: Chun Feng Wu , qemu-devel@nongnu.org
Subject: [EXTERNAL] Re: Does "-object" support structured options now?
On Wed, Mar 06, 2024 at 02:3
On Wed, Mar 06, 2024 at 05:48:11PM +, Jonathan Cameron wrote:
> On Mon, 4 Mar 2024 11:34:04 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Since fabric manager emulation is not supported yet, the change implements
> > the functions to add/release dynamic capacity extents as Q
On Wed, Mar 06, 2024 at 05:48:11PM +, Jonathan Cameron wrote:
> On Mon, 4 Mar 2024 11:34:04 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Since fabric manager emulation is not supported yet, the change implements
> > the functions to add/release dynamic capacity extents as Q
On 1/25/24 17:19, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Some Windows versions crash at boot or fail to enable the VMBus device if
they don't see the expected set of Hyper-V features (enlightenments).
Since this provides poor user experience let's warn user if the VMBus
device
On 3/4/24 02:54, Xiaoyao Li wrote:
On 3/1/2024 6:17 PM, Gerd Hoffmann wrote:
query kvm for supported guest physical address bits using
KVM_CAP_VM_GPA_BITS. Expose the value to the guest via cpuid
(leaf 0x8008, eax, bits 16-23).
Signed-off-by: Gerd Hoffmann
---
target/i386/cpu.h | 1
On Wed, Mar 06, 2024 at 05:28:27PM +, Jonathan Cameron wrote:
> On Mon, 4 Mar 2024 11:34:03 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Per CXL spec 3.1, two mailbox commands are implemented:
> > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> > Release Dyn
From: Dongwon Kim
The guest surface needs to be updated with a blob scanout after resumed
from saved vm state if blob is enabled.
v2: Rebased
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
hw/display/virtio-gpu.c | 21 ++---
1 file changed, 14 inser
From: Dongwon Kim
If the guest state is paused before it gets a response for the current
scanout frame submission (resource-flush), it won't flush new frames
after being restored as it still waits for the old response, which is
accepted as a scanout render done signal. So it's needed to unblock
t
On Wed, Mar 06, 2024 at 05:28:27PM +, Jonathan Cameron wrote:
> On Mon, 4 Mar 2024 11:34:03 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Per CXL spec 3.1, two mailbox commands are implemented:
> > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> > Release Dyn
On 06/03/24 9:31 pm, Fabiano Rosas wrote:
Het Gala writes:
On 06/03/24 8:06 pm, Fabiano Rosas wrote:
Het Gala writes:
Add a migrate_set_ports() function that from each QDict, fills in
the port in case it was 0 in the test.
Handle a list of channels so we can add a negative test that
pass
Hello, thank you for the post.
The href in the link
https://kubevirt.io/user-guide/debug_virt_stack/";>Virtualization
Debugging
should be replaced by
https://kubevirt.io/user-guide/debug_virt_stack/logging/
Best,
Alexei
Hi Stefan, you made the update swiftly;-)
BTW thank you for your meaningful posts.
Best,
Alexei
> On 06/03/2024 21:04 CET Stefan Hajnoczi wrote:
>
>
> On Wed, 6 Mar 2024 at 14:52, wrote:
> >
> > Hello, thank you for the post.
> >
> > The href in the link
> > https://kubevirt.io/user-guide/d
Hi,
On 6/3/24 10:53, Zhao Liu wrote:
From: Zhao Liu
Hi all,
To make review easier, I've merged my previous single SMP patch [1] and
SMP test series [2] into this series as well.
So this series includes:
* [Patch 1] Remove deprecated "parameter=0" SMP configurations, which
is marked as
On Fri, Mar 01, 2024 at 05:04:54PM +, Alex Bennée wrote:
> Vikram Garhwal writes:
>
> > From: Juergen Gross
> >
> > qemu_map_ram_ptr() and qemu_ram_ptr_length() share quite some code, so
> > modify qemu_ram_ptr_length() a little bit and use it for
> > qemu_map_ram_ptr(), too.
> >
> > Signed-
Hi Alex,
On Fri, Mar 01, 2024 at 05:10:28PM +, Alex Bennée wrote:
> Vikram Garhwal writes:
>
> > Enable grant ram mapping support for Xenpvh machine on ARM.
> >
> > Signed-off-by: Vikram Garhwal
> > Reviewed-by: Stefano Stabellini
> > ---
> > hw/arm/xen_arm.c | 3 +++
> > 1 file changed, 3
On 6/3/24 10:53, Zhao Liu wrote:
From: Zhao Liu
In machine_parse_smp_config(), the number of total CPUs is calculated
by:
drawers * books * sockets * dies * clusters * cores * threads
To avoid missing the future new topology level, use a local variable to
cache the calculation result so
On 6/3/24 14:34, Cédric Le Goater wrote:
It will simplify the changes coming after.
Signed-off-by: Cédric Le Goater
---
hw/vfio/common.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index
5b2e6a179cdd5f8ca5be
On 6/3/24 21:32, Eric Auger wrote:
Document the new aw-bits option.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
---
v4 -> v5
- tweek the aw-bits option description according to Cédric's
suggestion
---
qemu-options.hx | 3 +++
1 file changed, 3 insertions(+)
diff --git a/qe
On 6/3/24 21:32, Eric Auger wrote:
aw-bits is a new option that allows to set the bit width of
the input address range. This value will be used as a default for
the device config input_range.end. By default it is set to 64 bits
which is the current value.
Signed-off-by: Eric Auger
Reviewed-by:
On 6/3/24 21:32, Eric Auger wrote:
We are missing an entry for the virtio-iommu-pci device. Add the
information on which machine it is currently supported and document
the new granule option.
Signed-off-by: Eric Auger
---
qemu-options.hx | 8
1 file changed, 8 insertions(+)
diff --
On 6/3/24 18:19, Daniel Henrique Barboza wrote:
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henr
This is a respin of
[1] [PATCH v5 0/4] VIRTIO-IOMMU: Introduce an aw-bits option
(https://lore.kernel.org/all/20240215084315.863897-1-eric.au...@redhat.com/)
which now also integrates
[PATCH v6 0/3] VIRTIO-IOMMU: Set default granule to host page size
(https://lore.kernel.org/all/20240227165730.14
Document the new aw-bits option.
Signed-off-by: Eric Auger
Reviewed-by: Cédric Le Goater
---
v4 -> v5
- tweek the aw-bits option description according to Cédric's
suggestion
---
qemu-options.hx | 3 +++
1 file changed, 3 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 75
We used to set the default granule to 4KB but with VFIO assignment
it makes more sense to use the actual host page size.
Indeed when hotplugging a VFIO device protected by a virtio-iommu
on a 64kB/64kB host/guest config, we current get a qemu crash:
"vfio: DMA mapping failed, unable to continue"
aw-bits is a new option that allows to set the bit width of
the input address range. This value will be used as a default for
the device config input_range.end. By default it is set to 64 bits
which is the current value.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric L
Currently the default input range can extend to 64 bits. On x86,
when the virtio-iommu protects vfio devices, the physical iommu
may support only 39 bits. Let's set the default to 39, as done
for the intel-iommu.
We use hw_compat_8_2 to handle the compatibility for machines
before 9.0 which used t
We are missing an entry for the virtio-iommu-pci device. Add the
information on which machine it is currently supported and document
the new granule option.
Signed-off-by: Eric Auger
---
qemu-options.hx | 8
1 file changed, 8 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
This allows to choose which granule will be used by
default by the virtio-iommu. Current page size mask
default is qemu_target_page_mask so this translates
into a 4k granule on ARM and x86_64 where virtio-iommu
is supported.
Signed-off-by: Eric Auger
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-
Introduce a new enum type property allowing to set an
IOMMU granule. Values are 4k, 8k, 16k, 64k and host.
This latter indicates the vIOMMU granule will match
the host page size.
A subsequent patch will add such a property to the
virtio-iommu device.
Signed-off-by: Eric Auger
Signed-off-by: Phil
Use %u format to trace domain_range limits.
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
Reviewed-by: Cédric Le Goater
---
hw/virtio/trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
index 77905d1994..23508
On ARM we set 48b as a default (matching SMMUv3 SMMU_IDR5.VAX == 0).
hw_compat_8_2 is used to handle the compatibility for machine types
before 9.0 (default was 64 bits).
Signed-off-by: Eric Auger
Reviewed-by: Zhenzhong Duan
---
v6 -> v7
turn arm_virt_compat and arm_virt_compat_len static
---
On Wed, 6 Mar 2024 at 15:09, wrote:
> BTW thank you for your meaningful posts.
Thanks for the kind words!
Stefan
On Wed, 6 Mar 2024 at 14:52, wrote:
>
> Hello, thank you for the post.
>
> The href in the link
> https://kubevirt.io/user-guide/debug_virt_stack/";>Virtualization
> Debugging
>
> should be replaced by
> https://kubevirt.io/user-guide/debug_virt_stack/logging/
Hi Alexei,
Thanks for pointing out
On 3/6/24 15:57, Daniel Henrique Barboza wrote:
As a side note, it seems like 'bios-table-test' isn't being run for RISC-V. Not
sure if this
is intentional or a foresight.
s/foresight/hindsight
There's no 'make check' for what we want to say in the ML but hopefully there's
a way to enable
On 06/03/24 9:31 pm, Fabiano Rosas wrote:
Het Gala writes:
On 06/03/24 8:06 pm, Fabiano Rosas wrote:
Het Gala writes:
Add a migrate_set_ports() function that from each QDict, fills in
the port in case it was 0 in the test.
Handle a list of channels so we can add a negative test that
pass
On Wed, Mar 06, 2024 at 04:28:16PM +, Jonathan Cameron wrote:
> On Mon, 4 Mar 2024 11:34:01 -0800
> nifan@gmail.com wrote:
>
> > From: Fan Ni
> >
> > Add (file/memory backed) host backend, all the dynamic capacity regions
> > will share a single, large enough host backend. Set up addres
On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
>
> On 3/6/2024 8:19 AM, Alistair Francis wrote:
> > On Mon, Mar 4, 2024 at 8:28 PM Fei Wu wrote:
> >>
> >> The RISC-V Server Platform specification[1] defines a standardized set
> >> of hardware and software capabilities, that portable system softwar
HI Yuquan,
For your test, the first logging will come from the AER driver if
everything is working correctly.
You may want to check if the upstream pci bridge's AER UIE/CIE
masks are set. This could prevent the error from handled by the OS's
aer driver.
Regards,
Terry
On 3/6/24 11:12, Terry B
Hi,
This patch break check-qtest, most specifically 'bios-table'test', for aarch64.
I found this while running riscv-to-apply.next in the Gitlab pipeline.
Here's the output:
$ make -j && QTEST_QEMU_BINARY=./qemu-system-aarch64 V=1
./tests/qtest/bios-tables-test
TAP version 13
# random seed: R
On Wed, Feb 14, 2024 at 2:02 PM Si-Wei Liu wrote:
>
> On setups with one or more virtio-net devices with vhost on,
> dirty tracking iteration increases cost the bigger the number
> amount of queues are set up e.g. on idle guests migration the
> following is observed with virtio-net with vhost=on:
On 06/03/24 8:37 pm, Fabiano Rosas wrote:
Het Gala writes:
Add a positive test to check multifd live migration but this time
using list of channels (restricted to 1) as the starting point
instead of simple uri string.
Signed-off-by: Het Gala
Suggested-by: Fabiano Rosas
---
tests/qtest/migr
On 05/03/2024 14.42, Philippe Mathieu-Daudé wrote:
PCMachineClass::acpi_data_size was only used by the pc-i440fx-2.0
machine, which got removed. Since it is constant, replace the class
field by a definition.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/i386/pc.h | 4
hw/i386/pc
On 05/03/2024 14.42, Philippe Mathieu-Daudé wrote:
X86CPU::kvm_no_smi_migration was only used by the
pc-i440fx-2.3 machine, which got removed. Remove it
and simplify kvm_put_vcpu_events().
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h | 3 ---
target/i386/cpu.c | 2 --
On 05/03/2024 14.42, Philippe Mathieu-Daudé wrote:
The pc-i440fx-2.2 machine was deprecated for the 8.2
release (see commit c7437f0ddb "docs/about: Mark the
old pc-i440fx-2.0 - 2.3 machine types as deprecated"),
time to remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
docs/about/deprecate
On Mon, 4 Mar 2024 11:34:07 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Before the change, the QMP interface used for add/release DC extents
> only allows to release extents that exist in either pending-to-add list
> or accepted list in the device, which means the DPA range of the exten
On Mon, 4 Mar 2024 11:34:06 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by valid extent(s) in the device, the release
On Mon, 4 Mar 2024 11:34:05 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Not all dpa range in the DC regions is valid to access until an extent
All DPA ranges in the DC regions are invalid to access until an extent
covering the range has been added.
> covering the range has been added.
On Mon, 4 Mar 2024 11:34:04 -0800
nifan@gmail.com wrote:
> From: Fan Ni
>
> Since fabric manager emulation is not supported yet, the change implements
> the functions to add/release dynamic capacity extents as QMP interfaces.
We'll need them anyway, or to implement an fm interface via QMP
On 3/5/24 21:38, maobibo wrote:
Sorry, manual is updated already and we do not notice that still.
https://www.loongson.cn/uploads/images/2023102309132647981.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%84%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C%E5%8D%B7%E4%B8%80_r1p10.pdf
It is Chinese web link, English manua
Hi Jon,
This appears to partially address the same problem myself and Robert are
working on. We
are working to add support for CXL port devices to include root ports, RCECs,
USPs,
and DSPs. This was covered with LPC presentation and discussion.
We did not originally include RCEC error handlin
Hi Yuquan an Jon,
I added responses inline below.
On 3/6/24 07:23, Jonathan Cameron wrote:
> On Wed, 6 Mar 2024 19:27:07 +0800
> Yuquan Wang wrote:
>
>> Hello, Jonathan
>>
>> Recently I met some problems on CXL RAS tests.
>>
>> I tried to use "cxl-inject-uncorrectable-errors" and
>> "cxl-inje
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