Prefer using a well known local first CPU rather than a global one.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/bananapi_m2u.c | 2 +-
hw/arm/exynos4_boards.c | 7 ---
hw/arm/orangepi.c | 2 +-
hw/arm/realview.c | 2 +-
hw/arm/xilinx_zynq.c| 2 +-
5 files changed, 8 in
On 10/24/23 23:29, Glenn Miles wrote:
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
on each engine:
0: 14
1: 14
2
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx6.h | 1 -
hw/arm/sabrelite.c| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index 5b4d48da08..51
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/allwinner-r40.h | 1 -
hw/arm/bananapi_m2u.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx7.h | 1 -
hw/arm/mcimx7d-sabre.c| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 2cbfc6b2b2..41
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/allwinner-h3.h | 1 -
hw/arm/orangepi.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
inde
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/xlnx-zynqmp.h | 1 -
hw/arm/xlnx-zcu102.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 68
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/xlnx-versal.h | 1 -
hw/arm/xlnx-versal-virt.c| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 7b
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/allwinner-a10.h | 1 -
hw/arm/cubieboard.c| 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx31.h | 1 -
hw/arm/kzm.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index c116a73e0b
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx25.h | 1 -
hw/arm/imx25_pdk.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index 1b1086e945
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/fsl-imx6ul.h | 1 -
hw/arm/mcimx6ul-evk.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index 630126
Almost no ARM board header requires "hw/arm/boot.h".
Move this header inclusion to the source.
Philippe Mathieu-Daudé (10):
hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from heade
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.
Create a helper to avoid code repetition.
Signed-off-by: Daniel Henrique Barboza
Revi
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
The profile support is handling multi-letter extensions only. Let's add
support for MISA bits as well.
We'll go through every known MISA bit. If the user set the bit, doesn't
matter if to 'true' or 'false', ignore it. If the profile doesn't
de
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
We already track user choice for multi-letter extensions because we
needed to honor user choice when enabling/disabling extensions during
realize(). We refrained from adding the same mechanism for MISA
extensions since we didn't need it.
Profi
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
The TCG emulation implements all the extensions described in the
RVA22U64 profile, both mandatory and optional. The mandatory extensions
will be enabled via the profile flag. We'll leave the optional
extensions to be enabled by hand.
Given tha
Michael Banack writes:
Hello Michael,
> Yes, that patch should be:
>
> Signed-off-by: Michael Banack
>
Great, thanks for the confirmation.
> --Michael Banack
>
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
On 23/10/2023 13.30, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
For now, pixman is mandatory, but we set config_host.h and Kconfig.
Once compilation is fixed, "pixman" will become actually optional.
Signed-off-by: Marc-André Lureau
---
meson.build | 10
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
KVM does not have the means to support enabling the rva22u64 profile.
The main reasons are:
- we're missing support for some mandatory rva22u64 extensions in the
KVM module;
- we can't make promises about enabling a profile since it all de
Peter Xu writes:
> In multiple places, RDMA errors are handled in a strange way, where it only
> sets qemu_file_set_error() but not stop the migration immediately.
>
> It's not obvious what will happen later if there is already an error. Make
> all such failures stop migration immediately.
>
> C
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Add the direct-io migration parameter that tells the migration code to
>>> use O_DIRECT when opening the migration stream file whenever possible.
>>>
>>> This is currently only used for the secondary channels of
On 2023/10/21 6:39, Daniel Henrique Barboza wrote:
The rva22U64 profile, described in:
https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles
Contains a set of CPU extensions aimed for 64-bit userspace
applications. Enabling this set to be enabled via a single user fla
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Add a new migration capability 'fixed-ram'.
>>>
>>> The core of the feature is to ensure that each ram page has a specific
>>> offset in the resulting migration stream. The reason why we'd want
>>> such behavior
On 24/10/23 18:07, Titus Rwantare wrote:
On Tue, 24 Oct 2023 at 04:50, Philippe Mathieu-Daudé wrote:
On 24/10/23 12:06, Alex Bennée wrote:
A pull request is really just a GPG signed tag that you push to a repo.
You can use the existing git tooling to create the cover letter for it.
I've inc
On 2023/10/25 2:08, Alex Bennée wrote:
Akihiko Odaki writes:
Based-on: <20231019101030.128431-1-akihiko.od...@daynix.com>
("[PATCH v5 0/6] gdbstub and TCG plugin improvements")
I and other people in the University of Tokyo, where I research processor
design, found TCG plugins are very useful
On 2023/10/25 1:48, Alex Bennée wrote:
Akihiko Odaki writes:
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
---
accel/tcg/plugin-helpers.h | 3 ++-
include/exec/plugin-gen.h | 4 ++--
include/hw/core/cpu.h | 4 ++--
include/qemu/plu
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Add a capability that allows the management layer to delegate to QEMU
>>> the decision of whether to pause a VM and perform a non-live
>>> migration. Depending on the type of migration being performed, this
>>>
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
---
target/riscv/cpu.h | 5 +--
target/riscv/cpu.c | 4 +--
target/riscv/gdbstub
The capability to read registers is being added to plugins. Whether the
capability is enabled affects TCG translation.
Introduce "CPU flags" to represent a condition affecting TCG
translation.
The CPU flags replaces the plugin event bitmap held by CPUState; the
plugin event bitmap was needed beca
This function is no longer used.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
include/hw/core/cpu.h | 4
target/arm/cpu.h | 6 --
target/ppc/cpu.h | 1 -
target/arm/cpu.c | 1 -
target/arm/gdbstub.c | 18 --
target/ppc/cpu_init.c | 3 --
GDBFeature has the num_regs member so use it where applicable to
remove magic numbers.
Signed-off-by: Akihiko Odaki
---
include/hw/core/cpu.h | 3 ++-
target/s390x/cpu.h | 2 --
gdbstub/gdbstub.c | 5 -
target/arm/cpu.c| 1 -
target/arm/cpu64.c | 1 -
target/avr/cpu
Based-on: <20231019101030.128431-1-akihiko.od...@daynix.com>
("[PATCH v5 0/6] gdbstub and TCG plugin improvements")
I and other people in the University of Tokyo, where I research processor
design, found TCG plugins are very useful for processor design exploration.
The feature we find missing is
The initialization and exit hooks will not affect the state of vCPU
outside TCG context, but they may depend on the state of vCPU.
Therefore, it's better to call plugin hooks after the vCPU state is
fully initialized and before it gets uninitialized.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex
gdb_find_feature() and gdb_find_feature_register() find registers.
gdb_read_register() actually reads registers.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 29 +
gdbstub/gdbstub.c | 31 ++-
2 files changed, 59 insertions
It is based on GDB protocol to ensure interface stability.
The timing of the vcpu init hook is also changed so that the hook will
get called after GDB features are initialized.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706
Signed-off-by: Akihiko Odaki
---
include/qemu/qemu-plugin
This demonstrates how a register can be read from a plugin.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 10 +++-
contrib/plugins/execlog.c | 120 +++--
2 files changed, 97 insertions(+), 33 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
---
include/exec/gdbstub.h | 3 +++
gdbstub/gdbstub.c | 12 +---
target/riscv
Currently the number of registers exposed to GDB is written as magic
numbers in code. Derive the number of registers GDB actually see from
XML files to replace the magic numbers in code later.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
---
include
This avoids optimizations incompatible when reading registers.
Signed-off-by: Akihiko Odaki
---
accel/tcg/plugin-helpers.h | 3 ++-
include/exec/plugin-gen.h | 4 ++--
include/qemu/plugin.h | 2 ++
plugins/plugin.h | 2 +-
accel/tcg/plugin-gen.c | 39 +
Now we know all instances of GDBFeature that is used in CPU so we can
traverse them to find XML. This removes the need for a CPU-specific
lookup function for dynamic XMLs.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
include/exec/gdbstub.h | 6 +++
gdbstub/gdbstub.c | 118 ++
GDBFeatureBuilder unifies the logic to generate dynamic GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
include/exec/gdbstub.h | 50
gdbstub/gdbstub.c | 65 ++
2 files changed, 115 insertio
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Acked-by: Richard Henderson
---
target/arm/cpu.h | 21 +++---
target/arm/internals
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Richard Henderson
---
target/ppc/cpu-qom.h | 4 ++--
target/ppc/cpu.h
This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.
Signed-off-by: Akihiko Odaki
Acked-by: Alex Bennée
---
inclu
Simplify GDBRegisterState by replacing num_regs and xml members with
one member that points to GDBFeature.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
gdbstub/gdbstub.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/gdbstub/gdbstub.c b/gdbstub/g
Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the
gdb_read_register and gdb_write_register members of CPUClass to allow
to unify the logic to access registers of the core and coprocessors
in the future.
Signed-off-by: Akihiko Odaki
Reviewed-by: Alex Bennée
---
include/exec/gdbs
This function is useful to determine the number of registers exposed to
GDB from the XML name.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Reviewed-by: Richard Henderson
---
include/exec/gdbstub.h | 8
gdbstub/gdbstub.c | 13 +++
Okay good, I could merge it via ppc tree then.
Sorry haven't done a PR yet, I've been struggling to get much time :(
Thanks,
Nick
On Wed Oct 25, 2023 at 9:49 AM AEST, BALATON Zoltan wrote:
> Changes in v6:
> - Dropped patch 1, now it's
> Based-on: <20231024224056.842607-1-mark.cave-ayl...@ilande
Enable SVQ with VIRTIO_NET_F_RSS feature.
Signed-off-by: Hawkins Jiawei
---
v5:
- no changes
v4:
https://lore.kernel.org/all/4ee7f3f339469f41626ca2c3ac7b1c574ebce901.1697904740.git.yin31...@gmail.com/
- no code changes
v3:
https://lore.kernel.org/all/2d2a378291bfac4144a0c0c473cf80415bb580
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must
be loaded for the vhost backend.
Given that vhost-vdpa is one of the vhost backend, we need to
implement the SetSteeringEBPF method to support RSS for vhost-vdpa,
even if vhost-vdpa calculates the rss hash in the hardware device
instead
This series enables shadowed CVQ to intercept RSS command
through shadowed CVQ, update the virtio NIC device model
so qemu send it in a migration, and the restore of that
RSS state in the destination.
Note that this patch should be based on
patch "Vhost-vdpa Shadow Virtqueue Hash calculation Suppo
This patch reuses vhost_vdpa_net_load_rss() with some
refactorings to restore the receive-side scaling state
at device's startup.
Signed-off-by: Hawkins Jiawei
---
v5:
- resolve conflict with the updated patch
"Vhost-vdpa Shadow Virtqueue Hash calculation Support"
v4:
https://lore.kernel.org
This patch introduces vhost_vdpa_net_load_rss() to restore
the hash calculation state at device's startup.
Signed-off-by: Hawkins Jiawei
---
v4:
- fix some typos pointed out by Michael
- zero the `cfg` fields at the definition suggested by Michael
v3:
https://patchwork.kernel.org/project/qe
This series enables shadowed CVQ to intercept
VIRTIO_NET_CTRL_MQ_HASH_CONFIG command through shadowed CVQ,
update the virtio NIC device model so qemu send it in a
migration, and the restore of that Hash calculation state
in the destination.
ChangeLog
=
v4:
- fix some typos pointed out by
Enable SVQ with VIRTIO_NET_F_HASH_REPORT feature.
Signed-off-by: Hawkins Jiawei
---
v4:
- no changes
v3:
https://lore.kernel.org/all/c3b69f0a65600722c1e4d3aa14d53a71e8ffb888.1697902949.git.yin31...@gmail.com/
- no code changes
v2:
https://lore.kernel.org/all/a67d4abc2c8c5c7636addc729daa54
The Articia S is a generic chipset supporting several different CPUs
that were among others used on some PPC boards. This is a minimal
emulation of the parts needed for emulating the AmigaOne board.
Signed-off-by: BALATON Zoltan
Tested-by: Rene Engel
---
hw/pci-host/Kconfig | 5 +
h
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware
with patches to support AmigaOS and is very similar to pegasos2 so can
be easily emulated sharing most code with pegasos2. The reason to
emulate it is that AmigaOS comes in different versions for AmigaOne
and PegasosII which only
Add an avocado test for the amigaone board that tests it with the
firmware.
Signed-off-by: BALATON Zoltan
---
tests/avocado/ppc_amiga.py | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 tests/avocado/ppc_amiga.py
diff --git a/tests/avocado/ppc_am
Changes in v6:
- Dropped patch 1, now it's
Based-on: <20231024224056.842607-1-mark.cave-ayl...@ilande.co.uk>
([PATCH v2 0/3] ide: implement simple legacy/native mode switching for PCI IDE
controllers)
- Added Tested-by from Rene
Changes in v5:
- Fixed avocado test
Changes in v4:
- Found typo in
On Tue, 24 Oct 2023, Mark Cave-Ayland wrote:
The via-ide device currently attempts to set the default BAR addresses to the
values shown in the datasheet, but this doesn't work for 2 reasons: firstly
BARS 1-4 do not set the bottom 2 bits to PCI_BASE_ADDRESS_SPACE_IO, and
secondly the initial PCI b
Allow the VIA IDE controller to switch between both legacy and native modes by
calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_PROG
is updated.
This patch moves the initial setting of PCI_CLASS_PROG from via_ide_realize() to
via_ide_reset(), and removes the direct settin
This function reads the value of the PCI_CLASS_PROG register for PCI IDE
controllers and configures the PCI BARs and/or IDE ioports accordingly.
In the case where we switch to legacy mode, the PCI BARs are set to return zero
(as suggested in the "PCI IDE Controller" specification), the legacy IDE
The via-ide device currently attempts to set the default BAR addresses to the
values shown in the datasheet, but this doesn't work for 2 reasons: firstly
BARS 1-4 do not set the bottom 2 bits to PCI_BASE_ADDRESS_SPACE_IO, and
secondly the initial PCI bus reset clears the values of all PCI device BA
This series adds a simple implementation of legacy/native mode switching for PCI
IDE controllers and updates the via-ide device to use it.
The approach I take here is to add a new pci_ide_update_mode() function which
handles
management of the PCI BARs and legacy IDE ioports for each mode to avoid
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
on each engine:
0: 14
1: 14
2: 2
3: 16
Current code assumes that they a
Power9 is supposed to have 4 PIB-connected I2C engines with the
following number of ports on each engine:
0: 2
1: 13
2: 2
3: 2
Power10 also has 4 engines but has the following number of ports
on each engine:
0: 14
1: 14
2: 2
3: 16
Current code assumes that they a
On 24/10/2023 08:08, Bernhard Beschow wrote:
Am 23. Oktober 2023 21:06:11 UTC schrieb Mark Cave-Ayland
:
On 23/10/2023 18:19, Bernhard Beschow wrote:
Am 22. Oktober 2023 22:06:30 UTC schrieb Bernhard Beschow :
Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland
:
This function rea
Yes, that patch should be:
Signed-off-by: Michael Banack
--Michael Banack
On 10/23/23 14:29, Javier Martinez Canillas wrote:
Albert Esteve writes:
From: Michael Banack
To clarify the intent and reasoning behind the hotspot properties
introduce userspace documentation that goes over curso
On Tue, Oct 24, 2023 at 12:41:56PM +0200, Juan Quintela wrote:
> > @@ -509,6 +538,13 @@ static int vmstate_subsection_load(QEMUFile *f, const
> > VMStateDescription *vmsd,
> > }
> > }
> >
> > +for (i = 0; i < n; i++) {
> > +if (!visited[i] && vmstate_section_needed(vmsd
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Add the direct-io migration parameter that tells the migration code to
>> use O_DIRECT when opening the migration stream file whenever possible.
>>
>> This is currently only used for the secondary channels of fixed-ram
>> migration, which ca
Testing of the LED state showed that when the LED polarity was
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
the input GPIO of the LED, the LED was being turn off when it was
expected to be turned on.
Signed-off-by: Glenn Miles
---
Changes from v1:
- Changed logic for read
Testing of the LED state showed that when the LED polarity was
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
the input GPIO of the LED, the LED was being turn off when it was
expected to be turned on.
Signed-off-by: Glenn Miles
---
Changes from v1:
- Changed logic for read
Daniel P. Berrangé writes:
> On Mon, Oct 23, 2023 at 05:35:49PM -0300, Fabiano Rosas wrote:
>> From: Nikolay Borisov
>>
>> Introduce basic pwritev/preadv support in the generic channel layer.
>> Specific implementation will follow for the file channel as this is
>> required in order to support
Daniel P. Berrangé writes:
> On Mon, Oct 23, 2023 at 05:36:07PM -0300, Fabiano Rosas wrote:
>> Add the direct-io migration parameter that tells the migration code to
>> use O_DIRECT when opening the migration stream file whenever possible.
>>
>> This is currently only used for the secondary chan
Hello Cedric & Andrew,
On 10/24/23 10:21, Cédric Le Goater wrote:
On 10/24/23 17:00, Ninad Palsule wrote:
Hello Cedric,
On 10/24/23 02:46, Cédric Le Goater wrote:
On 10/21/23 23:17, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB
On Tue, 2023-10-24 at 17:22 +0100, Paul Durrant wrote:
> On 24/10/2023 16:48, David Woodhouse wrote:
> > On Tue, 2023-10-24 at 16:44 +0100, Paul Durrant wrote:
> > > On 19/10/2023 16:40, David Woodhouse wrote:
> > > > From: David Woodhouse
> > > >
> > > > On soft reset, the prinary console event
On Tue, 2023-10-24 at 18:46 +0100, Peter Maydell wrote:
> On Tue, 24 Oct 2023 at 18:40, Glenn Miles
> wrote:
> > Testing of the LED state showed that when the LED polarity was
> > set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
> > the input GPIO of the LED, the LED was being turn
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Add a new migration capability 'fixed-ram'.
>>
>> The core of the feature is to ensure that each ram page has a specific
>> offset in the resulting migration stream. The reason why we'd want
>> such behavior are two fold:
>>
>> - When doing
The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins. A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage scenario. Existing
On Tue, Oct 24, 2023 at 05:10:32PM +0200, Juan Quintela wrote:
> This way we can read it from any thread.
> I checked that it gives the same value than the current one. We never
s/than/as/
> use to qemu_files at the same time.
s/to/two/
>
> Signed-off-by: Juan Quintela
> ---
> migration/mig
Markus Armbruster writes:
> Fabiano Rosas writes:
>
>> Add a capability that allows the management layer to delegate to QEMU
>> the decision of whether to pause a VM and perform a non-live
>> migration. Depending on the type of migration being performed, this
>> could bring performance benefits.
Allow external devices to drive pca9552 input pins by adding
input GPIO's to the model. This allows a device to connect
its output GPIO's to the pca9552 input GPIO's.
In order for an external device to set the state of a pca9552
pin, the pin must first be configured for high impedance (LED
is off
This is a series of patches targeted at getting the pca9552
model ready for use by the powernv10 machine.
Changes from v2:
- Squashed changes to only update output GPIO if state changed
- Used Andrew's suggestion to simplify code
Glenn Miles (2):
misc/pca9552: Fix inverted input status
Juan Quintela writes:
> This let us simplify code of this shape.
>
>qemu_fflush(f);
>int ret = qemu_file_get_error(f);
>if (ret) {
> return ret;
>}
>
> into:
>
>int ret = qemu_fflush(f);
>if (ret) {
> return ret;
>}
>
> I updated all callers where there is
Juan Quintela writes:
> After last commit, it is a write only variable.
>
> Signed-off-by: Juan Quintela
> ---
> migration/migration-stats.h | 4
> migration/multifd.c | 3 ---
> migration/ram.c | 1 -
> 3 files changed, 8 deletions(-)
>
> diff --git a/migration/migrati
On Mon, Oct 23, 2023 at 05:07:52PM +0100, Jonathan Cameron wrote:
> Enables having multiple CCIs per devices. Each CCI (mailbox) has it's own
> state and command list, so they can't share a single structure.
>
> Signed-off-by: Jonathan Cameron
>
Reviewed-by: Fan Ni
> ---
> v2:
> - Dropped Fan
The patch below fixes a bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2
macros in target/ppc/fpu_helper.c where a non-NaN value is incorrectly
converted to 0, 0x8000, or 0x8000 if a preceding converted
floating-point value was a NaN value.
Resolves: https://gitlab.com/qemu-p
On Mon, Oct 23, 2023 at 05:07:51PM +0100, Jonathan Cameron wrote:
> New CCI types that will be supported shortly do not have a single buffer
> used in both directions. As such, split it up. To avoid the complexities
> of implementing all commands to handle potential aliasing, take a copy of
> the i
On Tue, 24 Oct 2023 at 18:40, Glenn Miles wrote:
>
> Testing of the LED state showed that when the LED polarity was
> set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
> the input GPIO of the LED, the LED was being turned off when it was
> expected to be turned on.
It looks to me f
Juan Quintela writes:
> There are only two differnces with the old value:
>
> - the amount of QEMUFile that hasn't yet been flushed. It can be
> discussed what is more exact, the new or the old one.
> - the amount of transferred bytes that we forgot to account for (the
> newer is better, i.e
Juan Quintela writes:
> qemu_file_transferred() don't exist anymore, so we can reuse the name.
>
> Signed-off-by: Juan Quintela
>
> ---
>
> v2: Update the documentation (thanks fabiano)
> ---
> migration/qemu-file.h | 9 -
> migration/block.c | 4 ++--
> migration/qemu-file.c | 2 +-
Juan Quintela writes:
> Signed-off-by: Juan Quintela
> ---
> migration/qemu-file.h | 18 --
> migration/qemu-file.c | 7 ---
> 2 files changed, 25 deletions(-)
>
> diff --git a/migration/qemu-file.h b/migration/qemu-file.h
> index a29c37b0d0..8b71152754 100644
> --- a/migra
Juan Quintela writes:
> We only use migration_transferred_bytes() to calculate the rate_limit,
> for that we don't need to flush whatever is on the qemu_file buffer.
> Remember that the buffer is really small (normal case is 32K if we use
> iov's can be 64 * TARGET_PAGE_SIZE), so this is not rele
Testing of the LED state showed that when the LED polarity was
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
the input GPIO of the LED, the LED was being turned off when it was
expected to be turned on.
Signed-off-by: Glenn Miles
---
hw/misc/led.c | 2 +-
1 file changed, 1 ins
Juan Quintela writes:
> Signed-off-by: Juan Quintela
> ---
> migration/qemu-file.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/migration/qemu-file.c b/migration/qemu-file.c
> index 384985f534..641ab703cc 100644
> --- a/migration/qemu-file.c
> +++ b/migration/qemu-file.c
> @@ -41
Juan Quintela writes:
> This way we can read it from any thread.
> I checked that it gives the same value than the current one. We never
> use to qemu_files at the same time.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Fabiano Rosas
In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB
instructions to decodetree, the conversion accidentally lost the
correct setting of the syndrome register when taking a trap because
of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct
full syndrome value with the
Juan Quintela writes:
> Remove the increase in qemu_file_fill_buffer() and add asserts to
> qemu_file_transferred* functions.
Patch looks ok, but I would rewrite the whole commit message like this:
Don't increment qemu_file_transferred at qemu_file_fill_buffer
We only call qemu_file_transferre
On Tue, Oct 24, 2023 at 06:14:36PM +0100, Alex Bennée wrote:
>
> Alex Bennée writes:
>
> > A lot of our vhost-user stubs are large chunks of boilerplate that do
> > (mostly) the same thing. This series continues the cleanups by
> > splitting the vhost-user-base and vhost-user-generic implementat
1 - 100 of 378 matches
Mail list logo
