Re: [PATCH v6 08/10] hw/fsi: Added qtest

On 21/10/2023 23.17, Ninad Palsule wrote: Added basic qtests for FSI model. Signed-off-by: Ninad Palsule --- v3: - Added new qtest as per Cedric's comment. V4: - Remove MAINTAINER and documentation changes from this commit v6: - Incorporated review comments by Thomas Huth. --- tests/qte

Re: [PATCH v3 9/9] hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it

On 20/10/2023 15.03, Philippe Mathieu-Daudé wrote: qbus_new(), called in i2c_init_bus(), should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/pxa2xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) Reviewed-by: Thomas Huth

Re: [PATCH v3 8/9] hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()

On 20/10/2023 15.03, Philippe Mathieu-Daudé wrote: Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/pxa2xx_pic.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) Reviewed-by: Thomas Huth

Re: [PATCH v3 7/9] hw/intc/pxa2xx: Pass CPU reference using QOM link property

On 20/10/2023 15.03, Philippe Mathieu-Daudé wrote: QOM objects shouldn't access each other internals fields except using the QOM API. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/pxa2xx_pic.c | 11 ++- 1 file changed, 10 insertions(+), 1 deletion(-) Reviewed-by: Thomas Huth

Re: [PATCH v2 03/13] migration: Use vmstate_register_any() for isa-ide

On 20/10/2023 21.42, Juan Quintela wrote: Thomas Huth wrote: On 20/10/2023 11.07, Juan Quintela wrote: Otherwise qom-test fails. ok 4 /i386/qom/x-remote qemu-system-i386: savevm_state_handler_insert: Detected duplicate SaveStateEntry: id=isa-ide, instance_id=0x0 Broken pipe ../../../../../mnt

Re: [PATCH 0/8] MAINTAINERS: Collect unmaintained files under PPC entries

On 21/10/2023 13.44, Michael Tokarev wrote: 18.10.2023 09:38, Cédric Le Goater : Adding Cc: qemu-triv...@nongnu.org because these changes don't need to go through the ppc tree. Heh.  You guys puzzled me quite a bit ;) Now this puzzle is complete. Okay, let's pick whole bunch (together with f

Re: [PATCH] MAINTAINERS: Add unvalued folders in tests/tcg/ to the right sections

On 21/10/2023 13.31, Michael Tokarev wrote: [Trim recipient list] 18.10.2023 09:24, Thomas Huth: Some subfolders in tests/tcg/ are already listed in the MAINTAINERS file, some others aren't listed yet. Add the missing ones now to the MAINTAINERS file, too, to make sure that get_maintainers.pl r

Re: [PATCH] target/loongarch: Support 4K page size

在 2023/10/23 上午10:40, Song Gao 写道: The LoongArch kernel supports 4K page size. Change TARGET_PAGE_BITS to 12. Signed-off-by: Song Gao --- target/loongarch/cpu-param.h | 2 +- target/loongarch/tlb_helper.c | 9 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/targ

Re: [PATCH v2 6/6] target/riscv/kvm: add zihpm reg

On Wed, Oct 18, 2023 at 8:14 AM Daniel Henrique Barboza wrote: > > Add zihpm support in the KVM driver now that QEMU supports it. > > This reg was added in Linux 6.6. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c | 1 + >

Re: [PATCH v2 4/6] target/riscv/cpu.c: add zihpm extension flag

On Wed, Oct 18, 2023 at 8:14 AM Daniel Henrique Barboza wrote: > > zihpm is the Hardware Performance Counters extension described in > chapter 12 of the unprivileged spec. It describes support for 29 > unprivileged performance counters, hpmcounter3-hpmcounter31. > > As with zicntr, QEMU already im

Re: [PATCH 2/2] igb: Add Function Level Reset to PF and VF

On Fri, Oct 20, 2023 at 5:41 PM Cédric Le Goater wrote: > > On 10/20/23 09:40, Cédric Le Goater wrote: > > On 10/20/23 06:24, Jason Wang wrote: > >> On Tue, Aug 29, 2023 at 5:06 PM Cédric Le Goater wrote: > >>> > >>> From: Cédric Le Goater > >>> > >>> The Intel 82576EB GbE Controller say that th

Re: [PATCH v3 0/6] riscv: query-cpu-model-expansion API

On Thu, Oct 19, 2023 at 7:05 AM Daniel Henrique Barboza wrote: > > Hi, > > This is a re-send of v2 after fixing a trivial conflict with Alistair's > riscv-to-apply.next. > > No other changes made. All patches acked. > > Changes from v2: > - rebased with Alistair's riscv-to-apply.next > - v2 link:

Re: [PATCH v2 3/6] target/riscv/kvm: add zicntr reg

On Wed, Oct 18, 2023 at 8:13 AM Daniel Henrique Barboza wrote: > > Add zicntr support in the KVM driver now that QEMU supports it. > > This reg was added in Linux 6.6. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c | 1 + >

Re: [PATCH v2 2/6] target/riscv/tcg: add ext_zicntr disable support

On Wed, Oct 18, 2023 at 8:13 AM Daniel Henrique Barboza wrote: > > Support for the zicntr counters are already in place. We need a way to > disable them if the user wants to. This is done by restricting access to > the CYCLE, TIME, and INSTRET counters via the 'ctr()' predicate when > we're about

Re: [PATCH v1 0/6] linux-user/loongarch64: Add LSX/LASX sigcontext

Ping ! 在 2023/10/10 上午11:36, Song Gao 写道: Hi, All. This series adds save/restore sigcontext. We use extctx_flags to choces which sigcontext need save/restore. The extctx_flags default value is EXTCTX_FLAGS_FPU, we need save/restore fpu context. After a LSX/LASX instruction is execed, extctx_

Re: [PATCH v3] target/riscv: pmp: Ignore writes when RW=01

On Thu, Oct 19, 2023 at 4:57 PM Mayuresh Chitale wrote: > > As per the Priv spec: "The R, W, and X fields form a collective WARL > field for which the combinations with R=0 and W=1 are reserved." > However currently such writes are not ignored as ought to be. The > combinations with RW=01 are allo

Re: [PATCH v2] target/riscv: pmp: Clear pmp/smepmp bits on reset

On Thu, Oct 19, 2023 at 4:57 PM Mayuresh Chitale wrote: > > As per the Priv and Smepmp specifications, certain bits such as the 'L' > bit of pmp entries and mseccfg.MML can only be cleared upon reset and it > is necessary to do so to allow 'M' mode firmware to correctly reinitialize > the pmp/smpe

[PATCH] target/loongarch: Support 4K page size

The LoongArch kernel supports 4K page size. Change TARGET_PAGE_BITS to 12. Signed-off-by: Song Gao --- target/loongarch/cpu-param.h | 2 +- target/loongarch/tlb_helper.c | 9 - 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu-param.h b/target/loongarch

Re: [PATCH v2] target/riscv: pmp: Clear pmp/smepmp bits on reset

On Thu, Oct 19, 2023 at 4:57 PM Mayuresh Chitale wrote: > > As per the Priv and Smepmp specifications, certain bits such as the 'L' > bit of pmp entries and mseccfg.MML can only be cleared upon reset and it > is necessary to do so to allow 'M' mode firmware to correctly reinitialize > the pmp/smpe

Re: [PATCH v2 00/16] tests: Add CPU topology related smbios test cases

On Sun, Oct 22, 2023 at 05:19:30AM -0400, Michael S. Tsirkin wrote: > Date: Sun, 22 Oct 2023 05:19:30 -0400 > From: "Michael S. Tsirkin" > Subject: Re: [PATCH v2 00/16] tests: Add CPU topology related smbios test > cases > > On Thu, Sep 28, 2023 at 08:59:27PM +0800, Zhao Liu wrote: > > From: Zha

Re: [PATCH v2] Add epmp to extensions list and rename it to smepmp

On Thu, Oct 19, 2023 at 4:56 PM Mayuresh Chitale wrote: > > From: Himanshu Chauhan > > Smepmp is a ratified extension which qemu refers to as epmp. > Rename epmp to smepmp and add it to extension list so that > it is added to the isa string. > > Signed-off-by: Himanshu Chauhan > Signed-off-by: M

Re: [PATCH v2 15/16] tests: bios-tables-test: Add test for smbios type4 thread count2

Hi Michael, On Sun, Oct 22, 2023 at 05:17:29AM -0400, Michael S. Tsirkin wrote: > Date: Sun, 22 Oct 2023 05:17:29 -0400 > From: "Michael S. Tsirkin" > Subject: Re: [PATCH v2 15/16] tests: bios-tables-test: Add test for smbios > type4 thread count2 > > On Thu, Sep 28, 2023 at 08:59:42PM +0800, Z

Re:[PATCH] virtio-blk: don't start dataplane during the stop of dataplane

>> I won't be able to reply until November 2nd. Maybe Kevin or Hanna can>> >> discuss this with you in the meantime. Thanks @Kevin, @Hanna, Do you have any oponions on this issue and my solution ? Original Mail Sender: StefanHajnoczi To: lv mengzhao10286442; CC: stefa...@redhat.com;m...

Re: [PATCH v2] Add epmp to extensions list and rename it to smepmp

On Thu, Oct 19, 2023 at 4:56 PM Mayuresh Chitale wrote: > > From: Himanshu Chauhan > > Smepmp is a ratified extension which qemu refers to as epmp. > Rename epmp to smepmp and add it to extension list so that > it is added to the isa string. > > Signed-off-by: Himanshu Chauhan > Signed-off-by: M

Re: [v2 4/6] tests/migration: Introduce dirty-ring-size option into guestperf

ping. Regarding the performance of the live migration, Guestperf could provide us with a clear response. IMHO, by just adding a few metrics, it might be developed into a more user-friendly metrics system in the future. We may still enrich it prior to that. On Fri, Oct 20, 2023 at 11:24 PM Hyman

Re: [PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

On Thu, Oct 19, 2023 at 1:47 AM Rob Bradford wrote: > > This has been replaced by a "pmu-mask" property that provides much more > flexibility. > > Signed-off-by: Rob Bradford > Acked-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > docs/about/deprecated.rst | 12 >

Re: [PATCH v4 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Thu, Oct 19, 2023 at 1:45 AM Rob Bradford wrote: > > Using a mask instead of the number of PMU devices supports the accurate > emulation of platforms that have a discontinuous set of PMU counters. > > The "pmu-num" property now generates a warning when used by the user on > the command line. In

Re: [PATCH v13 06/18] target/riscv: Use GDBFeature for dynamic XML

On Wed, Oct 18, 2023 at 6:16 AM Akihiko Odaki wrote: > > In preparation for a change to use GDBFeature as a parameter of > gdb_register_coprocessor(), convert the internal representation of > dynamic feature from plain XML to GDBFeature. > > Signed-off-by: Akihiko Odaki Acked-by: Alistair Franci

Re: [PATCH v2 4/4] hw/char/stm32f2xx_usart: Add more definitions for CR1 register

On Sat, Oct 21, 2023 at 4:20 AM Philippe Mathieu-Daudé wrote: > > From: Hans-Erik Floryd > > Signed-off-by: Hans-Erik Floryd > [PMD: Split from bigger patch] > Signed-off-by: Philippe Mathieu-Daudé > --- > Useful if unused? Still useful I think Acked-by: Alistair Francis Alistair

Re: [PATCH v2 3/4] hw/char/stm32f2xx_usart: Update IRQ when DR is written

On Sat, Oct 21, 2023 at 3:01 AM Philippe Mathieu-Daudé wrote: > > From: Hans-Erik Floryd > > Signed-off-by: Hans-Erik Floryd > [PMD: Split from bigger patch] > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/char/stm32f2xx_usart.c | 1 + > 1 file cha

Re: [PATCH v2 2/4] hw/char/stm32f2xx_usart: Update IRQ when SR is read

On Sat, Oct 21, 2023 at 4:12 AM Philippe Mathieu-Daudé wrote: > > From: Hans-Erik Floryd > > Signed-off-by: Hans-Erik Floryd > [PMD: Split from bigger patch] > Signed-off-by: Philippe Mathieu-Daudé > --- > Is this required? I don't think this is required Alistair > --- > hw/char/stm32f2xx_u

Re: [PATCH v2 1/4] hw/char/stm32f2xx_usart: Extract common IRQ update code to update_irq()

On Sat, Oct 21, 2023 at 4:14 AM Philippe Mathieu-Daudé wrote: > > From: Hans-Erik Floryd > > Signed-off-by: Hans-Erik Floryd > [PMD: Split from bigger patch] > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Alistair > --- > hw/char/stm32f2xx_usart.c | 28 ++

Re: [PATCH v2 0/1] docs/system/riscv: update 'virt' machine core limit

On Sat, Oct 21, 2023 at 6:04 AM Daniel Henrique Barboza wrote: > > Hi, > > Re-sending it with a more adequate commit title. > > Changes from v1: > - change commit title from "remove core limit from virt machine" to > "update 'virt' machine core limit" > - v1 link: > https://lore.kernel.org/qemu

Re: [PATCH v2 1/1] docs/system/riscv: update 'virt' machine core limit

On Sat, Oct 21, 2023 at 6:03 AM Daniel Henrique Barboza wrote: > > The 'virt' RISC-V machine does not have a 8 core limit. The current > limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at > this moment. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 > Signed-of

Re: [PATCH] linux-user/riscv: change default cpu to 'max'

On Fri, Oct 20, 2023 at 5:46 PM Daniel Henrique Barboza wrote: > > Commit f57d5f8004 deprecated the 'any' CPU type but failed to change the > default CPU for linux-user. The result is that all linux-users > invocations that doesn't specify a different CPU started to show a > deprecation warning: >

Re: [PATCH] linux-user/riscv: change default cpu to 'max'

On Fri, Oct 20, 2023 at 5:46 PM Daniel Henrique Barboza wrote: > > Commit f57d5f8004 deprecated the 'any' CPU type but failed to change the > default CPU for linux-user. The result is that all linux-users > invocations that doesn't specify a different CPU started to show a > deprecation warning: >

[PATCH v5 85/94] target/sparc: Move FqTOd, FqTOx to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 49 +-- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 71/94] target/sparc: Move gen_ne_fop_DDD insns to decodetree

Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16, FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d, FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d, FPSUB16d, FPSUB32d, FXNORd, FXORd. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-of

[PATCH v5 62/94] target/sparc: Merge LDFSR, LDXFSR implementations

Combine the helper to a single set_fsr(). Perform the mask and merge inline. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 3 +-- target/sparc/fop_helper.c | 17 ++-- target/sparc/translate.c | 42 +

[PATCH v5 39/94] target/sparc: Move UDIV, SDIV to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/helper.c | 4 --- target/sparc/translate.c | 54 ++- 3 files changed, 27 insertions(+), 33 deletions(-) diff --g

[PATCH v5 82/94] target/sparc: Move gen_fop_FD insns to decodetree

Move FdTOs, FdTOi, FxTOs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 51 +-- 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/tar

[PATCH v5 73/94] target/sparc: Move gen_gsr_fop_DDD insns to decodetree

Move FPACK32, FALIGNDATA, BSHUFFLE. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 101 -- 2 files changed, 55 insertions(+), 49 deletions(-) diff -

[PATCH v5 57/94] target/sparc: Move PREFETCH, PREFETCHA to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 8 ++-- target/sparc/translate.c | 23 --- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/

[PATCH v5 66/94] target/sparc: Move BMASK to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 +- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.de

[PATCH v5 55/94] target/sparc: Move SWAP, SWAPA to decodetree

Remove gen_swap_asi. Rename gen_swap_asi0 to gen_swap_asi. Merge gen_swap into gen_swap_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 58 +-- 2

[PATCH v5 93/94] target/sparc: Convert FZERO, FONE to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 +++ 2 files changed, 45 insertions(+), 29 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 91/94] target/sparc: Move FPCMP* to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 target/sparc/translate.c | 90 +-- 2 files changed, 47 insertions(+), 52 deletions(-) diff --git a/target/sparc/insns.decode b/t

[PATCH v5 60/94] target/sparc: Move asi fp load/store to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 51 +-- target/sparc/translate.c | 173 -- 2 files changed, 81 insertions(+), 143 deletions(-) diff --git a/target/sparc/insns.d

[PATCH v5 88/94] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 142 +- 2 files changed, 51 insertions(+), 94 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 94/94] target/sparc: Remove disas_sparc_legacy

All instructions are now converted. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 145 +-- 1 file changed, 1 insertion(+), 144 deletions(-) diff --git a/target/sparc/translate.c b/targ

[PATCH v5 78/94] target/sparc: Move gen_fop_DDD insns to decodetree

Move FADDd, FSUBd, FMULd, FDIVd. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 55 --- 2 files changed, 32 insertions(+), 27 deletions(-) diff --gi

[PATCH v5 89/94] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 192 -- 2 files changed, 91 insertions(+), 113 deletions(-) diff --git a/target/sparc/insns.decode b/

[PATCH v5 50/94] target/sparc: Split out ldst functions with asi pre-computed

As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 215 ++- 1 file changed, 123 inser

[PATCH v5 13/94] target/sparc: Move BPcc and Bicc to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 117 +++--- 2 files changed, 61 insertions(+), 60 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 10/94] target/sparc: Add decodetree infrastructure

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 ++- target/sparc/meson.build | 3 ++ 3 files changed, 55 insertions(+), 22 deletions(-) create m

[PATCH v5 80/94] target/sparc: Move FSMULD to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 43 +-- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/targ

[PATCH v5 83/94] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree

Note that gen_ne_fop_DF was incorrectly named and does pass env. The two sets of helpers should have been unified. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 67 -

[PATCH v5 90/94] target/sparc: Convert FCMP, FCMPE to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++ target/sparc/translate.c | 145 +++--- 2 files changed, 96 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 87/94] target/sparc: Move FdTOq, FxTOq to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 47 ++- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 92/94] target/sparc: Move FPACK16, FPACKFIX to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 55 --- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 48/94] target/sparc: Split out resolve_asi

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 25 + 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7fc4d8945a..81277fb8ea 10

[PATCH v5 53/94] target/sparc: Move asi integer load/store to decodetree

Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 + target/sparc/translate.c | 128 +-

[PATCH v5 16/94] target/sparc: Merge gen_cond with only caller

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translat

[PATCH v5 86/94] target/sparc: Move FiTOq, FsTOq to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 44 +-- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 52/94] target/sparc: Move simple integer load/store to decodetree

Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 + target/sparc/translate.c | 196 +++--- 2 files changed

[PATCH v5 43/94] target/sparc: Move POPC to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 +++ 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 44/94] target/sparc: Convert remaining v8 coproc insns to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 11 +++ target/sparc/translate.c | 32 ++-- 2 files changed, 17 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/t

[PATCH v5 84/94] target/sparc: Move FqTOs, FqTOi to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 48 +-- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 64/94] target/sparc: Move ARRAY* to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 57 --- 2 files changed, 40 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 67/94] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 ++ target/sparc/translate.c | 92 +-- 2 files changed, 62 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b

[PATCH v5 47/94] target/sparc: Move DONE, RETRY to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 88 --- 2 files changed, 29 insertions(+), 62 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 81/94] target/sparc: Move FDMULQ to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +-- 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/targ

[PATCH v5 32/94] target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver

Use direct loads and stores to env instead. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 32 +--- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 65b71dd931..7b83803b6b 100644

[PATCH v5 45/94] target/sparc: Move JMPL, RETT, RETURN to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 126 -- 2 files changed, 88 insertions(+), 45 deletions(-) diff --git a/target/sparc/insns.decode b/t

[PATCH v5 49/94] target/sparc: Drop ifdef around get_asi and friends

Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 189 +++ 1 file changed, 72 insert

[PATCH v5 56/94] target/sparc: Move CASA, CASXA to decodetree

Remove gen_cas_asi, gen_casx_asi. Rename gen_cas_asi0 to gen_cas_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 target/sparc/translate.c | 72 --- 2 files changed, 36 ins

[PATCH v5 61/94] target/sparc: Move LDFSR, STFSR to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 + target/sparc/translate.c | 152 +++--- 2 files changed, 64 insertions(+), 92 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 75/94] target/sparc: Move gen_fop_DD insns to decodetree

Move FSQRTd, FxTOd, FdTOx. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 50 +-- 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/ta

[PATCH v5 46/94] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 target/sparc/translate.c | 35 +-- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/target/sparc/insns.decode b/targe

[PATCH v5 54/94] target/sparc: Move LDSTUB, LDSTUBA to decodetree

Remove gen_ldstub_asi. Rename gen_ldstub_asi0 to gen_ldstub_asi. Merge gen_ldstub into gen_ldstub_asi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 target/sparc/translate.c | 46 +++

[PATCH v5 42/94] target/sparc: Move MOVcc, MOVR to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 116 -- 2 files changed, 64 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 79/94] target/sparc: Move gen_fop_QQQ insns to decodetree

Move FADDq, FSUBq, FMULq, FDIVq. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 52 +++ 2 files changed, 30 insertions(+), 26 deletions(-) diff --gi

[PATCH v5 33/94] target/sparc: Move basic arithmetic to decodetree

Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 185 +- 2 files changed, 94 insertions(+), 103 deletion

[PATCH v5 14/94] target/sparc: Move BPr to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 63 ++- 2 files changed, 25 insertions(+), 41 deletions(-) diff --git a/target/sparc/insns.decode b/tar

[PATCH v5 58/94] target/sparc: Split out fp ldst functions with asi precomputed

Take the operation size from the MemOp instead of a separate parameter. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 138 +++ 1 file changed, 80 insertions(+), 58 deletions(-) diff --

[PATCH v5 17/94] target/sparc: Merge gen_fcond with only caller

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate

[PATCH v5 59/94] target/sparc: Move simple fp load/store to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 19 target/sparc/translate.c | 194 ++ 2 files changed, 113 insertions(+), 100 deletions(-) diff --git a/target/sparc/insns.decode

[PATCH v5 77/94] target/sparc: Move gen_fop_FFF insns to decodetree

Move FADDs, FSUBs, FMULs, FDIVs. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 +++ 2 files changed, 31 insertions(+), 27 deletions(-) diff --gi

[PATCH v5 68/94] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 91 +-- 2 files changed, 56 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 15/94] target/sparc: Move FBPfcc and FBfcc to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 102 +++--- 2 files changed, 43 insertions(+), 63 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 18/94] target/sparc: Merge gen_branch_[an] with only caller

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 73 +--- 1 file changed, 30 insertions(+), 43 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b8d51d6d6

[PATCH v5 65/94] target/sparc: Move ADDRALIGN* to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 ++- 2 files changed, 34 insertions(+), 25 deletions(-) diff --git a/target/sparc/insns.decode b/ta

[PATCH v5 76/94] target/sparc: Move FSQRTq to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 38 ++ 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/targe

[PATCH v5 72/94] target/sparc: Move PDIST to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +-- 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/targ

[PATCH v5 51/94] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX

Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c | 48 +--- 1 file changed, 40 insertions(+), 8 de

[PATCH v5 63/94] target/sparc: Move EDGE* to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++- target/sparc/translate.c | 271 -- 2 files changed, 133 insertions(+), 160 deletions(-) diff --git a/target/sparc/insns.decode

[PATCH v5 35/94] target/sparc: Move MULX to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 7 ++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1cff18

[PATCH v5 74/94] target/sparc: Move gen_fop_FF insns to decodetree

Move FSQRTs, FiTOs, FsTOi. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 47 --- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/ta

[PATCH v5 69/94] target/sparc: Use tcg_gen_vec_{add,sub}*

Replace the local helpers for the same integer operations. Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/helper.h | 12 target/sparc/translate.c | 15 +- target/sparc/vis_helper.c | 59

[PATCH v5 34/94] target/sparc: Move ADDC to decodetree

Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 154 -- 2 files changed, 97 insertions(+), 58 deletions(-) diff --git a/target/sparc/insns.decode b/tar

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