On Sat, Oct 21, 2023 at 6:03 AM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > The 'virt' RISC-V machine does not have a 8 core limit. The current > limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at > this moment. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > docs/system/riscv/virt.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst > index f9a2eac544..f5fa7b8b29 100644 > --- a/docs/system/riscv/virt.rst > +++ b/docs/system/riscv/virt.rst > @@ -12,7 +12,7 @@ Supported devices > > The ``virt`` machine supports the following devices: > > -* Up to 8 generic RV32GC/RV64GC cores, with optional extensions > +* Up to 512 generic RV32GC/RV64GC cores, with optional extensions > * Core Local Interruptor (CLINT) > * Platform-Level Interrupt Controller (PLIC) > * CFI parallel NOR flash memory > -- > 2.41.0 > >
