Re: [PATCH 11/85] target/sparc: Merge gen_fcond with only caller

On 13/10/23 23:27, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 10/85] target/sparc: Merge gen_cond with only caller

On 13/10/23 23:27, Richard Henderson wrote: Signed-off-by: Richard Henderson --- target/sparc/translate.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO

On 13/10/23 23:27, Richard Henderson wrote: Always use TSO, per the Oracle 2015 manual. This is slightly less restrictive than the TCG_MO_ALL default, and happens to match the i386 model, which will eliminate a few extra barriers on that host. Signed-off-by: Richard Henderson --- target/sparc

Re: [RFC PATCH 04/11] tests/avocado: ppc add hypervisor tests

+ Anushree, Hari - FYI On 10/10/23 13:22, Nicholas Piggin wrote: The powernv and pseries machines both provide hypervisor facilities, which is a large and complicated set of features that don't get much system testing in CI. Add a new test case for these which runs QEMU KVM inside the target. -

Re: [PATCH v3 13/13] migration/rdma: Remove all "ret" variables that are used only once

Fabiano Rosas wrote: > Juan Quintela writes: > >> Change code that is: >> >> int ret; >> ... >> >> ret = foo(); >> if (ret[ < 0]?) { >> >> to: >> >> if (foo()[ < 0]) { >> >> Signed-off-by: Juan Quintela >> --- >> migration/rdma.c | 29 - >> 1 file changed, 8 insertio

[PATCH 07/17] tests/tcg/arm: move non-SVE tests out of conditional

test-aes, sha1-vector and sha512-vector need not be conditional on $(CROSS_CC_HAS_SVE), reorganize the "if"s to move them outside. Signed-off-by: Paolo Bonzini --- tests/tcg/aarch64/Makefile.target | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/tcg/aarch64/M

[PATCH 17/17] meson: add a note on why we use config_host for program paths

Signed-off-by: Paolo Bonzini --- meson.build | 5 + 1 file changed, 5 insertions(+) diff --git a/meson.build b/meson.build index 87bb4e9243a..c80882da6fd 100644 --- a/meson.build +++ b/meson.build @@ -4021,6 +4021,11 @@ summary(summary_info, bool_yn: true, section: 'Directories') summary_i

[PATCH 14/17] configure: unify handling of several Debian cross containers

The Debian and GNU architecture names match very often, even though there are common cases (32-bit Arm or 64-bit x86) where they do not and other cases in which the GNU triplet is actually a quadruplet. But it is still possible to group the common case into a single case inside probe_target_compile

[PATCH 06/17] hw/remote: move stub vfu_object_set_bus_irq out of stubs/

Signed-off-by: Paolo Bonzini --- hw/remote/meson.build | 4 +++- stubs/vfio-user-obj.c => hw/remote/vfio-user-obj-stub.c | 0 stubs/meson.build | 1 - 3 files changed, 3 insertions(+), 2 deletions(-) rename stubs/vfio-user-o

[PATCH 09/17] configure: clean up plugin option handling

Keep together all the conditions that lead to disabling plugins, and remove now-dead code. Since the option was not in SKIP_OPTIONS, it was present twice in the help message, both from configure and from meson-buildoptions.sh. Remove the duplication and take the occasion to document the option as

[PATCH 10/17] configure: clean up PIE option handling

Keep together all the conditions that lead to disabling PIE. Signed-off-by: Paolo Bonzini --- configure | 35 ++- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/configure b/configure index 7dad78f329b..a713493e9e2 100755 --- a/configure +++ b/conf

[PATCH 03/17] meson, cutils: allow non-relocatable installs

Suggested-by: Michael Tokarev Signed-off-by: Paolo Bonzini --- meson.build | 21 + meson_options.txt | 2 ++ scripts/meson-buildoptions.sh | 3 +++ util/cutils.c | 11 --- 4 files changed, 34 insertions(+), 3 deletions(-

[PATCH 15/17] configure, meson: use command line options to configure qemu-ga

Preserve the functionality of the environment variables, but allow using the command line instead. Signed-off-by: Paolo Bonzini --- configure | 16 +--- meson_options.txt | 7 +++ qga/meson.build | 9 ++--- scripts/meson-buildop

[PATCH 11/17] configure: remove some dead cruft

print_error is only invoked in one place, and $git is unused. Signed-off-by: Paolo Bonzini --- configure | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/configure b/configure index a713493e9e2..211591911cc 100755 --- a/configure +++ b/configure @@ -94,7 +94,7 @@ quote_s

[PATCH 16/17] meson-buildoptions: document the data at the top

Signed-off-by: Paolo Bonzini --- scripts/meson-buildoptions.py | 8 1 file changed, 8 insertions(+) diff --git a/scripts/meson-buildoptions.py b/scripts/meson-buildoptions.py index 2e88732a291..4814a8ff61f 100644 --- a/scripts/meson-buildoptions.py +++ b/scripts/meson-buildoptions.py @@

[PATCH 04/17] configure: clean up handling of CFI option

Avoid that --enable-cfi --disable-cfi leaves b_lto set to true. Signed-off-by: Paolo Bonzini --- configure | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/configure b/configure index bce8c57596f..3da46ed202d 100755 --- a/configure +++ b/configure @@ -766,11 +766,9 @@ f

[PATCH 01/17] meson: do not build shaders by default

They are not needed when building user-mode emulators. Signed-off-by: Paolo Bonzini --- ui/shader/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/ui/shader/meson.build b/ui/shader/meson.build index 592bf596b9a..3137e65578e 100644 --- a/ui/shader/meson.build +++ b/ui/shader/meson.

[PATCH 12/17] configure: move target-specific defaults to an external machine file

Enable Windows-specific defaults with a machine file, so that related options can be automatically parsed and included in the help message. Signed-off-by: Paolo Bonzini --- configs/meson/windows.txt | 9 + configure | 38 +++ scrip

[PATCH 00/17] More build system cleanups, optional non-relocatable installs

This mostly removes or simplifies some option parsing code, with some extra items of interest: - support for non-relocatable installs, which Michael Tokarev requested a while ago. - the main change outside configure and meson.build is a simplification of GDB conditionals, by unifying HAVE_GDB

[PATCH 13/17] configure: move environment-specific defaults to config-meson.cross

Store the -Werror and SMBD defaults in the machine file, which still allows them to be overridden on the command line and enables automatic parsing of the related options. Signed-off-by: Paolo Bonzini --- configure | 37 +-- scripts/meson-build

[PATCH 08/17] configure, tests/tcg: simplify GDB conditionals

Unify HAVE_GDB_BIN (currently in config-host.mak) and HOST_GDB_SUPPORTS_ARCH into a single GDB variable in config-target.mak. Signed-off-by: Paolo Bonzini --- configure | 30 +-- meson.build | 4 +-- tests/tcg

[PATCH 02/17] meson: do not use set10

Make all items of config-host.h consistent. To keep the --disable-coroutine-pool code visible to the compiler, mutuate the IS_ENABLED() macro from Linux. Signed-off-by: Paolo Bonzini --- include/qemu/compiler.h | 15 +++ meson.build | 2 +- tests/unit/test-coro

[PATCH 05/17] hw/xen: cleanup sourcesets

xen_ss is added unconditionally to arm_ss and i386_ss (the only targets that can have CONFIG_XEN enabled) and its contents are gated by CONFIG_XEN; xen_specific_ss has no condition for its constituent files but is gated on CONFIG_XEN when its added to specific_ss. So xen_ss is a duplicate of xen_s

[PATCH] tests/docker: avoid invalid escape in Python string

This is an error in Python 3.12; fix it by using a raw string literal. Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini --- tests/docker/docker.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/docker/docker.py b/tests/docker/docker.py index 688ef62989c..3b8a267

Re: [PATCH v5] migration: hold the BQL during setup

Fiona Ebner wrote: queued. > This is intended to be a semantic revert of commit 9b09503752 > ("migration: run setup callbacks out of big lock"). There have been so > many changes since that commit (e.g. a new setup callback > dirty_bitmap_save_setup() that also needs to be adapted now), it's > e

Re: [PATCH] qemu-ui-gtk clipboard: fix for freeze-crashes v2

Hello Edmund, The reproduction in the bug description sounds convoluted so I will focus on the code and patch instead: First of all, the patch title should not include a `v2`. The versioning (reroll count) must go in the `[PATCH]` prefix, e.g. `[PATCH v2]` Secondly, the commit message should

Re: [PATCH 2/2] riscv: zicond: make default

On Fri, Aug 11, 2023 at 5:01 PM Andrew Jones wrote: > > On Thu, Aug 10, 2023 at 02:07:17PM -0400, Alistair Francis wrote: > > On Tue, Aug 8, 2023 at 6:10 PM Vineet Gupta wrote: > > > > > > > > > > > > On 8/8/23 14:06, Daniel Henrique Barboza wrote: > > > > (CCing Alistair and other reviewers) > >

Re: [PATCH v3 01/11] tap: Remove tap_probe_vnet_hdr_len()

On 2023/10/16 14:25, Jason Wang wrote: On Fri, Oct 13, 2023 at 1:26 PM Akihiko Odaki wrote: On 2023/10/13 14:00, Jason Wang wrote: On Fri, Oct 13, 2023 at 12:14 PM Akihiko Odaki wrote: On 2023/10/13 10:38, Jason Wang wrote: On Wed, Oct 11, 2023 at 11:40 PM Akihiko Odaki wrote: It was n

Re: [PATCH v2 6/6] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion

On Wed, Sep 27, 2023 at 4:42 AM Daniel Henrique Barboza wrote: > > Use the recently added riscv_cpu_accelerator_compatible() to filter > unavailable CPUs for a given accelerator. At this moment this is the > case for a QEMU built with KVM and TCG support querying a binary running > with TCG: > > q

Re: [PATCH v2 5/6] target/riscv: add riscv_cpu_accelerator_compatible()

On Wed, Sep 27, 2023 at 4:42 AM Daniel Henrique Barboza wrote: > > Add an API to check if a given CPU is compatible with the current > accelerator. > > This will allow query-cpu-model-expansion to work properly in conditions > where QEMU supports both accelerators (TCG and KVM), QEMU is then > lau

Re: [PATCH v2 4/6] target/riscv: handle custom props in qmp_query_cpu_model_expansion

On Wed, Sep 27, 2023 at 4:42 AM Daniel Henrique Barboza wrote: > > Callers can add 'props' when querying for a cpu model expansion to see > if a given CPU model supports a certain criteria, and what's the > resulting CPU object. > > If we have 'props' to handle, gather it in a QDict and use the ne

Re: [PATCH v3 01/11] tap: Remove tap_probe_vnet_hdr_len()

On Fri, Oct 13, 2023 at 1:26 PM Akihiko Odaki wrote: > > On 2023/10/13 14:00, Jason Wang wrote: > > On Fri, Oct 13, 2023 at 12:14 PM Akihiko Odaki > > wrote: > >> > >> On 2023/10/13 10:38, Jason Wang wrote: > >>> On Wed, Oct 11, 2023 at 11:40 PM Akihiko Odaki > >>> wrote: > > It was

Re: [PATCH v2 3/6] target/riscv/tcg: add tcg_cpu_finalize_features()

On Wed, Sep 27, 2023 at 6:05 AM Daniel Henrique Barboza wrote: > > The query-cpu-model-expansion API is capable of passing extra properties > to a given CPU model and tell callers if this custom configuration is > valid. > > The RISC-V version of the API is not quite there yet. The reason is the >

Re: [PATCH v2 2/6] qapi,risc-v: add query-cpu-model-expansion

On Wed, Sep 27, 2023 at 4:41 AM Daniel Henrique Barboza wrote: > > This API is used to inspect the characteristics of a given CPU model. It > also allows users to validate a CPU model with a certain configuration, > e.g. if "-cpu X,a=true,b=false" is a valid setup for a given QEMU > binary. We'll

Re: [PATCH] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps

Hi Cédric, Liu, Joao, On 13/10/23 16:56, Cédric Le Goater wrote: From: Liu Yi L This patch modifies pci_setup_iommu() to set PCIIOMMUOps instead of setting PCIIOMMUFunc. PCIIOMMUFunc is used to get an address space for a PCI device in vendor specific way. The PCIIOMMUOps still offers this func

Re: [PATCH 0/4] target/riscv: rename ext_i* to ext_zi*

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza wrote: > > Hi, > > This series renames the following internal extensions flags: > > ext_ifencei, ext_icsr, ext_icbom, ext_icboz > > To add a leading 'z': > > ext_zifencei, ext_zicsr, ext_zicbom, ext_zicboz > > This was proposed by Andrew Jone

Re: [PATCH v4 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

On Thu, Oct 12, 2023 at 8:03 PM Rajnesh Kanwal wrote: > > This change adds support for inserting virtual interrupts from M-mode > into S-mode using mvien and mvip csrs. IRQ filtering is a use case of > this change, i-e M-mode can stop delegating an interrupt to S-mode and > instead enable it in MI

Re: [PATCH 1/7] hw/ppc/spapr: Restrict PPCTimebase structure declaration to sPAPR

Hi Mark, On 13/10/23 20:32, Mark Cave-Ayland wrote: On 13/10/2023 13:56, Philippe Mathieu-Daudé wrote: The PPCTimebase structure is only used by the sPAPR machine. Move its declaration to "hw/ppc/spapr.h". Move vmstate_ppc_timebase and the VMSTATE_PPC_TIMEBASE_V() macro to hw/ppc/spapr.c, alon

Re: [PATCH 2/3] target/riscv: Support discontinuous PMU counters

On Wed, Oct 11, 2023 at 7:51 PM Rob Bradford wrote: > > On Mon, 2023-10-09 at 11:00 -0700, Atish Kumar Patra wrote: > > On Sun, Oct 8, 2023 at 5:58 PM Alistair Francis > > wrote: > > > > > > On Wed, Oct 4, 2023 at 7:36 PM Rob Bradford > > > wrote: > > > > > > > > Hi Atish, > > > > > > > > On Tue

Re: [PATCH] tests/vm: netbsd: install dtc

On 13/10/23 17:30, Paolo Bonzini wrote: Install dtc as it is now a mandatory external dependency in order to build QEMU. Signed-off-by: Paolo Bonzini --- tests/vm/netbsd | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH 8/8] mailmap: fixup some more corrupted author fields

On 13/10/23 17:44, Alex Bennée wrote: Signed-off-by: Alex Bennée Cc: Timothée Cocault Cc: fanwenjie --- .mailmap | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.mailmap b/.mailmap index d214959288..477c1fae2a 100644 --- a/.mailmap +++ b/.mailmap @@ -30,10 +30,12 @@ malc malc # C

Re: [PATCH 3/4] target/riscv: rename ext_icbom to ext_zicbom

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza wrote: > > Add a leading 'z' to improve grepping. When one wants to search for uses > of zicbom they're more likely to do 'grep -i zicbom' than 'grep -i > icbom'. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza Revi

Re: [PATCH 4/4] target/riscv: rename ext_icboz to ext_zicboz

On Fri, Oct 13, 2023 at 4:07 AM Daniel Henrique Barboza wrote: > > Add a leading 'z' to improve grepping. When one wants to search for uses > of zicboz they're more likely to do 'grep -i zicboz' than 'grep -i > icboz'. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza Revi

Re: [PATCH 2/4] target/riscv: rename ext_icsr to ext_zicsr

On Fri, Oct 13, 2023 at 4:27 AM Daniel Henrique Barboza wrote: > > Add a leading 'z' to improve grepping. When one wants to search for uses > of zicsr they're more likely to do 'grep -i zicsr' than 'grep -i icsr'. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza Reviewed-

Re: [PATCH 1/4] target/riscv: rename ext_ifencei to ext_zifencei

On Fri, Oct 13, 2023 at 2:47 AM Daniel Henrique Barboza wrote: > > Add a leading 'z' to improve grepping. When one wants to search for uses > of zifencei they're more likely to do 'grep -i zifencei' than 'grep -i > ifencei'. > > Suggested-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza

Re: [PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

On Fri, Oct 13, 2023 at 9:04 PM Rob Bradford wrote: > > A 32-bit mask can be trivially created using the 64-bit macro so make > use of that instead. > > Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmu.c | 4 +--- > 1 file changed, 1 insertion(+), 3

Re: [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Fri, Oct 13, 2023 at 11:32 PM Rob Bradford wrote: > > Using a mask instead of the number of PMU devices supports the accurate > emulation of platforms that have a discontinuous set of PMU counters. > > Generate a warning if the old property changed from the default but > still go ahead and use

Re: [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous

On Fri, Oct 13, 2023 at 9:03 PM Rob Bradford wrote: > > Check the PMU available bitmask when checking if a counter is valid > rather than comparing the index against the number of PMUs. > > Signed-off-by: Rob Bradford > Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- >

Re: [PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation

On Fri, Oct 13, 2023 at 9:02 PM Rob Bradford wrote: > > During the FDT generation use the existing mask containing the enabled > counters rather then generating a new one. Using the existing mask will > support the use of discontinuous counters. > > Signed-off-by: Rob Bradford > Reviewed-by: LIU

Re: [PATCH v2 1/3] target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64

On 2023/10/16 13:07, Alistair Francis wrote: On Mon, Oct 16, 2023 at 1:22 PM Akihiko Odaki wrote: On 2023/10/16 10:51, Alistair Francis wrote: On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza wrote: On 10/14/23 00:35, Akihiko Odaki wrote: TARGET_RISCV64 does not have riscv-32bi

Re: [PATCH v2 1/3] target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64

On Mon, Oct 16, 2023 at 1:22 PM Akihiko Odaki wrote: > > > > On 2023/10/16 10:51, Alistair Francis wrote: > > On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 10/14/23 00:35, Akihiko Odaki wrote: > >>> TARGET_RISCV64 does not have riscv-32bit-cpu.xml so it

Re: [PATCH v2 6/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

On Thu, Oct 12, 2023 at 12:52 AM Rob Bradford wrote: > > This has been replaced by a "pmu-mask" property that provides much more > flexibility. > > Signed-off-by: Rob Bradford > --- > docs/about/deprecated.rst | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/docs/about/deprec

Re: [PATCH v2 4/6] qemu/bitops.h: Add MAKE_32BIT_MASK macro

On Thu, Oct 12, 2023 at 6:53 PM LIU Zhiwei wrote: > > > On 2023/10/11 22:45, Rob Bradford wrote: > > Add 32-bit version of mask generating macro and use it in the RISC-V PMU > > code. > CC Richard > > Signed-off-by: Rob Bradford > > --- > > include/qemu/bitops.h | 3 +++ > > target/riscv/pmu.c

Re: [PATCH v2 3/6] target/riscv: Use existing PMU counter mask in FDT generation

On Thu, Oct 12, 2023 at 2:37 AM Rob Bradford wrote: > > During the FDT generation use the existing mask containing the enabled > counters rather then generating a new one. Using the existing mask will > support the use of discontinuous counters. > > Signed-off-by: Rob Bradford Reviewed-by: Alist

Re: [PATCH v2 2/6] target/riscv: Don't assume PMU counters are continuous

On Thu, Oct 12, 2023 at 12:52 AM Rob Bradford wrote: > > Check the PMU available bitmask when checking if a counter is valid > rather than comparing the index against the number of PMUs. > > Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 5 +++

Re: [PATCH v2 1/3] target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64

On 2023/10/16 10:51, Alistair Francis wrote: On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza wrote: On 10/14/23 00:35, Akihiko Odaki wrote: TARGET_RISCV64 does not have riscv-32bit-cpu.xml so it shouldn't accept MXL_RV32. Signed-off-by: Akihiko Odaki --- Reviewed-by: Daniel H

Re: [PATCH 0/4] tcg: Optimize loads and stores to env

在 2023/8/31 上午10:57, Richard Henderson 写道: This is aimed at improving gvec generated code, which involves large numbers of loads and stores to the env slots of the guest cpu vector registers. The final patch helps eliminate redundant zero-extensions that can appear with e.g. avx2 and sve. From

Re: [PATCH V5 4/9] hw/acpi: Init GED framework with CPU hotplug events

On 10/12/23 03:43, Salil Mehta via wrote: ACPI GED(as described in the ACPI 6.2 spec) can be used to generate ACPI events when OSPM/guest receives an interrupt listed in the _CRS object of GED. OSPM then maps or demultiplexes the event by evaluating _EVT method. This change adds the support o

Re: [PATCH V5 1/9] accel/kvm: Extract common KVM vCPU {creation, parking} code

On 10/12/23 03:43, Salil Mehta via wrote: KVM vCPU creation is done once during the initialization of the VM when Qemu thread is spawned. This is common to all the architectures. Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the corresponding KVM vCPU object in the H

Re: [PATCH V5 1/9] accel/kvm: Extract common KVM vCPU {creation, parking} code

On 10/12/23 03:43, Salil Mehta via wrote: KVM vCPU creation is done once during the initialization of the VM when Qemu thread is spawned. This is common to all the architectures. Hot-unplug of vCPU results in destruction of the vCPU object in QOM but the corresponding KVM vCPU object in the H

Re: [PATCH v2 00/10] riscv: RVA22U64 profile support

On Fri, Oct 13, 2023 at 5:07 AM Daniel Henrique Barboza wrote: > > > > On 10/11/23 00:01, Alistair Francis wrote: > > On Sat, Oct 7, 2023 at 12:23 AM Daniel Henrique Barboza > > wrote: > >> > >> Hi, > >> > >> Several design changes were made in this version after the reviews and > >> feedback in

Re: [PATCH 6/8] contrib/gitdm: map HiSilicon to Huawei

On 2023/10/13 23:44, Alex Bennée wrote: > HiSilicon is a wholly owned subsidiary of Huawei so map the domain to > the same company to avoid splitting the contributions. > > Signed-off-by: Alex Bennée > Cc: Yicong Yang Reviewed-by: Yicong Yang > Cc: Jonathan Cameron > --- > contrib/gitdm/dom

Re: [RFC PATCH 11/11] ppc/pnv: Change powernv default to powernv10

On Wed, 11 Oct 2023 at 07:28, Nicholas Piggin wrote: > > On Tue Oct 10, 2023 at 10:05 PM AEST, Joel Stanley wrote: > > On Tue, 10 Oct 2023 at 18:24, Nicholas Piggin wrote: > > > > > > POWER10 is the latest IBM Power machine. Although it is not offered in > > > "OPAL mode" (i.e., powernv configura

Re: [RFC PATCH v3 27/78] target/riscv: add fallthrough pseudo-keyword

On Fri, Oct 13, 2023 at 6:52 PM Emmanouil Pitsidianakis wrote: > > In preparation of raising -Wimplicit-fallthrough to 5, replace all > fall-through comments with the fallthrough attribute pseudo-keyword. > > Signed-off-by: Emmanouil Pitsidianakis Acked-by: Alistair Francis Alistair > --- >

Re: [PATCH v2 1/3] target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64

On Sun, Oct 15, 2023 at 4:05 AM Daniel Henrique Barboza wrote: > > > > On 10/14/23 00:35, Akihiko Odaki wrote: > > TARGET_RISCV64 does not have riscv-32bit-cpu.xml so it shouldn't accept > > MXL_RV32. > > > > Signed-off-by: Akihiko Odaki > > --- > > Reviewed-by: Daniel Henrique Barboza > > > >

Re: [PATCH 2/6] target/tricore: Add read and write semihosting calls

On 10/15/23 13:59, Bastian Koppelmann wrote: Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 52 +++ 1 file changed, 52 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 27e1bdc59d..ccbeae4bc0

[PATCH] target/sparc: Clear may_lookup for npc == DYNAMIC_PC

With pairs of jmp+rett, pc == DYNAMIC_PC_LOOKUP and npc == DYNAMIC_PC. Make sure that we exit for interrupts. Signed-off-by: Richard Henderson --- Mark, I wonder if this will cure some of your lost interrupt issues. Spotted while looking at issues from the JMPL+RETT+RETURN patch. r~ --- targe

Re: [PATCH 00/85] target/sparc: Convert to decodetree

On 10/15/23 13:12, Mark Cave-Ayland wrote: 1 ./qemu-system-sparc -cdrom debian-40r4a-sparc-netinst.iso -boot d -bios ss5.bin (Boot with real SS-5 PROM instead of OpenBIOS) -> Hangs during PROM memory test -> Bisected to: 91b579b5293c4c5c3cfaf0214a5523b655dea4fe is the first bad commit commit 9

Re: [PATCH 3/4] hw/pci-host/bonito: Access memory regions via pci_address_space[_io]()

Am 11. Oktober 2023 18:59:53 UTC schrieb "Philippe Mathieu-Daudé" : >PCI functions are plugged on a PCI bus. They can only access >external memory regions via the bus. > >Signed-off-by: Philippe Mathieu-Daudé >--- > hw/pci-host/bonito.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions

Re: [PATCH 1/4] hw/isa/i82378: Access memory regions via pci_address_space()

Am 11. Oktober 2023 18:59:51 UTC schrieb "Philippe Mathieu-Daudé" : >PCI functions are plugged on a PCI bus. They can only access >external memory regions via the bus. > >Signed-off-by: Philippe Mathieu-Daudé With `info mtree` and `info mtree -f` in the QEMU console before and after this pat

[PATCH 5/6] target/tricore: Add open and creat semihosting calls

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 101 ++ 1 file changed, 101 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 2188ceeed0..34e546c3bf 100644 --- a/target/tricore/tricore-semi.c +++ b

[PATCH 2/6] target/tricore: Add read and write semihosting calls

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 52 +++ 1 file changed, 52 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 27e1bdc59d..ccbeae4bc0 100644 --- a/target/tricore/tricore-semi.c +++ b/

[PATCH 3/6] target/tricore: Add lseek semihosting call

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index ccbeae4bc0..6f321391ef 100644 --- a/target/tricore/tricore-semi.c +++ b/target/tricore/tricor

[PATCH 0/6] TriCore Semihosting

Hi, this patch series implements semihosting as done in the golden Infineon simulator 'TSIM'. 'TSIM' supports different semihosting variants, specific to various toolchain vendors. Only the GNU toolchain with Newlib [1] is freely available, thus I only implemented semihosting for GNU. This port of

[PATCH 4/6] target/tricore: Add close semihosting call

Signed-off-by: Bastian Koppelmann --- target/tricore/tricore-semi.c | 16 1 file changed, 16 insertions(+) diff --git a/target/tricore/tricore-semi.c b/target/tricore/tricore-semi.c index 6f321391ef..2188ceeed0 100644 --- a/target/tricore/tricore-semi.c +++ b/target/tricore/tric

[PATCH 6/6] target/tricore: Enable semihosting

Signed-off-by: Bastian Koppelmann --- configs/devices/tricore-softmmu/default.mak | 1 + docs/about/emulation.rst| 3 +++ qemu-options.hx | 3 ++- target/tricore/translate.c | 13 +++-- 4 files changed, 17 insertions(+),

[PATCH 1/6] target/tricore: Add semihosting stub

Signed-off-by: Bastian Koppelmann --- target/tricore/helper.h | 1 + target/tricore/meson.build| 1 + target/tricore/tricore-semi.c | 197 ++ 3 files changed, 199 insertions(+) create mode 100644 target/tricore/tricore-semi.c diff --git a/target/tri

Re: [PATCH 00/85] target/sparc: Convert to decodetree

On 13/10/2023 22:27, Richard Henderson wrote: While doing some other testing the other day, I noticed my sparc64 chroot running particularly slowly. I think I know what the problem is there, but fixing that was going to be particularly ugly with the existing sparc translator. So I've converted

Re: [PATCH v17 10/16] util/log: Add -d tb_stats

On 10/10/23 05:34, Philippe Mathieu-Daudé wrote: On 3/10/23 20:30, Richard Henderson wrote: From: Fei Wu Enable TBStatistics collection from startup. Signed-off-by: Vanderson M. do Rosario Signed-off-by: Alex Bennée Signed-off-by: Fei Wu [rth: Change "tb_stats_foo" to "tb_stats:foo"] Signe

Re: [PATCH v17 13/16] disas: Allow monitor_disas to read from ram_addr_t

Philippe Mathieu-Daudé writes: > On 3/10/23 20:30, Richard Henderson wrote: >> From: "Vanderson M. do Rosario" >> Introduce a MonitorDisasSpace to replace the current is_physical >> boolean argument to monitor_disas. Generate an error if we attempt >> to read past the end of a single RAMBlock

Re: [PATCH v17 09/16] util/log: Add Error argument to qemu_str_to_log_mask

On 10/10/23 05:55, Markus Armbruster wrote: Richard Henderson writes: Do not rely on return value of 0 to indicate error, pass along an Error pointer to be set. Not wrong, but goes against error.h's recommendation * - Whenever practical, also return a value that indicates success / *

Re: [PATCH 2/2] linux-user: Replace use of lfs64 related functions and macros

Did anything happen with this, or did it get stuck? We just had another user hit it in Gentoo at https://bugs.gentoo.org/915809. It looks like openembedded (obviously given the author) and Alpine have been using this for nearly a year. thanks, sam

Re: [PATCH] tcg: drop unused tcg_temp_free define

On 10/14/23 18:00, Mike Frysinger wrote: Use of the API was removed a while back, but the define wasn't. Signed-off-by: Mike Frysinger --- include/tcg/tcg-op.h | 2 -- 1 file changed, 2 deletions(-) Thanks for the catch. Queued. r~ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-o

Re: [PATCH 03/85] target/sparc: Remove always-set cpu features

On 10/13/23 14:27, Richard Henderson wrote: The oldest supported cpu is the microsparc 1; all other cpus use CPU_DEFAULT_FEATURES. Remove all bits that are always set: FLOAT, SWAP, MUL, DIV, FLUSH, FSQRT, FMUL. Signed-off-by: Richard Henderson I've just found the command-line properties that

Re: [PATCH] tcg: drop unused tcg_temp_free define

On 15/10/23 03:00, Mike Frysinger wrote: Use of the API was removed a while back, but the define wasn't. The cleanup started in commit 47f7313d81 ("tcg: Create tcg/tcg-temp-internal.h") and the last use got removed in d5920b7280 ("tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*"). Reviewed-by: Ph

Re: [RFC] virtio: enforce link up

On 10/15/23 10:42, Michael S. Tsirkin wrote: > On Sat, Oct 14, 2023 at 09:06:09PM +, Vincent Jardin wrote: >> On 10/14/23 18:37, Michael S. Tsirkin wrote: >>> On Sat, Oct 14, 2023 at 06:22:34PM +0200, Vincent Jardin wrote: Using interface's settings, let's enforce an always on link up. >>>

[RFC v2] net/vhost-user.c : enforce link up

Do never set the link down when the vhost-user socket is disconnected. XXX: currently, it cannot work. It is a reply commit to the former one that was a RFC on virtio-net. Don't use it. I do not understand how to get NetdevVhostUserOptions yet. Signed-off-by: Vincent Jardin --- net/vhost-user.c

Re: [PATCH v2] MAINTANERS: Split vt82c686 out of fuloong2e

On Sun, 15 Oct 2023, BALATON Zoltan wrote: The VIA south bridgges are now mostly used by other machines not just Noticed typo bridgges -> bridges, hopefully can be fixed when merging and don't need another version for it. Regards, BALATON Zoltan fuloong2e so split off into a separate secti

Re: [PATCH 07/18] target/i386: introduce flags writeback mechanism

On Sat, Oct 14, 2023 at 6:06 PM Richard Henderson < richard.hender...@linaro.org> wrote: > > On 10/14/23 03:01, Paolo Bonzini wrote: > > +static void prepare_update1_cc(X86DecodedInsn *decode, DisasContext *s, CCOp op) > > +{ > > +decode->cc_dst = s->T0; > > +set_cc_op(s, op); > > +} > > Yo

[RFC PATCH v2 2/3] virtio-net: Use vnet_hash BPF program

The vnet_hash BPF program is capable of hash reporting. Signed-off-by: Akihiko Odaki --- hw/net/virtio-net.c | 62 ++--- 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 8865825362..b9d01af39d

[RFC PATCH v2 3/3] docs: Describe eBPF hash reporting

eBPF hash reporting is now available. Signed-off-by: Akihiko Odaki --- docs/devel/ebpf_rss.rst | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/devel/ebpf_rss.rst b/docs/devel/ebpf_rss.rst index 4a68682b31..b015a8a78b 100644 --- a/docs/devel/ebpf_rss.rst +++ b/docs/d

[RFC PATCH v2 0/3] virtio-net: Introduce eBPF hash reporting

Based-on: <20231015140259.259434-1-akihiko.od...@daynix.com> ("[PATCH v4 00/20] virtio-net RSS/hash report fixes and improvements") I'm proposing to introduce a new BPF program type to report virtio-net hashes to Linux. This series contain patches to utilize the proposed Linux feature. The patches

Re: [PATCH v2 1/3] via-ide: Fix legacy mode emulation

On Sun, 15 Oct 2023, Mark Cave-Ayland wrote: On 14/10/2023 17:13, BALATON Zoltan wrote: On Sat, 14 Oct 2023, Mark Cave-Ayland wrote: On 09/10/2023 20:54, BALATON Zoltan wrote: The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because

[PATCH v2] MAINTANERS: Split vt82c686 out of fuloong2e

The VIA south bridgges are now mostly used by other machines not just fuloong2e so split off into a separate section and take maintanership. Signed-off-by: BALATON Zoltan --- v2: - Rebase on master - Take Philippe's offer and accept maintaining it (I hope Philippe can still help with review and

[PATCH v4 08/20] virtio-net: Copy header only when necessary

It is necessary to copy the header only for byte swapping. Worse, when byte swapping is not needed, the header can be larger than the buffer due to VIRTIO_NET_F_HASH_REPORT, which results in buffer overflow. Copy the header only when byte swapping is needed. Fixes: e22f0603fb ("virtio-net: refere

Re: [PATCH v3 1/3] via-ide: Fix legacy mode emulation

On 14/10/2023 20:37, BALATON Zoltan wrote: The initial value for BARs were set in reset method for emulating legacy mode at start but this does not work because PCI code resets BARs after calling device reset method. Remove this ineffective default to avoid confusion. Instead move setting the B

[PATCH v4 14/20] virtio-net: Do not clear VIRTIO_NET_F_HASH_REPORT

virtio-net can report hash values even if the peer does not have a virtio-net header. Signed-off-by: Akihiko Odaki --- hw/net/virtio-net.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 20df40442d..8865825362 100644 --- a/hw/net/virtio-net.c

[PATCH v4 20/20] ebpf: Add a separate target for skeleton

This generalizes the rule to generate the skeleton and allows to add another. Signed-off-by: Akihiko Odaki --- tools/ebpf/Makefile.ebpf | 15 --- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tools/ebpf/Makefile.ebpf b/tools/ebpf/Makefile.ebpf index 3391e7ce08..572ca5

[PATCH v4 18/20] ebpf: Return 0 when configuration fails

The kernel interprets the returned value as an unsigned 32-bit so -1 will mean queue 4294967295, which is awkward. Return 0 instead. Signed-off-by: Akihiko Odaki --- ebpf/rss.bpf.skeleton.h | 1339 +++ tools/ebpf/rss.bpf.c|2 +- 2 files changed, 670 in

[PATCH v4 17/20] ebpf: Simplify error handling

The error handling procedures required when rss_bpf__open() and rss_bpf__load(rss_bpf_ctx) are different so it's better to implement them separately. Signed-off-by: Akihiko Odaki --- ebpf/ebpf_rss.c | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/ebpf/ebpf_rss.c b/

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