On Fri, Oct 13, 2023 at 6:52 PM Emmanouil Pitsidianakis
<manos.pitsidiana...@linaro.org> wrote:
>
> In preparation of raising -Wimplicit-fallthrough to 5, replace all
> fall-through comments with the fallthrough attribute pseudo-keyword.
>
> Signed-off-by: Emmanouil Pitsidianakis <manos.pitsidiana...@linaro.org>
Acked-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
> target/riscv/insn_trans/trans_rvzce.c.inc | 22 +++++++++++-----------
> target/riscv/translate.c | 4 ++--
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 25cb60558a..98dd2e3cf6 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -122,7 +122,7 @@ static TCGCond gen_compare_i128(bool bz, TCGv rl,
>
> case TCG_COND_LTU:
> invert = true;
> - /* fallthrough */
> + fallthrough;
> case TCG_COND_GEU:
> {
> TCGv tmp = tcg_temp_new();
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc
> b/target/riscv/insn_trans/trans_rvzce.c.inc
> index 2d992e14c4..f0bcbb4f72 100644
> --- a/target/riscv/insn_trans/trans_rvzce.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzce.c.inc
> @@ -125,37 +125,37 @@ static uint32_t decode_push_pop_list(DisasContext *ctx,
> target_ulong rlist)
> case 15:
> reg_bitmap |= 1 << (X_Sn + 11) ;
> reg_bitmap |= 1 << (X_Sn + 10) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 14:
> reg_bitmap |= 1 << (X_Sn + 9) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 13:
> reg_bitmap |= 1 << (X_Sn + 8) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 12:
> reg_bitmap |= 1 << (X_Sn + 7) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 11:
> reg_bitmap |= 1 << (X_Sn + 6) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 10:
> reg_bitmap |= 1 << (X_Sn + 5) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 9:
> reg_bitmap |= 1 << (X_Sn + 4) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 8:
> reg_bitmap |= 1 << (X_Sn + 3) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 7:
> reg_bitmap |= 1 << (X_Sn + 2) ;
> - /* FALL THROUGH */
> + fallthrough;
> case 6:
> reg_bitmap |= 1 << X_S1 ;
> - /* FALL THROUGH */
> + fallthrough;
> case 5:
> reg_bitmap |= 1 << X_S0;
> - /* FALL THROUGH */
> + fallthrough;
> case 4:
> reg_bitmap |= 1 << xRA;
> break;
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f0be79bb16..c99e513221 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -446,7 +446,7 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
> return t;
> }
> #else
> - /* fall through */
> + fallthrough;
> case MXL_RV64:
> return cpu_gpr[reg_num];
> #endif
> @@ -516,7 +516,7 @@ static void gen_set_fpr_hs(DisasContext *ctx, int
> reg_num, TCGv_i64 t)
> tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
> break;
> #else
> - /* fall through */
> + fallthrough;
> case MXL_RV64:
> tcg_gen_mov_i64(cpu_gpr[reg_num], t);
> break;
> --
> 2.39.2
>
>
