[PATCH 1/1] accel/tcg: Fix the comment for CPUTLBEntryFull

When memory region is ram, the lower TARGET_PAGE_BITS is not the physical section number. Instead, its value is always 0. Add comment and assert to make it clear. Signed-off-by: LIU Zhiwei --- accel/tcg/cputlb.c | 11 +++ include/exec/cpu-defs.h | 12 ++-- 2 files changed,

[PATCH 4/4] target/i386: add live migration support for FRED

FRED CPU states are managed in 10 FRED MSRs, in addtion to a few existing CPU registers and MSRs, e.g., the CR4.FRED bit. Add the 10 new FRED MSRs to x86 CPUArchState for live migration support. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 24 +++ targ

[PATCH 3/4] target/i386: enumerate VMX nested-exception support

Allow VMX nested-exception support to be exposed in KVM guests, thus nested KVM guests can enumerate it. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3dba6b46d9..ba579e1fb7 100644

[PATCH 0/4] target/i386: add support for FRED

This patch set adds support for the Intel flexible return and event delivery (FRED) architecture to allow Qemu to run KVM guests with FRED enabled. The FRED architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the follo

[PATCH 2/4] target/i386: mark CR4.FRED not reserved

The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED is exposed to guests, otherwise it is still a reserved bit. Tested-by: Shan Kang Signed-off-by: Xin Li --- target/i386/cpu.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h

[PATCH 1/4] target/i386: add support for FRED in CPUID enumeration

FRED, i.e., the Intel flexible return and event delivery architecture, defines simple new transitions that change privilege level (ring transitions). In addition to these transitions, the FRED architecture defines a new instruction (LKGS) for managing the state of the GS segment register. The LKGS

Re: [PATCH v3 10/20] hw/virtio: add config support to vhost-user-device

On Thu Aug 31, 2023 at 5:47 PM CEST, Alex Bennée wrote: > > Albert Esteve writes: > > > Sorry to bring up this post, it's been a while since you posted. > > But I have been testing the patch the last couple of days. > > > > On Mon, Jul 10, 2023 at 9:58 PM Michael S. Tsirkin wrote: > > > > On Mon

Re: [PATCH 07/11] hw/arm/aspeed: Clean up local variable shadowing

On 9/1/23 00:56, Philippe Mathieu-Daudé wrote: Fix: hw/arm/aspeed_ast2600.c:391:18: error: declaration shadows a local variable [-Werror,-Wshadow] qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); ^ hw/arm/aspeed_ast2600.c:283:14: note: previous decla

Re: [PATCH v2 09/12] hw/vmapple/cfg: Introduce vmapple cfg region

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, Instead of device tree or other more standardized means, VMApple passes platform configuration to the first stage boot loader in a binary encoded format that resides at a dedicated RAM region in physical address space. This patch models this

Re: [PATCH v2 08/12] hw/vmapple/bdif: Introduce vmapple backdoor interface

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG emulation) via virtio-pci as well as a special, simple backdoor platform device. This patch implements this backdoor platform device to the best of my understanding. I

Re: [PATCH v2 07/12] hw/vmapple/aes: Introduce aes engine

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf --- hw/vmapple/aes.c

Re: [PATCH v2 02/12] hw/misc/pvpanic: Add MMIO interface

On 30/08/2023 17:14, Alexander Graf wrote: Hi Alex, In addition to the ISA and PCI variants of pvpanic, let's add an MMIO platform device that we can use in embedded arm environments. Signed-off-by: Alexander Graf Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- v

RE: [PATCH 1/3] hw/misc: Introduce AMD/Xilix Versal TRNG device

Hi Richard, Thanks for your input. I have questions regarding using qemu/guest-random.h for QEMU device models. Using qemu/guest-random.h, how can this TRNG model ensure its independence from other uses of the same qemu_guest_getrandom() and qemu_guest_random_seed_*()? By "other uses", I mean c

Re: [PATCH v2] target/riscv: Allocate itrigger timers only once

On Fri, Aug 18, 2023 at 1:42 PM Akihiko Odaki wrote: > > riscv_trigger_init() had been called on reset events that can happen > several times for a CPU and it allocated timers for itrigger. If old > timers were present, they were simply overwritten by the new timers, > resulting in a memory leak.

Re: [PATCH] target/riscv: Allocate itrigger timers only once

On Thu, Aug 17, 2023 at 2:28 AM Akihiko Odaki wrote: > > riscv_trigger_init() had been called on reset events that can happen > several times for a CPU and it allocated timers for itrigger. If old > timers were present, they were simply overwritten by the new timers, > resulting in a memory leak.

Re: [PATCH 00/13] linux-user patch queue

Ping. On 8/23/23 18:02, Richard Henderson wrote: Combine a bunch of smaller linux-user patches: Supercedes: 20230801230842.414421-1-del...@gmx.de ("[PATCH v2 0/3] linux-user: /proc/cpuinfo fix and content emulation for arm") Supercedes: 20230807122206.655701-1-...@linux.ibm.com ("[PATCH v2] lin

Re: [PATCH v2 27/33] cpu: Remove page_size_init

On Thu, Aug 31, 2023 at 8:23 PM Richard Henderson < richard.hender...@linaro.org> wrote: > Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user. > It should be removed from bsd-user as well, but defer that cleanup. > > Cc: Warner Losh > Reviewed-by: Philippe Mathieu-Daudé > Signed-o

Re: [PATCH v2] target/riscv: Use accelerated helper for AES64KS1I

On Fri, Sep 1, 2023 at 3:12 AM Ard Biesheuvel wrote: > > Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to > implement the first half of the key schedule derivation. This does not > actually involve shifting rows, so clone the same value into all four > columns of the AES vector to

Re: [PATCH] linux-user/riscv: Add new extensions to hwprobe

On Tue, Aug 29, 2023 at 12:58 AM Robbin Ehn wrote: > > This patch adds the new extensions in > linux 6.5 to the hwprobe syscall. > > And fixes RVC check to OR with correct value. > The previous variable contains 0 therefore it > did work. > > Signed-off-by: Robbin Ehn Thanks! Applied to riscv-t

[PATCH v2 02/33] linux-user: Adjust SVr4 NULL page mapping

Use TARGET_PAGE_SIZE and MAP_FIXED_NOREPLACE. We really should be attending to this earlier during probe_guest_base, as well as better detection and emulation of various Linux personalities. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 5 +++-- 1 file changed, 3 insertions(+), 2

[PATCH v2 14/33] softmmu/physmem: Remove HOST_PAGE_ALIGN

Align allocation sizes to the maximum of host and target page sizes. Signed-off-by: Richard Henderson --- softmmu/physmem.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 6f963ea127..04d8423b68 100644 --- a/softmmu

[PATCH v2 13/33] softmmu/physmem: Remove qemu_host_page_size

Use qemu_real_host_page_size() instead. Signed-off-by: Richard Henderson --- softmmu/physmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 18277ddd67..6f963ea127 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -3472,7

Re: [PATCH] linux-user/riscv: Add new extensions to hwprobe

On Tue, Aug 29, 2023 at 12:58 AM Robbin Ehn wrote: > > This patch adds the new extensions in > linux 6.5 to the hwprobe syscall. > > And fixes RVC check to OR with correct value. > The previous variable contains 0 therefore it > did work. > > Signed-off-by: Robbin Ehn Acked-by: Alistair Francis

[PATCH] softmmu/dirtylimit: Fix usleep early return on signal

From: alloc Timeout functions like usleep can return early on signal, which reduces more dirty pages than expected. In dirtylimit case, dirtyrate meter thread needs to kick all vcpus out to sync. The callchain: vcpu_calculate_dirtyrate global_dirty_log_sync memory_global_dirty_log_sy

[PATCH v2 26/33] *-user: Deprecate and disable -p pagesize

This option controls the host page size. From the mis-usage in our own testsuite, this is easily confused with guest page size. The only thing that occurs when changing the host page size is that stuff breaks, because one cannot actually change the host page size. Therefore reject all but the no

[PATCH v2 09/33] linux-user: Remove REAL_HOST_PAGE_ALIGN from mmap.c

We already have qemu_real_host_page_size() in a local variable. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index fc23192a32..48a6ef0af9 10064

Re: [PATCH v2 0/2] riscv: fix --enable-debug in riscv-to-apply.next

On Wed, Aug 30, 2023 at 11:36 PM Daniel Henrique Barboza wrote: > > Hi, > > This is the second version of the --enable-debug build fix for the > riscv-to-apply.next branch: > > https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > This implements suggestions from Richard Henderson made i

[PATCH v2 11/33] migration: Remove qemu_host_page_size

Replace with the maximum of the real host page size and the target page size. This is an exact replacement. Signed-off-by: Richard Henderson --- migration/ram.c | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/migration/ram.c b/migration/ram.c index 90

[PATCH v2 31/33] linux-user: Bound mmap_min_addr by host page size

Bizzarely, it is possible to set /proc/sys/vm/mmap_min_addr to a value below the host page size. Fix that. Signed-off-by: Richard Henderson --- linux-user/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/main.c b/linux-user/main.c index 2334d7cc67..1925c275e

[PATCH v2 32/33] target/ppc: Enable TARGET_PAGE_BITS_VARY for user-only

Since ppc binaries are generally built for multiple page sizes, it is trivial to allow the page size to vary. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu-param.h | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/cp

[PATCH v2 07/33] linux-user/arm: Remove qemu_host_page_size from init_guest_commpage

Use qemu_real_host_page_size. If the commpage is not within reserved_va, use MAP_FIXED_NOREPLACE. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 025747a1

Re: [PATCH v2 26/33] *-user: Deprecate and disable -p pagesize

On Thu, Aug 31, 2023 at 8:23 PM Richard Henderson < richard.hender...@linaro.org> wrote: > This option controls the host page size. From the mis-usage in > our own testsuite, this is easily confused with guest page size. > > The only thing that occurs when changing the host page size is > that st

[PATCH v2 29/33] linux-user: Allow TARGET_PAGE_BITS_VARY

If set, match the host and guest page sizes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/main.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 3dd3310331..2334d7cc67 100644

[PATCH v2 15/33] linux-user: Remove qemu_host_page_size from main

Use qemu_real_host_page_size() instead. Signed-off-by: Richard Henderson --- linux-user/main.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 96be354897..c1058abc3c 100644 --- a/linux-user/main.c +++ b/linux-user/main.c

[PATCH v2 27/33] cpu: Remove page_size_init

Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user. It should be removed from bsd-user as well, but defer that cleanup. Cc: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- bsd-user/qemu.h | 7 +++ include/exec/cpu-common.h | 7

[PATCH v2 25/33] tests/tcg: Extend file in linux-madvise.c

When guest page size > host page size, this test can fail due to the SIGBUS protection hack. Avoid this by making sure that the file size is at least one guest page. Visible with alpha guest on x86_64 host. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tests/tcg/mul

[PATCH v2 03/33] linux-user: Remove qemu_host_page_{size, mask} in probe_guest_base

The host SHMLBA is by definition a multiple of the host page size. Thus the remaining component of qemu_host_page_size is the target page size. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/elfload.c b

[PATCH v2 08/33] linux-user: Remove qemu_host_page_{size, mask} from mmap.c

Use qemu_real_host_page_size instead. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 66 +++ 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 9aab48d4a3..fc23192a32 100644 --- a/linux

[PATCH v2 33/33] target/alpha: Enable TARGET_PAGE_BITS_VARY for user-only

Since alpha binaries are generally built for multiple page sizes, it is trivial to allow the page size to vary. Signed-off-by: Richard Henderson --- target/alpha/cpu-param.h | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/alpha/cpu-param.h b/target/al

[PATCH v2 10/33] linux-user: Remove HOST_PAGE_ALIGN from mmap.c

This removes a hidden use of qemu_host_page_size, using instead the existing host_page_size local within each function. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c i

[PATCH v2 19/33] linux-user: Split out mmap_end

Use a subroutine instead of a goto within target_mmap__locked. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mmap.c | 69 +++ 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/linux-user/mmap.c b/lin

[PATCH v2 18/33] linux-user: Fix sub-host-page mmap

We cannot skip over the_end1 to the_end, because we fail to record the validity of the guest page with the interval tree. Remove "the_end" and rename "the_end1" to "the_end". Signed-off-by: Richard Henderson --- linux-user/mmap.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff -

[PATCH v2 23/33] linux-user: Split out mmap_h_gt_g

Signed-off-by: Richard Henderson --- linux-user/mmap.c | 288 ++ 1 file changed, 139 insertions(+), 149 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index ed82b4bb75..6ab2f35e6f 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c

[PATCH v2 20/33] linux-user: Do early mmap placement only for reserved_va

For reserved_va, place all non-fixed maps then proceed as for MAP_FIXED. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap.c index caa76eb11a..7d482df06d 100644 --- a/linux-u

[PATCH v2 04/33] linux-user: Remove qemu_host_page_size from create_elf_tables

AT_PAGESZ is supposed to advertise the guest page size. The random adjustment made here using qemu_host_page_size does not match anything else within linux-user. The idea here is good, but should be done more systemically via adjustment to TARGET_PAGE_SIZE. Signed-off-by: Richard Henderson ---

[PATCH v2 12/33] hw/tpm: Remove HOST_PAGE_ALIGN from tpm_ppi_init

The size of the allocation need not match the alignment. Signed-off-by: Richard Henderson --- hw/tpm/tpm_ppi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/tpm/tpm_ppi.c b/hw/tpm/tpm_ppi.c index 7f74e26ec6..91eeafd53a 100644 --- a/hw/tpm/tpm_ppi.c +++ b/hw/tpm/tpm_ppi

[PATCH v2 06/33] linux-user/nios2: Remove qemu_host_page_size from init_guest_commpage

Use qemu_real_host_page_size. If !reserved_va, use MAP_FIXED_NOREPLACE. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 939c9b4df1..025747a15c 100644 ---

[PATCH v2 30/33] target/arm: Enable TARGET_PAGE_BITS_VARY for AArch64 user-only

Since aarch64 binaries are generally built for multiple page sizes, it is trivial to allow the page size to vary. Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 6 - target/arm/cpu.c | 51 -- 2 files changed, 34 insertions(+), 23

[PATCH v2 17/33] linux-user: Move some mmap checks outside the lock

Basic validation of operands does not require the lock. Hoist them from target_mmap__locked back into target_mmap. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mmap.c | 107 +++--- 1 file changed, 53 insertions(+), 5

[PATCH v2 24/33] tests/tcg: Remove run-test-mmap-*

These tests are confused, because -p does not change the guest page size, but the host page size. Signed-off-by: Richard Henderson --- tests/tcg/alpha/Makefile.target | 3 --- tests/tcg/arm/Makefile.target | 3 --- tests/tcg/hppa/Makefile.target | 3 --- tests/tcg/i386/Makefile

[PATCH v2 28/33] accel/tcg: Disconnect TargetPageDataNode from page size

Dynamically size the node for the runtime target page size. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 4c1697

[PATCH v2 16/33] linux-user: Split out target_mmap__locked

All "goto fail" may be transformed to "return -1". Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/mmap.c | 62 ++- 1 file changed, 35 insertions(+), 27 deletions(-) diff --git a/linux-user/mmap.c b/linux-user/mmap

[PATCH v2 05/33] linux-user/hppa: Simplify init_guest_commpage

If reserved_va, then we have already reserved the entire guest virtual address space; no need to remap page. If !reserved_va, then use MAP_FIXED_NOREPLACE. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) di

[PATCH v2 22/33] linux-user: Split out mmap_h_lt_g

Work much harder to get alignment and mapping beyond the end of the file correct. Both of which are excercised by our test-mmap for alpha (8k pages) on any 4k page host. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 156 +- 1 file changed,

[PATCH v2 00/33] linux-user: Improve host and guest page size handling

Based-on: 20230829220228.928506-1-richard.hender...@linaro.org ("[PATCH v5 00/20] linux-user: Implement VDSOs") Changes for v2: * Minor adjustments to bsd-user. * Update docs for deprecation. * Philippe's r-b. Blurb from v1: While working on mmap issues for 8.1, I noticed a lot of corner c

[PATCH v2 21/33] linux-user: Split out mmap_h_eq_g

Move the MAX_FIXED_NOREPLACE check for reserved_va earlier. Move the computation of host_prot earlier. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 66 +-- 1 file changed, 53 insertions(+), 13 deletions(-) diff --git a/linux-user/mmap.c b/

[PATCH v2 01/33] accel/tcg: Remove qemu_host_page_size from page_protect/page_unprotect

Use qemu_real_host_page_size instead. Except for the final mprotect within page_protect, we already handled host < target page size. Signed-off-by: Richard Henderson --- accel/tcg/user-exec.c | 18 ++ 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/accel/tcg/user-

Re: [PATCH 1/2] riscv: zicond: make non-experimental

On Wed, Aug 9, 2023 at 4:18 AM Vineet Gupta wrote: > > zicond is now codegen supported in both llvm and gcc. > > This change allows seamless enabling/testing of zicond in downstream > projects. e.g. currently riscv-gnu-toolchain parses elf attributes > to create a cmdline for qemu but fails short

[PATCH 4/5] cxl/type3: add an optional mhd validation function for memory accesses

When memory accesses are made, some MHSLD's would validate the address is within the scope of allocated sections. To do this, the base device must call an optional function set by inherited devices. Signed-off-by: Gregory Price --- hw/mem/cxl_type3.c | 15 +++ include/hw/cx

[PATCH 1/5] cxl/mailbox: move mailbox effect definitions to a header

Preparation for allowing devices to define their own CCI commands Signed-off-by: Gregory Price --- hw/cxl/cxl-mailbox-utils.c | 35 +++ include/hw/cxl/cxl_mailbox.h | 18 ++ 2 files changed, 37 insertions(+), 16 deletions(-) create mode 100644 i

[PATCH 0/5 v2] CXL: SK hynix Niagara MHSLD Device

v2: - 5 patch series, first 4 are pull-aheads that can be merged separately - cci: rebased on 8-30 branch from jic23, dropped cci patches - mailbox: dropped MHD commands, integrated into niagara (for now) - mailbox: refactor CCI defines to avoid redefinition in niagara - type3: cleanup duplicate ty

[PATCH 2/5] cxl/type3: Cleanup multiple CXL_TYPE3() calls in read/write functions

Call CXL_TYPE3 once at top of function to avoid multiple invocations. Signed-off-by: Gregory Price --- hw/mem/cxl_type3.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index fd9d134d46..80d596ee10 100644 --- a/hw/mem/cxl_ty

[PATCH 3/5] cxl/type3: Expose ct3 functions so that inheriters can call them

For devices built on top of ct3, we need the init, realize, and exit functions exposed to correctly start up and tear down. Signed-off-by: Gregory Price --- hw/mem/cxl_type3.c | 8 include/hw/cxl/cxl_device.h | 5 + 2 files changed, 9 insertions(+), 4 deletions(-) diff --g

[PATCH 5/5] cxl/vendor: SK hynix Niagara Multi-Headed SLD Device

Create a new device to emulate the SK hynix Niagara MHSLD platform. This device has custom CCI commands that allow for applying isolation to each memory block between hosts. This enables an early form of dynamic capacity, whereby the NUMA node maps the entire region, but the host is responsible fo

Re: [PATCH v9 0/4] hw/ufs: Add Universal Flash Storage (UFS) support

On 23. 8. 30. 20:38, Stefan Hajnoczi wrote: On Thu, 3 Aug 2023 at 07:49, Jeuk Kim wrote: Dear Stefan, I'm really sorry, but could you please put this patch series instead of v8, which was previously merged into block-next? The fixes from v8 are below. Please let me know if you have any commen

Re: [PATCH 01/11] tcg: Clean up local variable shadowing

On 8/31/23 15:55, Philippe Mathieu-Daudé wrote: -MemOp op = get_memop(oi); +MemOp o = get_memop(oi); mop would be a more descriptive replacement. Otherwise, Reviewed-by: Richard Henderson r~

Re: [PATCH] arm64: Restore trapless ptimer access

On 8/31/23 12:00, Colton Lewis wrote: Due to recent KVM changes, QEMU is setting a ptimer offset resulting in unintended trap and emulate access and a consequent performance hit. Filter out the PTIMER_CNT register to restore trapless ptimer access. Quoting Andrew Jones: Simply reading the CNT r

Re: [PATCH v2 7/7] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree

On 8/31/23 13:30, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned i

Re: [PATCH v2 1/7] target/mips: Simplify Loongson MULTU.G opcode

On 8/31/23 13:30, Philippe Mathieu-Daudé wrote: Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DM

Re: [PATCH 1/3] hw/misc: Introduce AMD/Xilix Versal TRNG device

On 8/31/23 10:18, Tong Ho wrote: This adds a non-cryptographic grade implementation of the model for the True Random Number Generator (TRNG) component in AMD/Xilinx Versal device family. This model is only intended for non-real world testing of guest software, where cryptographically strong TRNG

Re: [PATCH] target/mips: Simplify Loongson MULTU.G opcode

On 8/31/23 13:11, Philippe Mathieu-Daudé wrote: Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DM

[PATCH v3 5/5] target/arm: Enable SCTLR_EL1.TIDCP for user-only

The linux kernel detects and enables this bit. Once trapped, EC_SYSTEMREGISTERTRAP is treated like EC_UNCATEGORIZED, so no changes required within linux-user/aarch64/cpu_loop.c. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/

[PATCH v3 3/5] target/arm: Implement HCR_EL2.TIDCP

Perform the check for EL2 enabled in the security space and the TIDCP bit in an out-of-line helper. Signed-off-by: Richard Henderson --- target/arm/helper.h| 1 + target/arm/tcg/op_helper.c | 13 + target/arm/tcg/translate-a64.c | 16 ++-- target/arm/tcg/

[PATCH v3 2/5] target/arm: Implement cortex-a710

The cortex-a710 is a first generation ARMv9.0-A processor. Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c| 1 + target/arm/tcg/cpu64.c | 212 +++ 3 files changed, 214 insertions(+) diff --git a/docs/system

[PATCH v3 1/5] target/arm: Implement RMR_ELx

Provide a stub implementation, as a write is a "request". Signed-off-by: Richard Henderson --- target/arm/helper.c | 64 + 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e3f5a7d2bd..654e7

[PATCH v3 0/5] target/arm: Implement cortex-a710

Changes for v3: * 9 patches upstreamed * Implement RMR_ELx generically, as a stub. * Implement TIDCP and the closely related v8.8 FEAT_TIDCP1. r~ Richard Henderson (5): target/arm: Implement RMR_ELx target/arm: Implement cortex-a710 target/arm: Implement HCR_EL2.TIDCP target/arm:

[PATCH v3 4/5] target/arm: Implement FEAT_TIDCP1

Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 + target/arm/helper.h| 1 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/op_helper.c | 20 target/arm/tcg/translate-a64.c | 5 +

[PATCH 07/11] hw/arm/aspeed: Clean up local variable shadowing

Fix: hw/arm/aspeed_ast2600.c:391:18: error: declaration shadows a local variable [-Werror,-Wshadow] qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); ^ hw/arm/aspeed_ast2600.c:283:14: note: previous declaration is here qemu_irq irq; ^ hw/

[PATCH 10/11] net/eth: Clean up local variable shadowing

Fix: net/eth.c:435:20: error: declaration shadows a local variable [-Werror,-Wshadow] size_t input_size = iov_size(pkt, pkt_frags); ^ net/eth.c:413:16: note: previous declaration is here size_t input_size = iov_size(pkt, pkt_frags); ^ Sig

[PATCH 09/11] hw/ide/ahci: Clean up local variable shadowing

hw/ide/ahci.c:1577:23: error: declaration shadows a local variable [-Werror,-Wshadow] IDEState *s = &ad->port.ifs[j]; ^ hw/ide/ahci.c:1569:29: note: previous declaration is here void ahci_uninit(AHCIState *s) ^ Signed-off-b

[PATCH 01/11] tcg: Clean up local variable shadowing

Fix: tcg/tcg.c:2551:27: error: declaration shadows a local variable [-Werror,-Wshadow] MemOp op = get_memop(oi); ^ tcg/tcg.c:2437:12: note: previous declaration is here TCGOp *op; ^ accel/tcg/tb-maint.c:245:18: error: declaration

[PATCH 02/11] target/arm: Clean up local variable shadowing

Fix: target/arm/tcg/translate-m-nocp.c:509:18: error: declaration shadows a local variable [-Werror,-Wshadow] TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); ^ target/arm/tcg/translate-m-nocp.c:433:14: note: previous declaration is here TCGv_i32 tmp;

[PATCH 03/11] target/mips: Clean up local variable shadowing

Fix: target/mips/tcg/nanomips_translate.c.inc:4410:33: error: declaration shadows a local variable [-Werror,-Wshadow] int32_t imm = extract32(ctx->opcode, 1, 13) | ^ target/mips/tcg/nanomips_translate.c.inc:3577:9: note: previous declara

[PATCH 05/11] hw/arm/virt: Clean up local variable shadowing

Fix: hw/arm/virt.c:821:22: error: declaration shadows a local variable [-Werror,-Wshadow] qemu_irq irq = qdev_get_gpio_in(vms->gic, ^ hw/arm/virt.c:803:13: note: previous declaration is here int irq; ^ Signed-off-by: Philippe Mathieu-Daudé

[PATCH 08/11] hw/m68k: Clean up local variable shadowing

Fix: hw/m68k/virt.c:263:13: error: declaration shadows a local variable [-Werror,-Wshadow] BOOTINFOSTR(param_ptr, BI_COMMAND_LINE, ^ hw/m68k/bootinfo.h:47:13: note: expanded from macro 'BOOTINFOSTR' int i; \ ^ hw/m68k/virt.c:130:9: note: previous

[PATCH 04/11] target/m68k: Clean up local variable shadowing

Fix: target/m68k/translate.c:828:18: error: declaration shadows a local variable [-Werror,-Wshadow] TCGv tmp = tcg_temp_new(); ^ target/m68k/translate.c:801:15: note: previous declaration is here TCGv reg, tmp, result; ^ Signed-off-by: Philippe

[PATCH 11/11] sysemu/device_tree: Clean up local variable shadowing

Fix: hw/mips/boston.c:472:5: error: declaration shadows a local variable [-Werror,-Wshadow] qemu_fdt_setprop_cells(fdt, name, "reg", reg_base, reg_size); ^ include/sysemu/device_tree.h:129:13: note: expanded from macro 'qemu_fdt_setprop_cells' int i; ^ hw/mips/b

[PATCH 00/11] (few more) Steps towards enabling -Wshadow

For rational see Markus cover on https://lore.kernel.org/qemu-devel/20230831132546.3525721-1-arm...@redhat.com/ This series contains few more, my take. Based-on: <20230831132546.3525721-1-arm...@redhat.com> Philippe Mathieu-Daudé (11): tcg: Clean up local variable shadowing target/arm: Clean

[PATCH 06/11] hw/arm/allwinner: Clean up local variable shadowing

Fix: hw/arm/allwinner-r40.c:412:14: error: declaration shadows a local variable [-Werror,-Wshadow] for (int i = 0; i < AW_R40_NUM_MMCS; i++) { ^ hw/arm/allwinner-r40.c:299:14: note: previous declaration is here unsigned i; ^ Signed-off-by: Philippe Mathieu-D

Re: [PATCH v2 2/2] i386: Fix MCE support for AMD hosts

John, I also noticed something important about this specific code: Qemu commit cb48748af7dfd7654323eb839d1f853ffa873652 introduced the use of the MCG_STATUS_RIPV in the case of a BUS_MCEERR_AR error, but it looks like your reference code is not having this flag. According to me, we should ke

Re: [PATCH v2 0/2] Fix MCE handling on AMD hosts

Hello John, I could test your fixes and I can confirm that the BUS_MCEERR_AR is now working on AMD: Before the fix, the VM panics with: qemu-system-x86_64: Guest MCE Memory Error at QEMU addr 0x7f89573ce000 and GUEST addr 0x10b5ce000 of type BUS_MCEERR_AR injected [   83.562579] mce: [Hardwa

[PATCH] arm64: Restore trapless ptimer access

Due to recent KVM changes, QEMU is setting a ptimer offset resulting in unintended trap and emulate access and a consequent performance hit. Filter out the PTIMER_CNT register to restore trapless ptimer access. Quoting Andrew Jones: Simply reading the CNT register and writing back the same value

[PATCH] add option for a multislot usb ccid device

Signed-off-by: Wilhelm Golz hw/usb/dev-smartcard-reader.c: add option for a multislot usb ccid device, similar to audio multi. --- hw/usb/dev-smartcard-reader.c | 106 +- 1 file changed, 103 insertions(+), 3 deletions(-) diff --git a/hw/usb/dev-smartcard-reader.

[PATCH v3.2 5/7] aspeed: Create flash devices only when defaults are enabled

When the -nodefaults option is set, flash devices should be created with : -blockdev node-name=fmc0,driver=file,filename=./flash.img \ -device mx66u51235f,cs=0x0,bus=ssi.0,drive=fmc0 \ To be noted that in this case, the ROM will not be installed and the initial boot sequence (U-Boot load

Re: [PATCH v2 11/12] hw/vmapple/virtio-blk: Add support for apple virtio-blk

On 31/8/23 22:03, Stefan Hajnoczi wrote: On Wed, Aug 30, 2023 at 04:14:24PM +, Alexander Graf wrote: Apple has its own virtio-blk PCI device ID where it deviates from the official virtio-pci spec slightly: It puts a new "apple type" field at a static offset in config space and introduces a n

[PATCH v2 3/7] target/mips: Convert Loongson DDIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 1 +

[PATCH v2 1/7] target/mips: Simplify Loongson MULTU.G opcode

Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DMULTU). Suggested-by: Richard Henderson Signed-of

[PATCH v2 7/7] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned integers Now that all opcodes from the extension h

[PATCH v2 4/7] target/mips: Convert Loongson DIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbo

[PATCH v2 0/7] target/mips: Convert Loongson LEXT opcodes to decodetree

Respin of old series... Since v1 [*]: - Fixed '!is_double' check (rth) - Rebased (removing tcg_temp_free calls) - Simplified MULT[U].G (rth) - Added R-b Cover from v1: Loongson is next step in the "MIPS decodetree conversion" epic. Start with the simplest extension. The diffstat addition

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