Fix:
target/arm/tcg/translate-m-nocp.c:509:18: error: declaration shadows a local
variable [-Werror,-Wshadow]
TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
^
target/arm/tcg/translate-m-nocp.c:433:14: note: previous declaration is here
TCGv_i32 tmp;
^
target/arm/tcg/mve_helper.c:2463:17: error: declaration shadows a local
variable [-Werror,-Wshadow]
int64_t extval = sextract64(src << shift, 0, 48);
^
target/arm/tcg/mve_helper.c:2443:18: note: previous declaration is here
int64_t val, extval;
^
target/arm/hvf/hvf.c:1936:13: error: declaration shadows a local variable
[-Werror,-Wshadow]
int ret = 0;
^
target/arm/hvf/hvf.c:1807:9: note: previous declaration is here
int ret;
^
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
target/arm/hvf/hvf.c | 1 -
target/arm/tcg/mve_helper.c | 8 ++++----
target/arm/tcg/translate-m-nocp.c | 2 +-
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 486f90be1d..20d534faef 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1933,7 +1933,6 @@ int hvf_vcpu_exec(CPUState *cpu)
uint32_t rt = (syndrome >> 5) & 0x1f;
uint32_t reg = syndrome & SYSREG_MASK;
uint64_t val;
- int ret = 0;
if (isread) {
ret = hvf_sysreg_read(cpu, reg, rt);
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
index 403b345ea3..32087b6f0a 100644
--- a/target/arm/tcg/mve_helper.c
+++ b/target/arm/tcg/mve_helper.c
@@ -924,8 +924,8 @@ DO_1OP_IMM(vorri, DO_ORRI)
bool qc = false; \
for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
bool sat = false; \
- TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \
- mergemask(&d[H##ESIZE(e)], r, mask); \
+ TYPE r_ = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \
+ mergemask(&d[H##ESIZE(e)], r_, mask); \
qc |= sat & mask & 1; \
} \
if (qc) { \
@@ -2460,7 +2460,7 @@ static inline int64_t do_sqrshl48_d(int64_t src, int64_t
shift,
return extval;
}
} else if (shift < 48) {
- int64_t extval = sextract64(src << shift, 0, 48);
+ extval = sextract64(src << shift, 0, 48);
if (!sat || src == (extval >> shift)) {
return extval;
}
@@ -2492,7 +2492,7 @@ static inline uint64_t do_uqrshl48_d(uint64_t src,
int64_t shift,
return extval;
}
} else if (shift < 48) {
- uint64_t extval = extract64(src << shift, 0, 48);
+ extval = extract64(src << shift, 0, 48);
if (!sat || src == (extval >> shift)) {
return extval;
}
diff --git a/target/arm/tcg/translate-m-nocp.c
b/target/arm/tcg/translate-m-nocp.c
index 33f6478bb9..42308c4db5 100644
--- a/target/arm/tcg/translate-m-nocp.c
+++ b/target/arm/tcg/translate-m-nocp.c
@@ -506,7 +506,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
/* fpInactive case: reads as FPDSCR_NS */
- TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
+ tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
storefn(s, opaque, tmp, true);
lab_end = gen_new_label();
tcg_gen_br(lab_end);
--
2.41.0
