Updated section name, so libbpf should init/gues proper
program type without specifications during open/load.
Also, added map_flags with explicitly declared BPF_F_MMAPABLE.
Added check for BPF_F_MMAPABLE flag to meson script and
requirements to libbpf version.
Signed-off-by: Andrew Melnychenko
--
It allows using file descriptors of eBPF provided
outside of QEMU.
QEMU may be run without capabilities for eBPF and run
RSS program provided by management tool(g.e. libvirt).
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss-stub.c | 6 ++
ebpf/ebpf_rss.c | 27 ++
eBPF RSS program and maps may now be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions,
and initialized eBPF program through the helper.
Signed-off-by: Andrew Melnychenko
---
hw/net/virtio-net.c| 55 ++--
This series of patches provides the ability to retrieve eBPF program
through qmp, so management application may load bpf blob with proper
capabilities.
Now, virtio-net devices can accept eBPF programs and maps through properties
as external file descriptors. Access to the eBPF map is direct throug
Changed eBPF map updates through mmaped array.
Mmaped arrays provide direct access to map data.
It should omit using bpf_map_update_elem() call,
which may require capabilities that are not present.
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss.c | 117 ++
Now, the binary objects may be retrieved by id.
It would require for future qmp commands that may require specific
eBPF blob.
Added command "request-ebpf". This command returns
eBPF program encoded base64. The program taken from the
skeleton and essentially is an ELF object that can be
loaded in t
On 8/30/2023 3:48 PM, Daniel P. Berrangé wrote:
On Wed, Aug 30, 2023 at 01:57:59PM +0800, Xiaoyao Li wrote:
On 8/30/2023 1:18 PM, Chenyi Qiang wrote:
On 8/29/2023 6:25 PM, Daniel P. Berrangé wrote:
On Tue, Aug 29, 2023 at 01:31:37PM +0800, Chenyi Qiang wrote:
On 8/22/2023 4:24 PM, Daniel
On Thu, Aug 31, 2023 at 08:22:34AM +0200, Philippe Mathieu-Daudé wrote:
> Hi Michael,
>
> On 30/8/23 23:48, Michael S. Tsirkin wrote:
> > current code sets PCI_SEC_LATENCY_TIMER to WO, but for
> > pcie to pcie bridges it must be RO 0 according to
> > pci express spec which says:
> > This regi
Hi Michael,
On 30/8/23 23:48, Michael S. Tsirkin wrote:
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI
Hi,
On 31/8/23 05:15, Liu Jaloo wrote:
Where actually defined the "PC_MACHINE_CLASS", I can't find it in source
code, please help to point out the file.
It is defined in include/hw/i386/pc.h:
OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE)
The macro itself is defined in inclu
Where actually defined the "PC_MACHINE_CLASS", I can't find it in source
code, please help to point out the file.
Thanks.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.c | 56 ++
1 file changed, 9 insertions(+), 47 deletions(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 38ad8dd4bd..89a7392ed3 100644
--- a/target/arm/tcg/translate.c
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-runtime.h | 25 ++
include/tcg/tcg-op-gvec-common.h | 6 ++
accel/tcg/tcg-runtime-gvec.c | 26 ++
tcg/tcg-op-gvec.c| 150 +++
4 files changed, 207 insertions(+)
diff --git a/ac
This should be usable for loongarch64 as well, rather than
rolling a local copy there.
r~
Richard Henderson (2):
tcg: Add gvec compare with immediate and scalar operand
target/arm: Use tcg_gen_gvec_cmpi for compare vs 0
accel/tcg/tcg-runtime.h | 25 ++
include/tcg/tcg-op-gvec-
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 61 -
1 file changed, 27 insertions(+), 34 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 90c7b32f36..bbcb81e908 100644
--- a/target/i386/tcg/translat
We have tcg_gen_qemu_{ld,st}_i128, which can be used to implement
load/store of vectors to guest memory. But at present we have to
split into, or concatenated from, two i64 to reference the guest
vector register backing store within env.
Provide tcg_gen_{ld,st}_i128, which can avoid the trip thro
Do not require the translators to jump through concat and
extract of i64 in order to move values to and from env.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 3 +++
tcg/tcg-op.c| 22 ++
2 files changed, 25 insertions(+)
diff --git a/i
Notice when a constant is stored to the same location twice.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 51c4c61b9f..6efc08f593 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -22
This is aimed at improving gvec generated code, which involves large
numbers of loads and stores to the env slots of the guest cpu vector
registers. The final patch helps eliminate redundant zero-extensions
that can appear with e.g. avx2 and sve.
>From the small amount of timing that I have done,
Avoid reusing vector temporaries so that we may re-use them
when propagating stores to loads.
Signed-off-by: Richard Henderson
---
tcg/tcg-op-gvec.c | 39 ++-
1 file changed, 6 insertions(+), 33 deletions(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
Will be needed in the next patch.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3013eb04e6..f00db3aa38 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -123,7 +123,7
Propagate stores to loads, loads to loads.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 199 +
1 file changed, 199 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index f00db3aa38..51c4c61b9f 100644
--- a/tcg/optimize.c
+++ b/t
On Tue, Aug 29, 2023 at 08:36:20AM +0800, Gurchetan Singh wrote:
> From: Gurchetan Singh
>
> Changes since v12:
> - Added r-b tags from Antonio Caggiano and Akihiko Odaki
> - Removed review version from commit messages
> - I think we're good to merge since we've had multiple people test and revie
Hi Shameer,
On 8/30/23 21:48, Shameer Kolothum wrote:
Now that we have Eager Page Split support added for ARM in the kernel,
enable it in Qemu. This adds,
-eager-split-size to -accel sub-options to set the eager page split chunk
size.
-enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE.
The chunk s
From: Oleksandr Tyshchenko
In order to use virtio backends we need to initialize RAM for the
xen-mapcache (which is responsible for mapping guest memory using foreign
mapping) to work. Calculate and add hi/low memory regions based on
machine->ram_size.
Use the constants defined in public header
From: Oleksandr Tyshchenko
In order to use virtio backends we need to allocate virtio-mmio
parameters (irq and base) and register corresponding buses.
Use the constants defined in public header arch-arm.h to be
aligned with the toolstack. So the number of current supported
virtio-mmio devices is
The following changes since commit 156618d9ea67f2f2e31d9dedd97f2dcccbe6808c:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2023-08-30 09:20:27 -0400)
are available in the Git repository at:
https://gitlab.com/sstabellini/qemu.git xen-virtio-2-tag
for you
On Tue, 29 Aug 2023, Vikram Garhwal wrote:
> From: Oleksandr Tyshchenko
>
> In order to use virtio backends we need to allocate virtio-mmio
> parameters (irq and base) and register corresponding buses.
>
> Use the constants defined in public header arch-arm.h to be
> aligned with the toolstack.
On Tue, 29 Aug 2023, Vikram Garhwal wrote:
> From: Oleksandr Tyshchenko
>
> In order to use virtio backends we need to initialize RAM for the
> xen-mapcache (which is responsible for mapping guest memory using foreign
> mapping) to work. Calculate and add hi/low memory regions based on
> machine-
On Thu, Aug 31, 2023 at 12:55 AM Michael Tokarev wrote:
> 29.08.2023 18:29, Hyman Huang wrote:
> > From: "alloc.young"
> >
> > Fix memory leak in hmp_info_vcpu_dirty_limit,use g_autoptr
> > to handle memory deallocation.
>
> It does not feel like -stable-worthy, or am I wrong and it should be
>
Hi Alex,
Thanks for reaching out. QEMU is an important development tool for the
Xen community and we are using QEMU as part of our upstream gitlab-ci
testing, see automation/scripts/qemu-*.
As Xen is gaining R52 and R82 support, it would be great to be able to
use QEMU for development and testing
On 8/30/23 01:49, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Richard Henderson
r~
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVPACK{EV/OD}.{B/H/W/D};
- XVPICK{EV/OD}.{B/H/W/D};
- XVILV{L/H}.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 27
target/loongarch/disas.c | 27
target/loongarch/
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVBITSEL.V;
- XVBITSELI.B;
- XVSET{EQZ/NEZ}.V;
- XVSETANYEQZ.{B/H/W/D};
- XVSETALLNEZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 16 +++
target/loongarch/insns.decode| 15 ++
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVFCMP.cond.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 8 +-
target/loongarch/insns.decode| 3 +
target/loongarch/disas.c | 94
target/l
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSEQ[I].{B/H/W/D};
- XVSLE[I].{B/H/W/D}[U];
- XVSLT[I].{B/H/W/D/}[U].
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 4 +
target/loongarch/insns.decode| 43 +++
target/loongarch/disas.c
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVFCVT{L/H}.{S.H/D.S};
- XVFCVT.{H.S/S.D};
- XVFRINT[{RNE/RZ/RP/RM}].{S/D};
- XVFTINT[{RNE/RZ/RP/RM}].{W.S/L.D};
- XVFTINT[RZ].{WU.S/LU.D};
- XVFTINT[{RNE/RZ/RP/RM}].W.D;
- XVFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S;
- XVFFINT.{S.W/D.L}[U];
- X[CVFFI
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVFRSTP[I].{B/H}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 5 ++
target/loongarch/disas.c | 5 ++
target/loongarch/vec_helper.c| 48
target/l
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVBITCLR[I].{B/H/W/D};
- XVBITSET[I].{B/H/W/D};
- XVBITREV[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 4 ++
target/loongarch/insns.decode| 27 +++
target/loongarch/
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- VPCNT.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 5 +
target/loongarch/disas.c | 5 +
target/loongarch/vec_helper.c| 4 ++--
target/loongarch/insn_
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVCLO.{B/H/W/D};
- XVCLZ.{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 9 +
target/loongarch/insns.decode| 9 +
target/loongarch/disas.c | 9
On 8/30/23 01:48, Song Gao wrote:
void HELPER(vssrarni_du_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
-Int128 shft_res1, shft_res2, mask1, mask2, r1, r2;
+int i, j;
+Int128 shft_res[4], mask1, mask2, r[4];
Likewise for the arrays.
r~
On 8/30/23 01:48, Song Gao wrote:
void HELPER(vssrlni_d_q)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
-Int128 shft_res1, shft_res2, mask;
+int i, j;
+Int128 shft_res[4], mask;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
+int oprsz = simd_oprsz(desc);
-
Hi all,
FYI, I recently released Subprovisioner [1], a
qemu-storage-daemon-powered Kubernetes storage provider that enables
users to provision block volumes backed by a single underlying shared
file system. It works by storing those volumes as qcow2 images and
exposing them as block devices using
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 16 ++
target/loongarch/disas.c
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSRLN.{B.H/H.W/W.D};
- XVSRAN.{B.H/H.W/W.D};
- XVSRLNI.{B.H/H.W/W.D/D.Q};
- XVSRANI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 2 +
target/loongarch/insns.decode| 16
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSRLR[I].{B/H/W/D};
- XVSRAR[I].{B/H/W/D}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 17 +
target/loongarch/disas.c | 18 ++
target/loongarch/vec_hel
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSLLWIL.{H.B/W.H/D.W};
- XVSLLWIL.{HU.BU/WU.HU/DU.WU};
- XVEXTL.Q.D, VEXTL.QU.DU.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 9
target/loongarch/disas.c | 9
target/loong
The ongoing QEMU multi-queue block layer effort makes it possible for multiple
threads to process I/O in parallel. The nbd block driver is not compatible with
the multi-queue block layer yet because QIOChannel cannot be used easily from
coroutines running in multiple threads. This series changes th
Callers must clean up their coroutines before calling
object_unref(OBJECT(ioc)) to prevent an fd handler leak. Add an
assertion to check this.
This patch is preparation for the fd handler changes that follow.
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Eric Blake
aio_context is always NULL, so drop it.
Suggested-by: Fabiano Rosas
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
---
include/block/nbd.h | 3 +--
nbd/client-connection.c | 3 +--
nbd/client.c| 5 ++---
qemu-nbd.c | 4 +
aio_context is always NULL, so drop it.
Suggested-by: Fabiano Rosas
Signed-off-by: Stefan Hajnoczi
Reviewed-by: Eric Blake
Reviewed-by: Philippe Mathieu-Daudé
---
nbd/client.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/nbd/client.c b/nbd/client.c
index 16e
v3:
- Fix wrong copy-pasted function name in doc comment [Eric]
- Fix "match" -> "matches" in comment [Eric]
v2:
- Add Patch 1 & 2 to remove unused NBD aio_context arguments and dead code
[Fabiano]
- Remove attach/detach prototypes from "io/channel.h" [Daniel]
- Add utility function to set fd hand
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XV{AND/OR/XOR/NOR/ANDN/ORN}.V;
- XV{AND/OR/XOR/NOR}I.B.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 12
target/loongarch/disas.c | 12
target/loongarch/vec_he
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVMSKLTZ.{B/H/W/D};
- XVMSKGEZ.B;
- XVMSKNZ.B.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 7 ++
target/loongarch/disas.c | 7 ++
target/loongarch/vec_helper.c| 80 ++
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.
Signed-off-by: Song Gao
---
target/loongarch/helper.h| 13 +
target/loongarch/insns.decode
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVEXTH.{H.B/W.H/D.W/Q.D};
- XVEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}.
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 9 +
target/loongarch/disas.c | 9 +
target/loongarch/vec_helper.c
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVSAT.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/insns.decode| 9
target/loongarch/disas.c | 9
target/loongarch/vec_helper.c| 48 ++--
ta
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 7 +++
target/loongarch/insns.decode| 17 +
target/loongarch/disas.c
On 8/30/23 13:56, Philippe Mathieu-Daudé wrote:
+ for (unsigned i = 0, n = vdso->reloc_count; i < n; i++) {
Do we really need 'n'?
You should always have an loop invariant condition if possible.
vdso->reloc_count doesn't seem updated, but I get your point.
But the compiler doesn't know
current code sets PCI_SEC_LATENCY_TIMER to WO, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, refer to the
[PCIe-to-PCI-P
On 28/8/23 20:55, Richard Henderson wrote:
Avoid multiple calls to io_prepare for unaligned acceses.
One call to do_ld_mmio_beN will never cross pages.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 84 +-
1 file changed, 30 insertions(+
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVMADD.{B/H/W/D};
- XVMSUB.{B/H/W/D};
- XVMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 3 +
target/loongarch/insns.decode
On 28/8/23 20:55, Richard Henderson wrote:
Since the introduction of CPUTLBEntryFull, we can recover
the full cpu address space physical address without having
to examine the MemoryRegionSection.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 12
1 file changed, 4 ins
On 2023/08/30 18:38, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
The function calls to `kbd_put_keysym` have been updated to now call
`kbd_put_keysym_console` with a NULL console parameter.
Like most console functions, NULL argument is now for the active console.
This will allo
On 30/8/23 18:17, Richard Henderson wrote:
On 8/30/23 07:22, Philippe Mathieu-Daudé wrote:
Hi Richard,
On 30/8/23 00:02, Richard Henderson wrote:
The vdso image will be pre-processed into a C data array, with
a simple list of relocations to perform, and identifying the
location of signal tramp
On 30/8/23 20:21, Daniel Henrique Barboza wrote:
On 8/28/23 13:47, Philippe Mathieu-Daudé wrote:
On 25/8/23 15:08, Daniel Henrique Barboza wrote:
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --d
On 2023/08/31 0:08, Alex Bennée wrote:
Akihiko Odaki writes:
This demonstrates how a register can be read from a plugin.
Signed-off-by: Akihiko Odaki
---
docs/devel/tcg-plugins.rst | 10 ++-
contrib/plugins/execlog.c | 140 -
2 files changed, 117 in
On 30/8/23 22:34, Richard Henderson wrote:
The previous change, 2d385be6152, assumed !PAGE_VALID meant that
the page would be unmapped by the elf image. However, since we
reserved the entire image space via mmap, PAGE_VALID will always
be set. Instead, assume PROT_NONE for the same condition.
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVMAX[I].{B/H/W/D}[U];
- XVMIN[I].{B/H/W/D}[U].
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 3 ++
target/loongarch/insns.decode| 36
target/loongarch/disas.c
On 8/30/23 01:48, Song Gao wrote:
-#define DO_VABS(a) ((a < 0) ? (-a) : (a))
-
-#define DO_VADDA(NAME, BIT, E, DO_OP) \
-void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t v) \
-{ \
-int i;
On 8/30/23 09:08, Philippe Mathieu-Daudé wrote:
Missed while reviewing commit dfd1b81274
("accel/tcg: Introduce translator_io_start").
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/translator.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/translat
The previous change, 2d385be6152, assumed !PAGE_VALID meant that
the page would be unmapped by the elf image. However, since we
reserved the entire image space via mmap, PAGE_VALID will always
be set. Instead, assume PROT_NONE for the same condition.
Furthermore, assume bss is only ever present
On 2023/08/31 0:02, Alex Bennée wrote:
Akihiko Odaki writes:
GDB has XML support since 6.7 which was released in 2007.
It's time to remove support for old GDB versions without XML support.
Signed-off-by: Akihiko Odaki
In principle I'm fine with this but should we not catch GDB's which
don
From: David Woodhouse
The interrupt from timer 0 in legacy mode is supposed to go to IRQ 0 on
the i8259 and IRQ 2 on the I/O APIC. The generic x86 GSI handling can't
cope with IRQ numbers differing between the two chips (despite it also
being the case for PCI INTx routing), so add a special case
From: David Woodhouse
As noted in the comment, the PCI INTx lines are supposed to be routed
to *both* the PIC and the I/O APIC. It's just that we don't cope with
the concept of an IRQ being asserted to two *different* pins on the
two irqchips.
So we have this hack of routing to I/O APIC only if
Thanks Alex
On Wed, Aug 30, 2023, 14:47 Alex Bennée wrote:
>
> Matt Borgerson writes:
>
> > Translation logic may partially decode an instruction, then abort and
> > remove the instruction from the TB. This can happen for example when an
> > instruction spans two pages. In this case, plugins ma
Matt Borgerson writes:
> Translation logic may partially decode an instruction, then abort and
> remove the instruction from the TB. This can happen for example when an
> instruction spans two pages. In this case, plugins may get an incorrect
> result when calling qemu_plugin_tb_n_insns to quer
Richard Henderson writes:
> Alex, perhaps this will DTRT for your plugin test case.
It does thanks, queued to plugins/next.
>
> r~
>
> Richard Henderson (2):
> accel/tcg: Add plugin_enabled to DisasContextBase
> target/sh4: Disable decode_gusa when plugins enabled
>
> include/exec/transl
On 8/30/23 01:48, Song Gao wrote:
This patch includes:
- XVMUL.{B/H/W/D};
- XVMUH.{B/H/W/D}[U];
- XVMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U];
- XVMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}.
Signed-off-by: Song Gao
---
target/loongarch/vec.h | 2 +
target/loongarch/insns.decode
On 8/28/23 13:47, Philippe Mathieu-Daudé wrote:
On 25/8/23 15:08, Daniel Henrique Barboza wrote:
Move the files to a 'kvm' dir to promote more code separation between
accelerators and making our lives easier supporting build options such
as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it
On 8/30/23 01:48, Song Gao wrote:
--- a/target/loongarch/vec.h
+++ b/target/loongarch/vec.h
@@ -50,4 +50,7 @@
#define DO_ADD(a, b) (a + b)
#define DO_SUB(a, b) (a - b)
+#define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1))
+#define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1
On 8/30/23 01:48, Song Gao wrote:
--- a/target/loongarch/vec.h
+++ b/target/loongarch/vec.h
@@ -47,4 +47,7 @@
#define Q(x) Q[x]
#endif /* HOST_BIG_ENDIAN */
+#define DO_ADD(a, b) (a + b)
+#define DO_SUB(a, b) (a - b)
+
Why are these moved?
r~
On 8/30/23 01:48, Song Gao wrote:
Use gen_helper_gvec_* series function.
and rename lsx_helper.c to vec_helper.c.
Signed-off-by: Song Gao
---
target/loongarch/helper.h | 642
.../loongarch/{lsx_helper.c => vec_helper.c} | 1297 -
These changes
Emmanouil Pitsidianakis writes:
> This commit adds basic documentation for using virtio-snd.
>
> Signed-off-by: Emmanouil Pitsidianakis
> ---
> docs/system/device-emulation.rst | 1 +
> docs/system/devices/virtio-snd.rst | 49 ++
> 2 files changed, 50 insertions
Michael Tokarev writes:
> 30.08.2023 14:49, Stefan Hajnoczi wrote:
>> From: Fabiano Rosas
>>
>> We can fail the blk_insert_bs() at init_blk_migration(), leaving the
>> BlkMigDevState without a dirty_bitmap and BlockDriverState. Account
>> for the possibly missing elements when doing cleanup.
>>
On Tue, Aug 29, 2023 at 11:18:03AM -0700, Steve Sistare wrote:
> Add an option to suspend the src in a-b-bootblock.S, which puts the guest
> in S3 state after one round of writing to memory. The option is enabled by
> poking a 1 into the suspend_me word in the boot block prior to starting the
> sr
On Tue, Aug 29, 2023 at 11:18:02AM -0700, Steve Sistare wrote:
> Define a state object to capture events seen by migration tests, to allow
> more events to be captured in a subsequent patch, and simplify event
> checking in wait_for_migration_pass. No functional change.
>
> Signed-off-by: Steve S
Dear Xen community,
Linaro is significantly invested in QEMU development, with a special
focus on Arm-related aspects. We recognize the value of QEMU as a
readily available software reference platform for projects that need to
test their software well before the availability of real hardware.
T
29.08.2023 18:29, Hyman Huang wrote:
From: "alloc.young"
Fix memory leak in hmp_info_vcpu_dirty_limit,use g_autoptr
to handle memory deallocation.
It does not feel like -stable-worthy, or am I wrong and it should be picked up
for -stable?
Thanks,
/mjt
On Wed, Aug 30, 2023 at 09:45:58AM +0800,
Xiaoyao Li wrote:
> On 8/29/2023 10:40 PM, Philippe Mathieu-Daudé wrote:
> > On 18/8/23 11:49, Xiaoyao Li wrote:
> > > Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
> > > work prior to create any vcpu. This is for i386 TDX because it nee
30.08.2023 14:49, Stefan Hajnoczi wrote:
From: Fabiano Rosas
We can fail the blk_insert_bs() at init_blk_migration(), leaving the
BlkMigDevState without a dirty_bitmap and BlockDriverState. Account
for the possibly missing elements when doing cleanup.
Fix the following crashes:
Thread 1 "qemu
On Tue, Aug 29, 2023 at 11:18:01AM -0700, Steve Sistare wrote:
> During RUN_STATE_SUSPENDED, the cpu clock remains enabled, so the
> timers_state saved to the migration stream is stale, causing time errors
> in the guest when it wakes from suspend.
Instead of having this, I'm wondering whether we
29.08.2023 21:54, Richard Henderson wrote:
..
Richard Henderson (5):
softmmu: Assert data in bounds in iotlb_to_section
softmmu: Use async_run_on_cpu in tcg_commit
tcg: Remove vecop_list check from tcg_gen_not_vec
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
On Tue, Aug 29, 2023 at 11:18:00AM -0700, Steve Sistare wrote:
> Do not wake a suspended guest during bg_migration.
>
> Signed-off-by: Steve Sistare
> ---
> migration/migration.c | 12 +---
> softmmu/runstate.c| 1 +
> 2 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git
Thanks for your answer, that'll help.
On 30/08/2023 13:49, Marc-André Lureau wrote:
Hi Antonio
On Wed, Aug 30, 2023 at 3:14 PM Antonio Caggiano
wrote:
Hi Marc-André,
I've been testing this, but I can't find where qemu_egl_display is set
when using sdl.
Whil ui/gtk.c sets that in gl_area_re
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
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