Re: [PATCH] vhost: release memory objects in error path

Hello Peter, all On Thu, 25 May 2023 at 18:33, Peter Xu wrote: > IIRC this bug used to only reproduce on rt kernels, is it still the case? > * Yes, it's a same crash. > Here besides doing correct unregister, does it also mean that even if > event_notifier_init() failed there's totally no erro

Re: [PATCH v3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"

On Tue, May 23, 2023 at 8:29 PM Sunil V L wrote: > > Currently, virt machine supports two pflash instances each with > 32MB size. However, the first pflash is always assumed to > contain M-mode firmware and reset vector is set to this if > enabled. Hence, for S-mode payloads like EDK2, only one pf

Re: [PATCH v4 0/3] hw/riscv/virt: pflash improvements

On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote: > On Thu, May 25, 2023 at 10:18:00PM +0530, Sunil V L wrote: > > This series improves the pflash usage in RISC-V virt machine with solutions > > to > > below issues. > > > > 1) Currently the first pflash is reserved for ROM/M-mode f

Re: [PATCH 1/3] hw/ufs: Initial commit for emulated Universal-Flash-Storage

On 26/05/2023 07.05, Jeuk Kim wrote: Universal Flash Storage (UFS) is a high-performance mass storage device with a serial interface. It is primarily used as a high-performance data storage device for embedded applications. This commit contains code for UFS device to be recognized as a UFS PCI d

Re: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP calls

On Fri, May 26, 2023 at 2:22 PM Duan, Zhenzhong wrote: > > > >-Original Message- > >From: Peter Xu > >Sent: Thursday, May 25, 2023 9:54 PM > >Subject: Re: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP > >calls > > > >On Thu, May 25, 2023 at 11:29:34AM +, Duan, Zhenzhong wro

[PATCH v3 4/6] target/riscv: Create an KVM AIA irqchip

implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 83 target/riscv/kvm_riscv.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c

[PATCH v3 2/6] target/riscv: support the AIA device emulation with KVM enabled

Remove M mode AIA devices when using KVM acceleration Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 199 +--- 1 file changed, 105 insertions(+), 94 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4e3efbee1

[PATCH v3 3/6] target/riscv: check the in-kernel irqchip support

We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..eb469e8ca5 10

[PATCH v3 5/6] target/riscv: update APLIC and IMSIC to support KVM AIA

- Do not set the mmio operations of APLIC and IMSIC when using KVM AIA - Send interrupt signal to KVM AIA via KVM_IRQ_LINE API Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/intc/riscv_aplic.c | 19 +++ hw/intc/riscv_imsic.c | 16 +++- 2 files changed, 26

[PATCH v3 0/6] Add RISC-V KVM AIA Support

This series adds support for KVM AIA in RISC-V architecture. In order to test these patches, we require Linux with KVM AIA support which can be found in the qemu_kvm_aia branch at https://github.com/yong-xuan/linux.git This kernel branch is based on the riscv_aia_v1 branch available at https://git

[PATCH v3 6/6] target/riscv: select KVM AIA in riscv virt machine

Select KVM AIA when the host kernel has in-kernel AIA chip support. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- hw/riscv/virt.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 18b94888ab..57a07fa6c5 100644 --- a/hw/riscv/virt.c

[PATCH v3 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support placeholder

Sync-up Linux header to get latest KVM RISC-V headers having AIA support. Note: This is a placeholder commit and could be replaced when all referenced Linux patchsets are mainlined. The linux-headers changes are from 2 different patchsets. [1] https://lore.kernel.org/lkml/20230404153452.2405681

RE: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP calls

>-Original Message- >From: Peter Xu >Sent: Thursday, May 25, 2023 9:54 PM >Subject: Re: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP >calls > >On Thu, May 25, 2023 at 11:29:34AM +, Duan, Zhenzhong wrote: >> Hi Peter, >> >> See inline. >> >-Original Message- >> >Fro

[PATCH v2 5/6] target/tricore: Fix wrong PSW for call insns

we were copying PSW into a local variable, updated PSW.CDE in the local and never wrote it back. So when we called save_context_upper() we were using the non-local version of PSW which did not contain the updated PSW.CDE. Signed-off-by: Bastian Koppelmann --- target/tricore/op_helper.c | 2 ++ 1

[PATCH v2 6/6] tests/tcg/tricore: Add recursion test for CSAs

Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 3 ++- tests/tcg/tricore/c/test_context_save_areas.c | 15 +++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/tricore/c/test_context_save_areas.c diff --git a/tests/

[PATCH v2 4/6] target/tricore: Refactor PCXI/ICR register fields

starting from ISA version 1.6.1 (previously known as 1.6P/E), some bitfields in PCXI and ICR have changed. We also refactor these registers using the register fields API. Signed-off-by: Bastian Koppelmann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1453 --- v1 -> v2: - Created ice

[PATCH v2 3/6] tests/tcg/tricore: Add first C program

this allows us to exercise the startup code used by GCC to call main(). Signed-off-by: Bastian Koppelmann --- configure | 1 + tests/tcg/tricore/Makefile.softmmu-target | 13 + tests/tcg/tricore/c/crt0-tc2x.S | 335 ++ tests/tcg/tr

[PATCH v2 2/6] tests/tcg/tricore: Uses label for memory addresses

the linker might rearrange sections, so lets reference memory by label name instead of addr + off. Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/asm/macros.h | 1 - tests/tcg/tricore/asm/test_ld_bu.S | 4 ++-- tests/tcg/tricore/asm/test_ld_h.S | 8 3 files changed, 6 inse

[PATCH v2 1/6] tests/tcg/tricore: Move asm tests into 'asm' directory

this seperates these tests from the upcoming tests written in C. Also rename the compiled test to 'test_.asm.tst'. Signed-off-by: Bastian Koppelmann --- tests/tcg/tricore/Makefile.softmmu-target | 35 --- tests/tcg/tricore/{ => asm}/macros.h | 0 tests/tcg/tricore/{ =>

[PATCH v2 0/6] TriCore PCXI/ICR register fixes

Hi, the main motivator for this series was https://gitlab.com/qemu-project/qemu/-/issues/1453. To test that I'm not screwing up this refactor I also extended the tests by C programs so we can test the PCXI/ICR registers by recursive function call. Through these tests I also found a problem, where

Re: [PATCH v3 1/1] hw/arm/aspeed:Add vpd data for Rainier machine

On 5/25/23 21:57, Ninad Palsule wrote: Hello Cedric, On 5/25/23 1:37 AM, Cédric Le Goater wrote: [ ... ] However, regarding Cédric's log above, a reboot is expected on the first boot of a fresh image when there's valid VPD available. For the first boot of a fresh image we configure the kerne

Re: [PATCH v2 3/3] cpu, qdict, vl: Enable printing options for CPU type

This is really, really, *really* for maintainers of the code parsing -cpu to review. Code parsing -cpu: * parse_cpu_option() in cpu.c Eduardo Habkost (supporter:Machine core) Marcel Apfelbaum (supporter:Machine core) "Philippe Mathieu-Daudé" (reviewer:Machine core) Yanan Wang (review

[PATCH 3/3] hw/ufs: Support for UFS logical unit

This commit adds support for ufs logical unit. The LU handles processing for the SCSI command, unit descriptor query request. This commit enables the UFS device to process IO requests. Signed-off-by: Jeuk Kim --- hw/ufs/lu.c | 1441 ++ hw/ufs/mes

[PATCH 1/3] hw/ufs: Initial commit for emulated Universal-Flash-Storage

Universal Flash Storage (UFS) is a high-performance mass storage device with a serial interface. It is primarily used as a high-performance data storage device for embedded applications. This commit contains code for UFS device to be recognized as a UFS PCI device. Patches to handle UFS logical un

[PATCH 2/3] hw/ufs: Support for Query Transfer Requests

This commit makes the UFS device support query and nop out transfer requests. The next patch would be support for UFS logical unit and scsi command transfer request. Signed-off-by: Jeuk Kim --- hw/ufs/ufs.c | 967 ++- hw/ufs/ufs.h | 45 +++ 2 fil

[PATCH 0/3] hw/ufs: Add Universal Flash Storage (UFS) support

This patch series adds support for a new PCI-based UFS device. The UFS pci device id (PCI_DEVICE_ID_REDHAT_UFS) is not registered in the Linux kernel yet, so it does not work right away, but I confirmed that it works with Linux when the UFS pci device id is registered. I have also verified that i

Re: [PATCH v3 2/5] vdpa: add vhost_vdpa_reset_status_fd

On Thu, May 25, 2023 at 1:37 AM Eugenio Perez Martin wrote: > > On Wed, May 17, 2023 at 7:49 AM Jason Wang wrote: > > > > On Wed, May 17, 2023 at 1:46 PM Eugenio Perez Martin > > wrote: > > > > > > On Wed, May 17, 2023 at 5:14 AM Jason Wang wrote: > > > > > > > > On Tue, May 9, 2023 at 11:44 PM

Re: [PATCH v4 2/2] virtio-net: pass Device-TLB enable/disable events to vhost

On Thu, May 25, 2023 at 8:58 PM Viktor Prutyanov wrote: > > If vhost is enabled for virtio-net, Device-TLB enable/disable events > must be passed to vhost for proper IOMMU unmap flag selection. > > Signed-off-by: Viktor Prutyanov Acked-by: Jason Wang Thanks > --- > hw/net/virtio-net.c | 1 +

Re: [PATCH v4 1/2] vhost: register and change IOMMU flag depending on Device-TLB state

On Thu, May 25, 2023 at 8:58 PM Viktor Prutyanov wrote: > > The guest can disable or never enable Device-TLB. In these cases, > it can't be used even if enabled in QEMU. So, check Device-TLB state > before registering IOMMU notifier and select unmap flag depending on > that. Also, implement a way

Re: [PATCH v2 0/7] target/riscv: Add support for PC-relative translation

On Wed, May 24, 2023 at 12:15 AM Weiwei Li wrote: > > This patchset tries to add support for PC-relative translation. > > The existence of CF_PCREL can improve performance with the guest > kernel's address space randomization. Each guest process maps libc.so > (et al) at a different virtual addre

Re: [PATCH] cryptodev: Handle unexpected request to avoid crash

> On Apr 27, 2023, at 16:05, zhenwei pi wrote: > > Generally guest side should discover which services the device is > able to offer, then do requests on device. > > However it's also possible to break this rule in a guest. Handle > unexpected request here to avoid NULL pointer dereference. >

Re: [PATCH v3] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"

On Tue, May 23, 2023 at 8:29 PM Sunil V L wrote: > > Currently, virt machine supports two pflash instances each with > 32MB size. However, the first pflash is always assumed to > contain M-mode firmware and reset vector is set to this if > enabled. Hence, for S-mode payloads like EDK2, only one pf

Re: Re: [PATCH] linux-user/i386: Properly align signal frame

"The beginning of the structure, with pretaddr, should be just below 16-byte alignment." It is incorrect! The beginning of the structure, with pretaddr not aligned as 16-byte! On x86-64, It aligned as (16n - sizeof(void*)) because of instruction "call" ! > -原始邮件- > 发件人: "Richard He

Re: [PATCH 2/2] docs/clx: Change to lowercase as others

On 25/05/2023 19:49, Jonathan Cameron via wrote: > On Fri, 19 May 2023 16:58:02 +0800 > Li Zhijian wrote: > >> Using the same style except the 'Topo' abbreviation. >> >> Signed-off-by: Li Zhijian >> --- >> I'm not a native speaker, feel free to correct me. > > I've edited slightly and applied

Re: [PATCH v2 7/7] target/riscv: Remove pc_succ_insn from DisasContext

On Wed, May 24, 2023 at 12:07 AM Weiwei Li wrote: > > pc_succ_insn is no longer useful after the introduce of cur_insn_len > and all pc related value use diff value instead of absolute value. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair >

Re: [PATCH v2 6/7] target/riscv: Enable PC-relative translation

On Wed, May 24, 2023 at 12:12 AM Weiwei Li wrote: > > Add a base pc_save for PC-relative translation(CF_PCREL). > Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb. > Use gen_pc_plus_diff to get the pc-relative address. > Enable CF_PCREL in System mode. > > Signed-off-by: Weiwei

Re: [PATCH v2 5/7] target/riscv: Use true diff for gen_pc_plus_diff

On Wed, May 24, 2023 at 12:14 AM Weiwei Li wrote: > > Reduce reliance on absolute values by using true pc difference for > gen_pc_plus_diff() to prepare for PC-relative translation. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > ta

Re: [PATCH v2 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc

On Wed, May 24, 2023 at 12:08 AM Weiwei Li wrote: > > Reduce reliance on absolute values(by passing pc difference) to > prepare for PC-relative translation. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/tra

[PATCH v2 0/4] tests/decode: Convert tests to meson

Add --test-for-error to decodetree.py and convert the tests to meson. This exposes an exception error that had been hidden by the fact that the script as a whole did exit with error. Which proves that this is a better way to run the tests. r~ Richard Henderson (4): decodetree: Add --test-for

[PATCH v2 1/4] decodetree: Add --test-for-error

Invert the exit code, for use with the testsuite. Signed-off-by: Richard Henderson --- scripts/decodetree.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index a03dc6b5e3..3f9f6876f7 100644 --- a/scripts/decodetree.py

[PATCH v2 4/4] tests/decode: Convert tests to meson

Signed-off-by: Richard Henderson --- tests/decode/check.sh| 24 tests/decode/meson.build | 59 tests/meson.build| 5 +--- 3 files changed, 60 insertions(+), 28 deletions(-) delete mode 100755 tests/decode/check.sh create mod

[PATCH v2 3/4] decodetree: Diagnose empty pattern group

Test err_pattern_group_empty.decode failed with exception: Traceback (most recent call last): File "./scripts/decodetree.py", line 1424, in main() File "./scripts/decodetree.py", line 1342, in main toppat.build_tree() File "./scripts/decodetree.py", line 627, in build_tree self.tree = s

[PATCH v2 2/4] decodetree: Fix recursion in prop_format and build_tree

Two copy-paste errors walking the parse tree. Signed-off-by: Richard Henderson --- scripts/decodetree.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 3f9f6876f7..e2640cc79b 100644 --- a/scripts/decodetree.py +++ b/scr

Re: [PATCH v2 3/7] target/riscv: Change gen_goto_tb to work on displacements

On Wed, May 24, 2023 at 12:14 AM Weiwei Li wrote: > > Reduce reliance on absolute value to prepare for PC-relative translation. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- > targ

Re: [PATCH v2 2/7] target/riscv: Introduce cur_insn_len into DisasContext

On Wed, May 24, 2023 at 12:16 AM Weiwei Li wrote: > > Use cur_insn_len to store the length of the current instruction to > prepare for PC-relative translation. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/translate.c

Re: [PATCH v2 0/8] Add support for extension specific disas

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Some extensions have conflict encodings, such as > * Z*inx reuse the same encodings as normal float point extensions. > * Zcm* reuse the some encodings of Zcd. > * Custom extensions from different vendors may share the same encodings. > To re

Re: [PATCH v3 2/3] vhost: register and change IOMMU flag depending on Device-TLB state

On Thu, May 25, 2023 at 8:55 PM Viktor Prutyanov wrote: > > On Wed, May 24, 2023 at 11:25 AM Jason Wang wrote: > > > > On Sat, May 20, 2023 at 1:50 AM Viktor Prutyanov wrote: > > > > > > On Thu, May 18, 2023 at 9:14 AM Jason Wang wrote: > > > > > > > > On Fri, May 12, 2023 at 9:51 PM Viktor Pru

Re: [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Remove redundant parenthese and fix multi-line comments. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > disas/riscv.c | 219 +

Re: [PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters

On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote: > > Fix lines with over 80 characters. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > disas/riscv.c | 201 +++

Re: [PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector > instructions are the same op index as their own. And they have no > functional decomp_data. So they have no functional difference from just > leaving them as zero. > > Signe

Re: [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions

On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote: > > Support disas for Z*inx instructions only when Zfinx extension is supported. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > disas/riscv.c

Re: [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions

On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote: > > Support disas for Zcmt* instructions only when related extensions > are supported. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > disas/ri

Re: [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Pass RISCVCPUConfig as disassemble_info.target_info to support disas > of conflict instructions related to specific extensions. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: A

Re: [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Use pointer to pass more information of target to disasembler, > such as pass cpu.cfg related information in following commits. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Daniel Henrique Barboza Reviewed-by: A

Re: [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h

On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote: > > Split RISCVCPUConfig declarations to prepare for passing it to disas. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 114 +---

Re: [PATCH v5 0/3] Smstateen FCSR

On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale wrote: > > Patch 4 and 5 of the smstateen series need to be re-submitted with > changes described in the email below. > https://lists.nongnu.org/archive/html/qemu-riscv/2022-11/msg00155.html > Hence splitting the patch 4 of the original series into

Re: [PATCH v5 2/3] target/riscv: Reuse tb->flags.FS

On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale wrote: > > When misa.F is 0 tb->flags.FS field is unused and can be used to save > the current state of smstateen0.FCSR check which is needed by the > floating point translation routines. > > Signed-off-by: Mayuresh Chitale > Reviewed-by: Richard H

Re: [PATCH v5 1/3] target/riscv: smstateen check for fcsr

On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale wrote: > > Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec > and check for it when accessing the fcsr register and its fields. > > Signed-off-by: Mayuresh Chitale > Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Alist

[PATCH v4 10/16] tcg/ppc: Support 128-bit load/store

Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h | 2 + tcg/ppc/tcg-target-con-str.h | 1 + tcg/ppc/tcg-target.h

[PATCH v4 09/16] tcg/aarch64: Support 128-bit load/store

With FEAT_LSE2, LDP/STP suffices. Without FEAT_LSE2, use LDXP+STXP 16-byte atomicity is required and LDP/STP otherwise. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 + tcg/aarch64/tcg-target.h | 11 ++- tcg/aarch64/tcg-target.c

[PATCH v4 07/16] tcg/aarch64: Reserve TCG_REG_TMP1, TCG_REG_TMP2

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 8996e29ca9..5e7ac6fb76 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-t

[PATCH v4 15/16] accel/tcg: Add aarch64 lse2 load_atom_extract_al16_or_al8

Signed-off-by: Richard Henderson --- .../aarch64/host/load-extract-al16-al8.h | 40 +++ 1 file changed, 40 insertions(+) create mode 100644 host/include/aarch64/host/load-extract-al16-al8.h diff --git a/host/include/aarch64/host/load-extract-al16-al8.h b/host/include/aarch

[PATCH v4 08/16] tcg/aarch64: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use TMP[0-2], not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-con-set.h | 2 -- tcg/aarch64/tcg-target-con-str.h | 1

Re: [PATCH] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

On 5/25/23 16:51, Richard Henderson wrote: PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +-

Re: [PATCH] tcg: Fix register move type in tcg_out_ld_helper_ret

On 5/24/23 13:02, Richard Henderson wrote: The first move was incorrectly using TCG_TYPE_I32 while the second move was correctly using TCG_TYPE_REG. This prevents a 64-bit host from moving all 128-bits of the return value. Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_help

[PATCH v4 11/16] tcg/s390x: Support 128-bit load/store

Use LPQ/STPQ when 16-byte atomicity is required. Note that these instructions require 16-byte alignment. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 103

[PATCH v4 12/16] accel/tcg: Extract load_atom_extract_al16_or_al8 to host header

Signed-off-by: Richard Henderson --- .../generic/host/load-extract-al16-al8.h | 45 +++ accel/tcg/ldst_atomicity.c.inc| 36 +-- 2 files changed, 47 insertions(+), 34 deletions(-) create mode 100644 host/include/generic/host/load-extract-al16-al8.h

[PATCH v4 16/16] accel/tcg: Add aarch64 store_atom_insert_al16

Signed-off-by: Richard Henderson --- host/include/aarch64/host/store-insert-al16.h | 47 +++ 1 file changed, 47 insertions(+) create mode 100644 host/include/aarch64/host/store-insert-al16.h diff --git a/host/include/aarch64/host/store-insert-al16.h b/host/include/aarch64/host/

[PATCH v4 00/16] tcg: Improvements to atomic128

This is a merge of a couple of singleton fixes, CONFIG_ATOMIC128 detection, and tcg backend code generation patch sets, just to keep everything in one place. Tested with the Arm FEAT_LSE2 patch set, which greatly increases the number of 16-byte atomic operations. Patches needing review: 01-tcg-

[PATCH v4 04/16] qemu/atomic128: Add x86_64 atomic128-ldst.h

With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic load/store without cmpxchg16b. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- host/include/x86_64/host/atomic128-ldst.h | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 host/include/x86_64

[PATCH v4 03/16] meson: Split test for __int128_t type from __int128_t arithmetic

Older versions of clang have missing runtime functions for arithmetic with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use __int128_t for implementing Int128. But __int128_t is present, data movement works, and can be use for atomic128. Probe for both CONFIG_INT128_TYPE and CONFIG_INT1

[PATCH v4 01/16] tcg: Fix register move type in tcg_out_ld_helper_ret

The first move was incorrectly using TCG_TYPE_I32 while the second move was correctly using TCG_TYPE_REG. This prevents a 64-bit host from moving all 128-bits of the return value. Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in tcg_out_{ld,st}_helper_{args,ret}") Signed-off-by: Richard Hender

Re: [PATCH v3 0/2] accel/tcg: Improvements to atomic128.h

On 5/24/23 11:32, Richard Henderson wrote: Changes for v3: * Most of the v2 patch set merged, except x86_64 atomic128-ldst.h, which failed testing with clang-11 with debian 11. * New patch to change __int128_t detection. * This in turn enabled CONFIG_ATOMIC128, which was not ideal

[PATCH v4 14/16] accel/tcg: Add x86_64 load_atom_extract_al16_or_al8

Signed-off-by: Richard Henderson --- .../x86_64/host/load-extract-al16-al8.h | 50 +++ 1 file changed, 50 insertions(+) create mode 100644 host/include/x86_64/host/load-extract-al16-al8.h diff --git a/host/include/x86_64/host/load-extract-al16-al8.h b/host/include/x86_64/

[PATCH v4 05/16] tcg/i386: Support 128-bit load/store

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 +- tcg/i386/tcg-target.c.inc | 191 +- 2 files changed, 190 insertions(+), 5 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 0106946996..b167f1e8d6 100644 --- a

[PATCH v4 13/16] accel/tcg: Extract store_atom_insert_al16 to host header

Signed-off-by: Richard Henderson --- host/include/generic/host/store-insert-al16.h | 50 +++ accel/tcg/ldst_atomicity.c.inc| 40 +-- 2 files changed, 51 insertions(+), 39 deletions(-) create mode 100644 host/include/generic/host/store-insert-al16.h di

[PATCH v4 06/16] tcg/aarch64: Rename temporaries

We will need to allocate a second general-purpose temporary. Rename the existing temps to add a distinguishing number. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 ++-- 1 file changed, 25 insertions(+), 25 del

[PATCH v4 02/16] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] accel/tcg: Fix check for page writeability in load_atomic16_or_exit

PAGE_WRITE is current writability, as modified by TB protection; PAGE_WRITE_ORG is the original page writability. Fixes: cdfac37be0d ("accel/tcg: Honor atomicity of loads") Signed-off-by: Richard Henderson --- accel/tcg/ldst_atomicity.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH v2 14/20] target/arm: Check alignment in helper_mte_check

Fixes a bug in that with SCTLR.A set, we should raise any alignment fault before raising any MTE check fault. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/tcg/mte_helper.c| 18 ++ target/arm/tcg/translate

[PATCH v2 09/20] target/arm: Load/store integer pair with one tcg operation

This is required for LSE2, where the pair must be treated atomically if it does not cross a 16-byte boundary. But it simplifies the code to do this always. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 70 ++ 1

[PATCH v2 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP

While we don't require 16-byte atomicity here, using a single larger load simplifies the code, and makes it a closer match to STXP. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 31 --- 1 file changed, 20 insertions(+), 11 deletions(-) diff --

[PATCH v2 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/tcg/translate.h | 2 ++ target/arm/tcg/hflags.c| 6 ++ target/arm/tcg/translate-a64.c | 1 + 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/ar

[PATCH v2 20/20] target/arm: Enable FEAT_LSE2 for -cpu max

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c| 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 7338987875..ecbbd63adf 100644 --- a/docs/sy

[PATCH v2 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c

We have many other instances of stg in the testsuite; change these to provide an instance of stz2g. Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-7.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/tcg/aarch64/mte-7.c b/tests/tcg/aarch64/mte-7.c index a98

[PATCH v2 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G

This fixes a bug in that these two insns should have been using atomic 16-byte stores, since MTE is ARMv8.5 and LSE2 is mandatory from ARMv8.4. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 17 ++--- 1 file changed, 10 insertions(+)

[PATCH v2 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2

FEAT_LSE2 only requires that atomic operations not cross a 16-byte boundary. Ordered operations may be completely unaligned if SCTLR.nAA is set. Because this alignment check is so special, do it by hand. Make sure not to keep TCG temps live across the branch. Signed-off-by: Richard Henderson --

[PATCH v2 03/20] target/arm: Introduce finalize_memop_{atom,pair}

Let finalize_memop_atom be the new basic function, with finalize_memop and finalize_memop_pair testing FEAT_LSE2 to apply the appropriate atomicity. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 39 +- target/arm/tcg/translate-a64.c | 2 ++

[PATCH v2 19/20] tests/tcg/multiarch: Adjust sigbus.c

With -cpu max and FEAT_LSE2, the __aarch64__ section will only raise an alignment exception when the load crosses a 16-byte boundary. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/multiarch/sigbus.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-)

[PATCH v2 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive

No need to duplicate this check across multiple call sites. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 44 -- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/ta

[PATCH v2 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 61 +++--- 1 file changed, 35 insertions(+), 26 deletions(-) diff --git a/target/arm/t

[PATCH v2 13/20] target/arm: Pass single_memop to gen_mte_checkN

Pass the individual memop to gen_mte_checkN. For the moment, do nothing with it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 31 +++ target/arm/tcg/translate-sve.c | 4 ++--

[PATCH v2 00/20] target/arm: Implement FEAT_LSE2

v1: https://patchew.org/QEMU/20230216030854.1212208-1-richard.hender...@linaro.org/ All prerequisites are upstream. There are still outstanding patches to improve the atomic16 support, but those are all optimizations. Patches needing r-b: 01-target-arm-Add-commentary-for-CPUARMState.exclusi.p

[PATCH v2 01/20] target/arm: Add commentary for CPUARMState.exclusive_high

Document the meaning of exclusive_high in a big-endian context, and why we can't change it now. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d469a2637b..4e16eab82e 100644 --- a/target/ar

[PATCH v2 02/20] target/arm: Add feature test for FEAT_LSE2

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4e16eab82e..36ab66d0c3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3850,6 +3850,11 @@ static inline boo

[PATCH v2 07/20] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r

Round len_align to 16 instead of 8, handling an odd 8-byte as part of the tail. Use MO_ATOM_NONE to indicate that all of these memory ops have only byte atomicity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-sve.c | 95 +-

[PATCH v2 12/20] target/arm: Pass memop to gen_mte_check1*

Pass the completed memop to gen_mte_check1_mmuidx. For the moment, do nothing more than extract the size. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.h | 2 +- target/arm/tcg/translate-a64.c | 82 ++ target/arm/tc

[PATCH v2 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}

While we don't require 16-byte atomicity here, using a single larger operation simplifies the code. Introduce finalize_memop_asimd for this. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 24 +++ target/arm/tcg/translate-a64.c | 35 +++-

[PATCH v2 17/20] target/arm: Move mte check for store-exclusive

Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 +- 1 file changed, 36 insert

[PATCH v2 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st}

We are going to need the complete memop beforehand, so let's not compute it twice. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 43 ++ 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/target/arm/t

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