com/vivier/qemu.git tags/linux-user-for-8.1-pull-request
for you to fetch changes up to 3e7f6c76d529dd4096d043cbd16593e40b469e70:
linux-user: fix getgroups/setgroups allocations (2023-05-05 14:37:05 +0200)
linux-user pull reques
On Fri May 5, 2023 at 9:09 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Create spapr_nested.c for the nested HV implementation (modulo small
> > pieces in MMU and exception handling).
> >
> This separation of nested code in its own file is very much needed,
On Fri May 5, 2023 at 9:03 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > Arguably this is just shuffling around register accesses, but one nice
> > thing it does is allow the exit to save away the L2 state then switch
> > the environment to the L1 before copy
On Fri May 5, 2023 at 8:54 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 5/3/23 06:09, Nicholas Piggin wrote:
> > @@ -1593,12 +1713,14 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu,
> > return H_PARAMETER;
> > }
> >
> > -spapr_cpu->nested_host_state = g_try_new(CPUPPCS
在 2023/5/12 下午7:44, Cédric Le Goater 写道:
Hello,
On 5/12/23 08:33, Song Gao wrote:
Add a new test in tests/avocado to check LoongArch virt machine start.
Reviewed-by: Thomas Huth
Signed-off-by: Song Gao
---
MAINTAINERS | 1 +
tests/avocado/machine_loongarch.py |
Add a new test in tests/avocado to check LoongArch virt machine start.
Reviewed-by: Thomas Huth
Signed-off-by: Song Gao
---
MAINTAINERS| 1 +
tests/avocado/machine_loongarch.py | 58 ++
2 files changed, 59 insertions(+)
create mode 100644 te
Signed-off-by: Taylor Simpson
Co-authored-by: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Brian Cain
Message-Id:
<17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathb...@quicinc.com>
---
From: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
---
MAINTAINERS| 1 +
configs/targets/hexagon-linux-user.mak | 1 +
target/hexagon/cpu.c | 3 +-
From: Matheus Tavares Bernardino
In the previous commit, we modified gdbstub.c to only send stop-reply
packets as a response to GDB commands that accept it. Now, let's add a
test for this intended behavior. Running this test before the fix from
the previous commit fails as QEMU sends a stop-reply
From: Brian Cain
Signed-off-by: Brian Cain
Co-authored-by: Sid Manning
Signed-off-by: Sid Manning
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Taylor Simpson
Signed-off-by: Taylor Simpson
Message-Id:
<32e7de567cdae184a6781644454bbb19916
From: Matheus Tavares Bernardino
This enables LLDB to work with hexagon linux-user mode through the GDB
remote protocol.
Helped-by: Richard Henderson
Signed-off-by: Matheus Tavares Bernardino
Reviewed-by: Richard Henderson
Signed-off-by: Taylor Simpson
Message-Id:
---
linux-user/hexagon/c
Enable conditional compilation depending on whether idef-parser
is configured
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-2-tsimp...@quicinc.com>
---
meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/meson.build b/meson.build
in
The following have overrides
S2_insert
S2_insert_rp
S2_asr_r_svw_trun
A2_swiz
These instructions have semantics that write to the destination
before all the operand reads have been completed. Therefore,
the idef-parser versions were disabled with the short-circuit patch.
Test cas
With the overrides added in prior commits, this function is not used
Remove references in macros.h
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-7-tsimp...@quicinc.com>
---
target/hexagon/macros.h| 14 --
target/hexagon/op_helpe
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
branch
From: Matheus Tavares Bernardino
Running qemu-hexagon with a binary that was compiled for an arch version
unknown by qemu can produce a somewhat confusing message:
qemu-hexagon: unable to find CPU model 'unknown'
Let's give a bit more info by appending the eflags so that the message
becomes:
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-5-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 32 +
Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-11-tsimp...@quicinc.com>
---
target/hexagon/translate.h
Precursor to moving new_value from the global state to DisasContext
USR will need to stay in the global state because some helpers will
set it's value
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-17-tsimp...@quicinc.com>
---
target/hexagon/cp
In certain cases, we can avoid the overhead of writing to future_VRegs
and write directly to VRegs. We consider HVX reads/writes when computing
ctx->need_commit. Then, we can early-exit from gen_commit_hvx.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <2023042723001
In certain cases, we can avoid the overhead of writing to hex_new_value
and write directly to hex_gpr. We add need_commit field to DisasContext
indicating if the end-of-packet commit is needed. If it is not needed,
get_result_gpr() and get_result_gpr_pair() can return hex_gpr.
We pass the ctx->n
Tests added for the following instructions
J2_callrh
J2_jumprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-10-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v73_scalar.c| 96 +++
tests/tcg/hexagon/Makefile.t
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Acked-by: Richard Henderson
Message-Id: <20230427230012.3800327-4-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 21 +++
target/
These instructions have implicit writes to registers, so we don't
want them to be helpers when idef-parser is off.
The following instructions are overriden
S2_cabacdecbin
SA1_cmpeqi
Remove the log_pred_write function from op_helper.c
Remove references in macros.h
Signed-off-by: Taylor Si
Add DisasContext arg to gen_log_reg_write_pair also
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-3-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h| 2 +-
target/hexagon/genptr.h | 2 +-
target/hexag
The new_value array in the CPUHexagonState is only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Taylor Si
From: Matheus Tavares Bernardino
GDB's remote serial protocol allows stop-reply messages to be sent by
the stub either as a notification packet or as a reply to a GDB command
(provided that the cmd accepts such a response). QEMU currently does not
implement notification packets, so it should only
The pred_written variable in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Tay
Only endloop instructions will conditionally write to a predicate.
When there is an endloop instruction, we preload the values into
new_pred_value.
The only place pred_written is needed is when HEX_DEBUG is on.
We remove the last use of check_for_attrib. However, new uses will be
introduced late
From: Paolo Bonzini
Changes in v2
Fix yyassert's for sign and zero extends
Coverity reports a parameter that is "set but never used". This is caused
by an assignment operator being used instead of equality.
Co-authored-by: Taylor Simpson
Signed-off-by: Paolo Bonzini
Signed-off-by:
From: Matheus Tavares Bernardino
Currently, qemu-hexagon only models the v67 cpu. Nonetheless if we try
to get this information with `-cpu help`, qemu just exists with an error
code and no output. Let's correct that.
The code is basically a copy from target/alpha/cpu.h, but we strip the
"-hexago
From: Matheus Tavares Bernardino
Each slot in a packet can be assigned to at most one instruction.
Although the assembler generally ought to enforce this rule, we better
be safe than sorry and also do some check to properly throw an "invalid
packet" exception on wrong slot assignments.
This shou
The following instructions are added
L2_loadw_aq
L4_loadd_aq
R6_release_at_vi
R6_release_st_vi
S2_storew_rl_at_vi
S4_stored_rl_at_vi
S2_storew_rl_st_vi
S4_stored_rl_st_vi
The release instructions are nop's in qemu. The others behave as
loads/stores.
The encodings
When generating TCG, make sure we have read all the operand registers
before writing to the destination registers.
This is a prerequesite for short-circuiting where the source and dest
operands could be the same.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-6-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_hvx.c | 90 +
tests/tcg/hexagon/v6mpy_ref.c.inc | 161 ++
tests/tcg/hexagon/Makefile.target | 3 +
From: Matheus Tavares Bernardino
Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which mi
The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.
These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1 in
The following changes since commit 278238505d28d292927bff7683f39fb4fbca7fd1:
Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into
staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20230512-1
Changes in v3
Fix bugs exposed by dpmpyss_rnd_s0 instruction
Set correct size/signedness for constants
Test cases added to tests/tcg/hexagon/misc.c
Changes in v2
Fix bug in imm_print identified in clang build
Currently, idef-parser skips all floating point instructions
In certain cases, we can avoid the overhead of writing to hex_new_pred_value
and write directly to hex_pred. We consider predicate reads/writes when
computing ctx->need_commit. The get_result_pred() function uses this
field to decide between hex_new_pred_value and hex_pred. Then, we can
early-ex
From: Marco Liebel
test_vshuff checks that the vshuff instruction works correctly when
both vector registers are the same. Using vshuff in this way is
undefined and will be rejected by the compiler in a future version of
the toolchain.
Signed-off-by: Marco Liebel
Reviewed-by: Brian Cain
Review
The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.
We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-8-tsimp...@quicinc.com>
Add support for the ELF flags
Move target/hexagon/cpu.[ch] to be v73
Change the compiler flag used by "make check-tcg"
The decbin instruction is removed in Hexagon v73, so check the
version before trying to compile the instruction.
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Mess
The following instructions are added
V6_v6mpyvubs10_vxx
V6_v6mpyhubs10_vxx
V6_v6mpyvubs10
V6_v6mpyhubs10
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-5-tsimp...@quicinc.com>
---
target/hexagon/mmvec/macros.h| 9
These instructions have implicit reads from p0, so we don't want
them in helpers when idef-parser is off.
Signed-off-by: Taylor Simpson
Reviewed-by: Richard Henderson
Message-Id: <20230427230012.3800327-6-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 16
target/hexagon/m
The new_pred_value array in the CPUHexagonState is only used for
bookkeeping within the translation of a packet. With recent changes
that eliminate the need to free TCGv variables, these make more sense
to be transient and kept in DisasContext.
Suggested-by: Richard Henderson
Signed-off-by: Tayl
The following instructions are added
J2_callrh
J2_junprh
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-9-tsimp...@quicinc.com>
---
target/hexagon/gen_tcg.h | 4
target/hexagon/attribs_def.h.inc | 1 +
target/hexagon
From: Matheus Tavares Bernardino
The Hexagon PRM says that "The assembler automatically encodes
instructions in the packet in the proper order. In the binary encoding
of a packet, the instructions must be ordered from Slot 3 down to
Slot 0."
Prior to the architecture version v73, the slot constr
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-4-tsimp...@quicinc.com>
---
tests/tcg/hexagon/v68_scalar.c| 186 ++
tests/tcg/hexagon/Makefile.target | 2 +
2 files changed, 188 insertions(+)
create mode 100644 tes
The following instructions are added
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson
Reviewed-by: Anton Johansson
Message-Id: <20230427224057.3766963-7-tsimp...@quicinc.com>
-
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Thursday, May 4, 2023 10:38 AM
> To: qemu-devel@nongnu.org
> Cc: alex.ben...@linaro.org; Brian Cain ;
> f4...@amsat.org; peter.mayd...@linaro.org; Taylor Simpson
> ; phi...@linaro.org; richard.hender...@linaro.org;
> Laurent V
On Wed, 10 May 2023, Olaf Hering wrote:
> Wed, 10 May 2023 00:58:27 +0200 Olaf Hering :
>
> > In my debugging (with v8.0.0) it turned out the three pci_set_word
> > causes the domU to hang. In fact, it is just the last one:
> >
> >pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */
> >
On Thu, May 11, 2023 at 09:10:31PM -0500, Eric Blake wrote:
>
> Rather than open-coding two different ways to check for an unwanted
> negative sign, reuse the same code in both functions. That way, if we
> decide down the road to accept "-0" instead of rejecting it, we have
> fewer places to ch
On Fri, May 12, 2023 at 11:16:03AM -0500, Eric Blake wrote:
>
>
> On Wed, May 10, 2023 at 10:35:55PM +0200, Kevin Wolf wrote:
> >
> > There are some error paths in blk_exp_add() that jump to 'fail:' before
> > 'exp' is even created. So we can't just unconditionally access exp->blk.
> >
> > Ad
On 5/11/23 12:56, Fan Ni wrote:
> From: Fan Ni
>
> Add dynamic capacity extent information to the definition of
> CXLType3Dev and add get DC extent list mailbox command based on
> CXL.spec.3.0:.8.2.9.8.9.2.
>
> With this command, we can create dc regions as below:
>
> region=$(cat /sys/bus/cxl/
Is there a way to execute a long-standing QMP command outside of the
BQL?
The situation we're seeing is a slow query-block due to a slow system
call (fstat over NFS) causing the main thread to spend too long
holding the global mutex and locking up the vcpu thread when it goes
out of the guest for
On 12/5/23 12:04, Song Gao wrote:
ipi is used to communicate between cpus, this patch modified
loongarch ipi device as percpu deivce, so that there are
"device"
2 MemoryRegions with ipi device, rather than 2*cpus
MemoryRegions, which may be large than QDEV_MAX_MMIO if
more cpus are added on l
The REXW bit must be set to produce a 64-bit pointer result; the
bit is disabled in 32-bit mode, so we can do this unconditionally.
Fixes: 7d9e1ee424b0 ("tcg/i386: Adjust assert in tcg_out_addi_ptr")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1592
Resolves: https://gitlab.com/qemu-pro
Peter Maydell writes:
> On Tue, 9 May 2023 at 19:58, Peter Maydell wrote:
>>
>> I just noticed that the guest console output seems to no longer
>> be in the avocado log file. Can it be reinstated, please?
>> The console logs are typically the most useful clue to "why did this
>> test fail" and
This patchset fixes two minor Coverity issues which are
entirely unrelated apart from both being in arm target code.
thanks
-- PMM
Peter Maydell (2):
target/arm: Saturate L2CTLR_EL1 core count field rather than
overflowing
hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'
hw/ar
In the vexpress board code, we allocate a new MemoryRegion at the top
of vexpress_common_init() but only set it up and use it inside the
"if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not.
This isn't a very interesting leak as it's a tiny amount of memory
once at startup, but it's
The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72
and which we (arguably dubiously) also provide in '-cpu max' has a
2 bit field for the number of processors in the cluster. On real
hardware this must be sufficient because it can only be configured
with up to 4 CPUs in the cluster
On Thu, May 11, 2023 at 09:10:22PM -0500, Eric Blake wrote:
>
> All the qemu_strto*() functions permit a NULL endptr, just like their
> libc counterparts, leaving parse_uint() as the oddball that caused
> SEGFAULT on NULL and required the user to call parse_uint_full()
> instead. Relax things f
On Wed, May 10, 2023 at 10:36:01PM +0200, Kevin Wolf wrote:
>
> There are some conditions under which we don't actually need to do
> anything for taking a reader lock: Writing the graph is only possible
> from the main context while holding the BQL. So if a reader is running
> in the main contex
On Wed, May 10, 2023 at 10:36:00PM +0200, Kevin Wolf wrote:
>
> When jobs are sleeping, for example to enforce a given rate limit, they
> can be reentered early, in particular in order to get paused, to update
> the rate limit or to get cancelled.
>
> Before this patch, they behave in this case
On Wed, May 10, 2023 at 10:35:59PM +0200, Kevin Wolf wrote:
>
> bdrv_unref() is a no_coroutine_fn, so calling it from coroutine context
> is invalid. Use bdrv_co_unref() instead.
>
> Signed-off-by: Kevin Wolf
> ---
> tests/unit/test-bdrv-drain.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
On Wed, May 10, 2023 at 10:35:58PM +0200, Kevin Wolf wrote:
>
> If we take a reader lock, we can't call any functions that take a writer
> lock internally without causing deadlocks once the reader lock is
> actually enforced in the main thread, too. Take the reader lock only
> where it is actual
On Thu, May 11, 2023 at 09:10:21PM -0500, Eric Blake wrote:
>
> It's already confusing that we have two very similar functions for
> wrapping the parse of a 64-bit unsigned value, differing mainly on
> whether they permit leading '-'. Adjust the signature of parse_uint()
> and parse_uint_full()
On Wed, May 10, 2023 at 10:35:57PM +0200, Kevin Wolf wrote:
>
> If we take a reader lock, we can't call any functions that take a writer
> lock internally without causing deadlocks once the reader lock is
> actually enforced in the main thread, too. Take the reader lock only
> where it is actual
On Wed, May 10, 2023 at 10:35:56PM +0200, Kevin Wolf wrote:
>
> qcow2_do_open() calls a few no_co_wrappers that wrap functions taking
> the graph lock internally as a writer. Therefore, it can't hold the
> reader lock across these calls, it causes deadlocks. Drop the lock
> temporarily around th
On Wed, May 10, 2023 at 10:35:55PM +0200, Kevin Wolf wrote:
>
> There are some error paths in blk_exp_add() that jump to 'fail:' before
> 'exp' is even created. So we can't just unconditionally access exp->blk.
>
> Add a NULL check, and switch from exp->blk to blk, which is available
> earlier,
On Wed, May 10, 2023 at 10:35:54PM +0200, Kevin Wolf wrote:
>
> These are functions that modify the graph, so they must be able to take
> a writer lock. This is impossible if they already hold the reader lock.
> If they need a reader lock for some of their operations, they should
> take it inter
W dniu 12.05.2023 o 18:02, Leif Lindholm pisze:
Longer-term, I still want to move to "max" as the default, but that is
likely to require some invasive changes to TF-A, and this is already a
huge improvement.
Firmware was main reason why I not moved to "max". It is easier to keep
system runnin
On 2023-05-12 15:50, Peter Maydell wrote:
On Sat, 6 May 2023 at 19:34, Marcin Juszkiewicz
wrote:
The world outside moves to newer and newer cpu cores. Let move SBSA
Reference Platform to something newer as well.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 2 +-
1 file change
sigframe::pretcode & rt_sigframe::pretcode must align of 16n-sizeof(void*)
instead of 16n, Because rsp align of 16n before instruction "call" in caller,
After "call", push address of "call" in caller. sp of begin in callee is
16n-sizeof(void*)
Resolves: https://gitlab.com/qemu-project/qemu/-/is
Le 12/05/2023 à 14:08, John Paul Adrian Glaubitz a écrit :
Hello Laurent!
On Fri, 2023-05-12 at 13:13 +0200, Laurent Vivier wrote:
This patch breaks something with LTP (20230127) test fchown05_16 on sid/sparc64:
tst_test.c:1558: TINFO: Timeout per run is 0h 00m 30s
fchown05.c:44: TPASS: fchown
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol
---
hw/net/e1000e_core.c | 18 ++--
hw/net/igb_core.c| 216 +--
tests/qtest/libqos/igb.c | 5
Packet-split descriptors are used by Linux VF driver for MTU values from 2048
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 360 ++--
hw/net/igb_regs.h | 9 ++
hw/net/trace-events | 2 +-
3 files changed, 328 insertions(+), 43 deletions(-)
Based-on: <20230423041833.5302-1-akihiko.od...@daynix.com>
("[PATCH v3 00/47] igb: Fix for DPDK")
Purposes of this series of patches:
* introduce packet-split RX descriptors support. This feature is used by Linux
VF driver for MTU values from 2048.
* refactor RX descriptor handling for introduct
Rename e1000e_ba_state according to qemu typdefs guide.
Signed-off-by: Tomasz Dzieciol
---
hw/net/e1000e_core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
index f9ff31fd70..be0cf2f941 100644
--- a/hw/net/e1000e_core.
TCP ACK detection is no longer present in igb.
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 96b7335b31..012eb1e1b9 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1327,11 +1327,
Refactoring is done in preparation for support of multiple advanced
descriptors RX modes, especially packet-split modes.
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 176 ++--
hw/net/igb_regs.h | 10 +--
hw/net/trace-events | 6 +-
3 files
Signed-off-by: Tomasz Dzieciol
---
hw/net/igb_core.c | 4 +++-
hw/net/igb_regs.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index 0eabe7106e..6d95cccea3 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -1415,7 +1415,9 @@ igb
Rename E1000E_RingInfo_st and E1000E_RingInfo according to qemu typdefs guide.
Signed-off-by: Tomasz Dzieciol
---
hw/net/e1000e_core.c | 34 +-
hw/net/igb_core.c| 42 +-
2 files changed, 38 insertions(+), 38 deletions(-)
Bit 63 in a Table descriptor is only the NSTable bit for stage 1
translations; in stage 2 it is RES0. We were incorrectly looking at
it all the time.
This causes problems if:
* the stage 2 table descriptor was incorrectly setting the RES0 bit
* we are doing a stage 2 translation in Secure addre
We currently don't correctly handle the VSTCR_EL2.SW and VTCR_EL2.NSW
configuration bits. These allow configuration of whether the stage 2
page table walks for Secure IPA and NonSecure IPA should do their
descriptor reads from Secure or NonSecure physical addresses. (This
is separate from how the
From: Richard Henderson
These files got missed when populating tcg/.
Because they are included with "", no change to the users required.
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20230504110412.1892411-2-richard.hender...@linar
From: Fabiano Rosas
We cannot allow this config to be disabled at the moment as not all of
the relevant code is protected by it.
Commit 29d9efca16 ("arm/Kconfig: Do not build TCG-only boards on a
KVM-only build") moved the CONFIGs of several boards to Kconfig, so it
is now possible that nothing
From: Akihiko Odaki
I am now employed by Daynix. Although my role as a reviewer of
macOS-related change is not very relevant to the employment, I decided
to use the company email address to avoid confusions from different
addresses.
Signed-off-by: Akihiko Odaki
Reviewed-by: Marc-André Lureau
R
From: Richard Henderson
While we cannot move the main "helper.h" out of target/arm/,
due to usage by generic code, we can move the sub-includes.
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Message-id: 20230504110412.1892411-3-richard.hender...@linaro.org
Reviewed-by: Philippe M
When we take a PNG screenshot the ordering of the colour channels in
the data is not correct, resulting in the image having weird
colouring compared to the actual display. (Specifically, on a
little-endian host the blue and red channels are swapped; on
big-endian everything is wrong.)
This happen
From: Fabiano Rosas
Semihosting has been made a 'default y' entry in Kconfig, which does
not work because when building --without-default-devices, the
semihosting code would not be available.
Make semihosting unconditional when TCG is present.
Fixes: 29d9efca16 ("arm/Kconfig: Do not build TCG-o
In check_s2_mmu_setup() we have a check that is attempting to
implement the part of AArch64.S2MinTxSZ that is specific to when EL1
is AArch32:
if !s1aarch64 then
// EL1 is AArch32
min_txsz = Min(min_txsz, 24);
Unfortunately we got this wrong in two ways:
(1) The minimum txsz
In the doc sources, we have a few cross-reference targets with odd
names "pcsys_005fxyz". These are the legacy of the semi-automated
conversion of the old info docs to rST (the '005f' is because ASCII
0x5f is '_' and the old info link names had underscores in them).
Remove the targets which nothi
From: Fabiano Rosas
On a build configured with: --disable-tcg --enable-xen it is possible
to produce a QEMU binary with no TCG nor KVM support. Skip the cdrom
boot tests if that's the case.
Fixes: 0c1ae3ff9d ("tests/qtest: Fix tests when no KVM or TCG are present")
Signed-off-by: Fabiano Rosas
Coverity points out (in CID 1508390) that write_bootloader has
some dead code, where we assign to 'p' and then in the following
line assign to it again. This happened as a result of the
refactoring in commit cd5066f8618b.
Fix the dead code by removing the 'void *v' variable entirely and
instead ad
511-2' of https://gitlab.com/rth7680/qemu into
staging (2023-05-11 11:44:23 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230512
for you to fetch changes up to 478dccbb99db0bf8f00537dd0b4d0de88d5cb537:
target/
On Wed, 10 May 2023 at 21:38, Kevin Wolf wrote:
>
> There are some error paths in blk_exp_add() that jump to 'fail:' before
> 'exp' is even created. So we can't just unconditionally access exp->blk.
>
> Add a NULL check, and switch from exp->blk to blk, which is available
> earlier, just to be ext
Hi Peter,
On 5/12/23 16:46, Peter Maydell wrote:
> On Sat, 1 Apr 2023 at 11:49, Mostafa Saleh wrote:
>> This patch series adds stage-2 translation support for SMMUv3. It is
>> controlled by a new system property “arm-smmuv3.stage”.
>> - When set to “1”: Stage-1 only would be advertised and suppor
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