Re: [PATCH v4 00/48] igb: Fix for DPDK

On Thu, May 4, 2023 at 2:45 PM Akihiko Odaki wrote: > > Hi Jason, > > Can you have a look at this series as well as the patch pointed to by > Based-on: tag? Just come back from vacation, I will have a look at it. Thanks > > Regards, > Akihiko Odaki > > On 2023/04/26 19:36, Akihiko Odaki wrote:

Re: [RFC 0/7] vhost-vdpa: add support for iommufd

On Fri, May 5, 2023 at 11:29 AM Jason Wang wrote: > > Hi Cindy > > On Wed, May 3, 2023 at 5:13 PM Cindy Lu wrote: > > > > Hi All > > There is the RFC to support the IOMMUFD in vdpa device > > any comments are welcome > > Thanks > > Cindy > > Please post the kernel patch as well as a reference. >

Re: [PATCH] scripts/coverity-scan: Add xtensa and openrisc components

On Thu, May 04, 2023 at 02:45:26PM +0100, Peter Maydell wrote: > We have two target architectures which don't have Coverity components > defined for them: xtensa and openrisc. Add them. > > Signed-off-by: Peter Maydell > --- > As usual with coverity components, these will need to be added > manua

[PATCH] docs: vhost-user: VHOST_USER_GET_STATUS require reply

Add VHOST_USER_GET_STATUS to the list of requests that require a reply. Cc: Maxime Coquelin Cc: Michael S. Tsirkin Signed-off-by: Yajun Wu --- docs/interop/vhost-user.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index 8a5924e

Re: [PATCH v3 0/5] virtio-gpu cleanups and obvious definitions

On 2023/05/05 4:12, Gurchetan Singh wrote: From: Gurchetan Singh v3 of "virtio-gpu cleanups and obvious definitions" https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg05392.html All patches have been reviewed, though there was a question from Bernhard Beschow about patch (3) and how it

Re: [RFC 0/7] vhost-vdpa: add support for iommufd

Hi Cindy On Wed, May 3, 2023 at 5:13 PM Cindy Lu wrote: > > Hi All > There is the RFC to support the IOMMUFD in vdpa device > any comments are welcome > Thanks > Cindy Please post the kernel patch as well as a reference. Thanks > > Cindy Lu (7): > vhost: introduce new UAPI to support IOMMUFD

[PULL 23/45] target/loongarch: Implement vsllwil vextl

This patch includes: - VSLLWIL.{H.B/W.H/D.W}; - VSLLWIL.{HU.BU/WU.HU/DU.WU}; - VEXTL.Q.D, VEXTL.QU.DU. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-24-gaos...@loongson.cn> --- target/loongarch/disas.c| 9 + target/loongarch/

[PULL 19/45] target/loongarch: Implement vsigncov

This patch includes: - VSIGNCOV.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-20-gaos...@loongson.cn> --- target/loongarch/disas.c| 5 ++ target/loongarch/helper.h | 5 ++ target/loongarch/insn_trans

[PULL 18/45] target/loongarch: Implement vexth

This patch includes: - VEXTH.{H.B/W.H/D.W/Q.D}; - VEXTH.{HU.BU/WU.HU/DU.WU/QU.DU}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-19-gaos...@loongson.cn> --- target/loongarch/disas.c| 9 ++ target/loongarch/helper.h

[PULL 45/45] hw/intc: don't use target_ulong for LoongArch ipi

From: Alex Bennée The calling function is already working with hwaddr and uint64_t so lets avoid bringing target_ulong in if we don't need to. Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Song Gao Message-Id: <20230404132711.2563638-1-alex.ben...@linaro.org> Sig

[PULL 37/45] target/loongarch: Implement vbitsel vset

This patch includes: - VBITSEL.V; - VBITSELI.B; - VSET{EQZ/NEZ}.V; - VSETANYEQZ.{B/H/W/D}; - VSETALLNEZ.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-38-gaos...@loongson.cn> --- target/loongarch/disas.c| 20 ++ targ

[PULL 44/45] target/loongarch: CPUCFG support LSX

Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-45-gaos...@loongson.cn> --- target/loongarch/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 55d7f9255e..c0afc21b2f 100644 --- a/target/loong

[PULL 41/45] target/loongarch: Implement vld vst

This patch includes: - VLD[X], VST[X]; - VLDREPL.{B/H/W/D}; - VSTELM.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-42-gaos...@loongson.cn> --- target/loongarch/disas.c| 34 + target/loongarch/insn_trans/trans_lsx.c

[PULL 43/45] target/loongarch: Use {set/get}_gpr replace to cpu_fpr

Introduce set_fpr() and get_fpr() and remove cpu_fpr. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-44-gaos...@loongson.cn> --- .../loongarch/insn_trans/trans_farith.c.inc | 72 +++ target/loongarch/insn_trans/trans_fcmp.c.inc | 12

[PULL 00/45] loongarch-to-apply queue

The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab: Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-2023050

[PULL 15/45] target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}

This patch includes: - VMADD.{B/H/W/D}; - VMSUB.{B/H/W/D}; - VMADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VMADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-16-gaos...@loongson.cn> --- target/loongarch/disas.c

[PULL 27/45] target/loongarch: Implement vssrln vssran

This patch includes: - VSSRLN.{B.H/H.W/W.D}; - VSSRAN.{B.H/H.W/W.D}; - VSSRLN.{BU.H/HU.W/WU.D}; - VSSRAN.{BU.H/HU.W/WU.D}; - VSSRLNI.{B.H/H.W/W.D/D.Q}; - VSSRANI.{B.H/H.W/W.D/D.Q}; - VSSRLNI.{BU.H/HU.W/WU.D/DU.Q}; - VSSRANI.{BU.H/HU.W/WU.D/DU.Q}. Reviewed-by: Richard Henderson Signed-off-by: Song

[PULL 17/45] target/loongarch: Implement vsat

This patch includes: - VSAT.{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-18-gaos...@loongson.cn> --- target/loongarch/disas.c| 9 ++ target/loongarch/helper.h | 9 ++ target/loongarch/insn_tran

[PULL 36/45] target/loongarch: Implement vfcmp

This patch includes: - VFCMP.cond.{S/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-37-gaos...@loongson.cn> --- target/loongarch/disas.c| 94 + target/loongarch/helper.h | 5 ++ target/loo

[PULL 29/45] target/loongarch: Implement vclo vclz

This patch includes: - VCLO.{B/H/W/D}; - VCLZ.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-30-gaos...@loongson.cn> --- target/loongarch/disas.c| 9 ++ target/loongarch/helper.h | 9 ++ targe

[PULL 22/45] target/loongarch: Implement vsll vsrl vsra vrotr

This patch includes: - VSLL[I].{B/H/W/D}; - VSRL[I].{B/H/W/D}; - VSRA[I].{B/H/W/D}; - VROTR[I].{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-23-gaos...@loongson.cn> --- target/loongarch/disas.c| 36 +

[PULL 33/45] target/loongarch: Implement LSX fpu arith instructions

This patch includes: - VF{ADD/SUB/MUL/DIV}.{S/D}; - VF{MADD/MSUB/NMADD/NMSUB}.{S/D}; - VF{MAX/MIN}.{S/D}; - VF{MAXA/MINA}.{S/D}; - VFLOGB.{S/D}; - VFCLASS.{S/D}; - VF{SQRT/RECIP/RSQRT}.{S/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-34-gaos...@lo

[PULL 39/45] target/loongarch: Implement vreplve vpack vpick

This patch includes: - VREPLVE[I].{B/H/W/D}; - VBSLL.V, VBSRL.V; - VPACK{EV/OD}.{B/H/W/D}; - VPICK{EV/OD}.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-40-gaos...@loongson.cn> --- target/loongarch/disas.c| 35 + ta

[PULL 16/45] target/loongarch: Implement vdiv/vmod

This patch includes: - VDIV.{B/H/W/D}[U]; - VMOD.{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-17-gaos...@loongson.cn> --- target/loongarch/disas.c| 17 ++ target/loongarch/helper.h | 17 +++

[PULL 35/45] target/loongarch: Implement vseq vsle vslt

This patch includes: - VSEQ[I].{B/H/W/D}; - VSLE[I].{B/H/W/D}[U]; - VSLT[I].{B/H/W/D/}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-36-gaos...@loongson.cn> --- target/loongarch/disas.c| 43 + target/loongarch/helper.h

[PULL 24/45] target/loongarch: Implement vsrlr vsrar

This patch includes: - VSRLR[I].{B/H/W/D}; - VSRAR[I].{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-25-gaos...@loongson.cn> --- target/loongarch/disas.c| 18 target/loongarch/helper.h | 18

[PULL 01/45] target/loongarch: Add LSX data type VReg

Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-2-gaos...@loongson.cn> --- linux-user/loongarch64/signal.c | 4 +- target/loongarch/cpu.c | 2 +- target/loongarch/cpu.h | 21 - target/loongarch/gdbstub.c | 4 +- target/

[PULL 12/45] target/loongarch: Implement vadda

This patch includes: - VADDA.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-13-gaos...@loongson.cn> --- target/loongarch/disas.c| 5 ++ target/loongarch/helper.h | 5 ++ target/loongarch/insn_trans/tr

[PULL 21/45] target/loongarch: Implement LSX logic instructions

This patch includes: - V{AND/OR/XOR/NOR/ANDN/ORN}.V; - V{AND/OR/XOR/NOR}I.B. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-22-gaos...@loongson.cn> --- target/loongarch/disas.c| 12 + target/loongarch/helper.h

[PULL 25/45] target/loongarch: Implement vsrln vsran

This patch includes: - VSRLN.{B.H/H.W/W.D}; - VSRAN.{B.H/H.W/W.D}; - VSRLNI.{B.H/H.W/W.D/D.Q}; - VSRANI.{B.H/H.W/W.D/D.Q}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-26-gaos...@loongson.cn> --- target/loongarch/disas.c| 16 +++

[PULL 32/45] target/loongarch: Implement vfrstp

This patch includes: - VFRSTP[I].{B/H}. Acked-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-33-gaos...@loongson.cn> --- target/loongarch/disas.c| 5 +++ target/loongarch/helper.h | 5 +++ target/loongarch/insn_trans/tra

[PULL 04/45] target/loongarch: Implement vadd/vsub

This patch includes: - VADD.{B/H/W/D/Q}; - VSUB.{B/H/W/D/Q}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-5-gaos...@loongson.cn> --- target/loongarch/disas.c| 23 +++ target/loongarch/insn_trans/trans_lsx.c.inc | 69 +

[PULL 30/45] target/loongarch: Implement vpcnt

This patch includes: - VPCNT.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-31-gaos...@loongson.cn> --- target/loongarch/disas.c| 5 + target/loongarch/helper.h | 5 + target/loongarch/insn_tr

[PULL 42/45] target/loongarch: Implement vldi

This patch includes: - VLDI. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-43-gaos...@loongson.cn> --- target/loongarch/disas.c| 7 + target/loongarch/insn_trans/trans_lsx.c.inc | 137 target/loongarch/insns

[PULL 34/45] target/loongarch: Implement LSX fpu fcvt instructions

This patch includes: - VFCVT{L/H}.{S.H/D.S}; - VFCVT.{H.S/S.D}; - VFRINT[{RNE/RZ/RP/RM}].{S/D}; - VFTINT[{RNE/RZ/RP/RM}].{W.S/L.D}; - VFTINT[RZ].{WU.S/LU.D}; - VFTINT[{RNE/RZ/RP/RM}].W.D; - VFTINT[{RNE/RZ/RP/RM}]{L/H}.L.S; - VFFINT.{S.W/D.L}[U]; - VFFINT.S.L, VFFINT{L/H}.D.W. Reviewed-by: Richard

[PULL 20/45] target/loongarch: Implement vmskltz/vmskgez/vmsknz

This patch includes: - VMSKLTZ.{B/H/W/D}; - VMSKGEZ.B; - VMSKNZ.B. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-21-gaos...@loongson.cn> --- target/loongarch/disas.c| 7 ++ target/loongarch/helper.h | 7 ++ t

[PULL 14/45] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}

This patch includes: - VMUL.{B/H/W/D}; - VMUH.{B/H/W/D}[U]; - VMULW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VMULW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-15-gaos...@loongson.cn> --- target/loongarch/disas.c

[PULL 38/45] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr

This patch includes: - VINSGR2VR.{B/H/W/D}; - VPICKVE2GR.{B/H/W/D}[U]; - VREPLGR2VR.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-39-gaos...@loongson.cn> --- target/loongarch/disas.c| 33 ++ target/loongarch/insn_t

[PULL 11/45] target/loongarch: Implement vabsd

This patch includes: - VABSD.{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-12-gaos...@loongson.cn> --- target/loongarch/disas.c| 9 ++ target/loongarch/helper.h | 9 ++ target/loongarch/insn_trans

[PULL 31/45] target/loongarch: Implement vbitclr vbitset vbitrev

This patch includes: - VBITCLR[I].{B/H/W/D}; - VBITSET[I].{B/H/W/D}; - VBITREV[I].{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-32-gaos...@loongson.cn> --- target/loongarch/disas.c| 25 ++ target/loongarch/helper.h

[PULL 40/45] target/loongarch: Implement vilvl vilvh vextrins vshuf

This patch includes: - VILV{L/H}.{B/H/W/D}; - VSHUF.{B/H/W/D}; - VSHUF4I.{B/H/W/D}; - VPERMI.W; - VEXTRINS.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-41-gaos...@loongson.cn> --- target/loongarch/disas.c| 25 ta

[PULL 26/45] target/loongarch: Implement vsrlrn vsrarn

This patch includes: - VSRLRN.{B.H/H.W/W.D}; - VSRARN.{B.H/H.W/W.D}; - VSRLRNI.{B.H/H.W/W.D/D.Q}; - VSRARNI.{B.H/H.W/W.D/D.Q}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-27-gaos...@loongson.cn> --- target/loongarch/disas.c| 16

[PULL 13/45] target/loongarch: Implement vmax/vmin

This patch includes: - VMAX[I].{B/H/W/D}[U]; - VMIN[I].{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-14-gaos...@loongson.cn> --- target/loongarch/disas.c| 33 target/loongarch/helper.h | 18 +

[PULL 10/45] target/loongarch: Implement vavg/vavgr

This patch includes: - VAVG.{B/H/W/D}[U]; - VAVGR.{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-11-gaos...@loongson.cn> --- target/loongarch/disas.c| 17 ++ target/loongarch/helper.h | 18 ++ targ

[PULL 08/45] target/loongarch: Implement vhaddw/vhsubw

This patch includes: - VHADDW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}; - VHSUBW.{H.B/W.H/D.W/Q.D/HU.BU/WU.HU/DU.WU/QU.DU}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-9-gaos...@loongson.cn> --- target/loongarch/disas.c| 17 +++

[PULL 03/45] target/loongarch: Add CHECK_SXE maccro for check LSX enable

Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-4-gaos...@loongson.cn> --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++ 3 files ch

[PULL 06/45] target/loongarch: Implement vneg

This patch includes; - VNEG.{B/H/W/D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-7-gaos...@loongson.cn> --- target/loongarch/disas.c| 10 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 20 target

[PULL 09/45] target/loongarch: Implement vaddw/vsubw

This patch includes: - VADDW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VSUBW{EV/OD}.{H.B/W.H/D.W/Q.D}[U]; - VADDW{EV/OD}.{H.BU.B/W.HU.H/D.WU.W/Q.DU.D}. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-10-gaos...@loongson.cn> --- target/loongarch/disas.c

[PULL 28/45] target/loongarch: Implement vssrlrn vssrarn

This patch includes: - VSSRLRN.{B.H/H.W/W.D}; - VSSRARN.{B.H/H.W/W.D}; - VSSRLRN.{BU.H/HU.W/WU.D}; - VSSRARN.{BU.H/HU.W/WU.D}; - VSSRLRNI.{B.H/H.W/W.D/D.Q}; - VSSRARNI.{B.H/H.W/W.D/D.Q}; - VSSRLRNI.{BU.H/HU.W/WU.D/DU.Q}; - VSSRARNI.{BU.H/HU.W/WU.D/DU.Q}. Reviewed-by: Richard Henderson Signed-off-

[PULL 05/45] target/loongarch: Implement vaddi/vsubi

This patch includes: - VADDI.{B/H/W/D}U; - VSUBI.{B/H/W/D}U. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-6-gaos...@loongson.cn> --- target/loongarch/disas.c| 14 target/loongarch/insn_trans/trans_lsx.c.inc | 37

[PULL 07/45] target/loongarch: Implement vsadd/vssub

This patch includes: - VSADD.{B/H/W/D}[U]; - VSSUB.{B/H/W/D}[U]. Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-8-gaos...@loongson.cn> --- target/loongarch/disas.c| 17 + target/loongarch/insn_trans/trans_lsx.c.inc

[PULL 02/45] target/loongarch: meson.build support build LSX

Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-Id: <20230504122810.4094787-3-gaos...@loongson.cn> --- target/loongarch/insn_trans/trans_lsx.c.inc | 5 + target/loongarch/lsx_helper.c | 6 ++ target/loongarch/meson.build| 1 + target/loongarch

Re: [PATCH v3 0/3] target/riscv: implement query-cpu-definitions

On Wed, May 3, 2023 at 7:51 PM Daniel Henrique Barboza wrote: > > Alistair, > > Patch 2 has a typo right in the commit title: > > "target/riscv: add query-cpy-definitions support" > > it should be 'query-cpu-definitions'. Can you amend it in the tree? Or should > I re-send? I have fixed it in my

[PULL 73/89] target/riscv: Check SUM in the correct register

From: Richard Henderson Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual.

[PULL 16/89] target/riscv: expose properties for Zc* extension

From: Weiwei Li Expose zca,zcb,zcf,zcd,zcmp,zcmt properties. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230307081403.61950-9-liwei...@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 14 ++ 1 file chang

[PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx

From: Weiwei Li Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done by check currently. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Message-Id: <20230408135908.25269-1-liwei...@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/

[PULL 69/89] target/riscv: Introduce mmuidx_priv

From: Richard Henderson Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel

[PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled

From: LIU Zhiwei Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type. Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-ID: <20230325145348.1208-1-zhiwei_...@linux.alibaba.com> Reviewed-by: Alistair Francis Reviewed-by: Richard Hende

[PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET

From: Weiwei Li The MPP will be set to the least-privileged supported mode (U if U-mode is implemented, else M). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20230407014743.18779-2-liwei...@iscas.ac.cn> Signed-off-by: Alistair Francis ---

[PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags

From: Richard Henderson Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by:

[PULL 58/89] target/riscv: Extract virt enabled state from tb flags

From: LIU Zhiwei Virt enabled state is not a constant, so we should put it into tb flags. Thus we can use it like a constant condition at translation phase. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143

[PULL 66/89] target/riscv: Handle HLV, HSV via helpers

From: Richard Henderson Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson Reviewed-by: Alistair Fr

[PULL 78/89] target/riscv: Don't modify SUM with is_debug

From: Richard Henderson If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henri

[PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX

From: Richard Henderson Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-10-richard

[PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop

From: Richard Henderson These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-20-richard.hender...@linaro.org> Message-Id: <20230412

[PULL 74/89] target/riscv: Hoist second stage mode change to callers

From: Richard Henderson Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-1

[PULL 57/89] target/riscv: fix H extension TVM trap

From: Yi Chen - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled. - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled. - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA. - Raise RISCV_EXCP_VIRT_INSTRUCTION_FAULT when VU-mode executes SFENCE.V

[PULL 68/89] target/riscv: Introduce mmuidx_sum

From: Richard Henderson In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.11425

[PULL 59/89] target/riscv: Add a general status enum for extensions

From: LIU Zhiwei The pointer masking is the only extension that directly use status. The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei

[PULL 62/89] target/riscv: Add a tb flags field for vstart

From: LIU Zhiwei Once we mistook the vstart directly from the env->vstart. As env->vstart is not a constant, we should record it in the tb flags if we want to use it in translation. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li

Re: [PULL 00/89] riscv-to-apply queue

On Fri, May 5, 2023 at 11:05 AM Alistair Francis wrote: > > On Fri, May 5, 2023 at 11:03 AM Alistair Francis wrote: > > > > The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab: > > > > Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu > > into stagin

[PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg()

From: Daniel Henrique Barboza This function was created to move the sync between cpu->cfg.ext_N bit changes to env->misa_ext* from the validation step to an ealier step, giving us a guarantee that we could use either cpu->cfg.ext_N or riscv_has_ext(env,N) in the validation. We don't have any cpu

[PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT

From: Richard Henderson We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.hender...@linaro.org> Message-Id: <2023041211433

[PULL 86/89] target/riscv: Restore the predicate() NULL check behavior

From: Bin Meng When reading a non-existent CSR QEMU should raise illegal instruction exception, but currently it just exits due to the g_assert() check. This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617. Some comments are also added to indicate that predicate() must be provid

[PULL 83/89] target/riscv: add CPU QOM header

From: Daniel Henrique Barboza QMP CPU commands are usually implemented by a separated file, -qmp-cmds.c, to allow them to be build only for softmmu targets. This file uses a CPU QOM header with basic QOM declarations for the arch. We'll introduce query-cpu-definitions for RISC-V CPUs in the next

[PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize()

From: Daniel Henrique Barboza When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N properties updated. The same can't be said about env->misa_ext*, since the user might enable/disable MISA extensions in the command line, and env->misa_ext* won't caught these changes. The curren

[PULL 70/89] target/riscv: Introduce mmuidx_2stage

From: Richard Henderson Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-15-richard.hender...@linaro.

[PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU

From: Rahul Pathak Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board. CPU specs and general information can be found here: https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/

Re: [PULL 00/89] riscv-to-apply queue

On Fri, May 5, 2023 at 11:03 AM Alistair Francis wrote: > > The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab: > > Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into > staging (2023-05-04 12:08:00 +0100) > > are available in the Git repository a

[PULL 63/89] target/riscv: Separate priv from mmu_idx

From: Fei Wu Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Here an individual priv field is added into TB_FLAGS. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-2-f

[PULL 44/89] target/riscv: remove cpu->cfg.ext_s

From: Daniel Henrique Barboza Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 80/89] target/riscv: Reorg access check in get_physical_address

From: Richard Henderson We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson Reviewed-

[PULL 84/89] target/riscv: add query-cpy-definitions support

From: Daniel Henrique Barboza This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU. This initial support includes only the name of the CPU and its typename. Here's what the c

[PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv

From: Richard Henderson The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1

[PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed

From: Alexandre Ghiti As per the specification, in 64-bit, if any of the pte reserved bits 60-54 is set an exception should be triggered (see 4.4.1, "Addressing and Memory Protection"). In addition, we must check the napot/pbmt bits are not set if those extensions are not active. Reported-by: An

[PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props()

From: Daniel Henrique Barboza The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's

[PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU

From: Daniel Henrique Barboza This new abstract type will be used to differentiate between static and non-static CPUs in query-cpu-definitions. All generic CPUs were changed to be of this type. Named CPUs are kept as TYPE_RISCV_CPU and will still be considered static. This is the output of quer

[PULL 79/89] target/riscv: Merge checks for reserved pte flags

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-24-richard.hender...@linaro.org> Message-Id: <20230412114333.118895-24-richard.hender...@linaro.org> Signed-off-

[PULL 10/89] target/riscv: add support for Zca extension

From: Weiwei Li Modify the check for C extension to Zca (C implies Zca). Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa Message-Id: <20230307081403.61950-3-liwei...@iscas.ac.cn> Signed-off-by: A

[PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index

From: Richard Henderson Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwe

[PULL 48/89] target/riscv: remove cpu->cfg.ext_v

From: Daniel Henrique Barboza Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags

From: LIU Zhiwei Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson Signed-off-by: LIU Z

[PULL 40/89] target/riscv: remove cpu->cfg.ext_f

From: Daniel Henrique Barboza Create a new "f" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are replaced with riscv_has_ext(env, RVF). Remove the old "f" property and 'ext_f' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 37/89] target/riscv: remove cpu->cfg.ext_a

From: Daniel Henrique Barboza Create a new "a" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are replaced with riscv_has_ext(env, RVA). Remove the old "a" property and 'ext_a' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 76/89] target/riscv: Move leaf pte processing out of level loop

From: Richard Henderson Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-21-richard.hender...

[PULL 81/89] target/riscv: Reorg sum check in get_physical_address

From: Richard Henderson Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signe

[PULL 31/89] target/riscv: Fix lines with over 80 characters

From: Weiwei Li Fix lines with over 80 characters for both code and comments. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-Id: <20230405085813.40643-5-liwei...@iscas.ac.cn> Signed-off-by

[PULL 41/89] target/riscv: remove cpu->cfg.ext_i

From: Daniel Henrique Barboza Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 38/89] target/riscv: remove cpu->cfg.ext_c

From: Daniel Henrique Barboza Create a new "c" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are replaced with riscv_has_ext(env, RVC). Remove the old "c" property and 'ext_c' from RISCVCPUConfig. Signed-off-by: Daniel Henrique

[PULL 87/89] target/riscv: Fix Guest Physical Address Translation

From: Irina Ryapolova Before changing the flow check for sv39/48/57. According to specification (for Supervisor mode): Sv39 implementations support a 39-bit virtual address space, divided into 4 KiB pages. Instruction fetch addresses and load and store effective addresses, which are 64 bits, mus

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