The following changes since commit f6b761bdbd8ba63cee7428d52fb6b46e4224ddab:
Merge tag 'qga-pull-2023-05-04' of https://github.com/kostyanf14/qemu into staging (2023-05-04 12:08:00 +0100) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230505 for you to fetch changes up to 9dd207d409cc2eb08fe52965b9d1fd4a12a82bd5: hw/intc: don't use target_ulong for LoongArch ipi (2023-05-05 10:00:47 +0800) ---------------------------------------------------------------- Add LoongArch LSX instructions. ---------------------------------------------------------------- Alex Bennée (1): hw/intc: don't use target_ulong for LoongArch ipi Song Gao (44): target/loongarch: Add LSX data type VReg target/loongarch: meson.build support build LSX target/loongarch: Add CHECK_SXE maccro for check LSX enable target/loongarch: Implement vadd/vsub target/loongarch: Implement vaddi/vsubi target/loongarch: Implement vneg target/loongarch: Implement vsadd/vssub target/loongarch: Implement vhaddw/vhsubw target/loongarch: Implement vaddw/vsubw target/loongarch: Implement vavg/vavgr target/loongarch: Implement vabsd target/loongarch: Implement vadda target/loongarch: Implement vmax/vmin target/loongarch: Implement vmul/vmuh/vmulw{ev/od} target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od} target/loongarch: Implement vdiv/vmod target/loongarch: Implement vsat target/loongarch: Implement vexth target/loongarch: Implement vsigncov target/loongarch: Implement vmskltz/vmskgez/vmsknz target/loongarch: Implement LSX logic instructions target/loongarch: Implement vsll vsrl vsra vrotr target/loongarch: Implement vsllwil vextl target/loongarch: Implement vsrlr vsrar target/loongarch: Implement vsrln vsran target/loongarch: Implement vsrlrn vsrarn target/loongarch: Implement vssrln vssran target/loongarch: Implement vssrlrn vssrarn target/loongarch: Implement vclo vclz target/loongarch: Implement vpcnt target/loongarch: Implement vbitclr vbitset vbitrev target/loongarch: Implement vfrstp target/loongarch: Implement LSX fpu arith instructions target/loongarch: Implement LSX fpu fcvt instructions target/loongarch: Implement vseq vsle vslt target/loongarch: Implement vfcmp target/loongarch: Implement vbitsel vset target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr target/loongarch: Implement vreplve vpack vpick target/loongarch: Implement vilvl vilvh vextrins vshuf target/loongarch: Implement vld vst target/loongarch: Implement vldi target/loongarch: Use {set/get}_gpr replace to cpu_fpr target/loongarch: CPUCFG support LSX hw/intc/loongarch_ipi.c | 2 +- linux-user/loongarch64/signal.c | 4 +- target/loongarch/cpu.c | 5 +- target/loongarch/cpu.h | 27 +- target/loongarch/disas.c | 911 +++++ target/loongarch/fpu_helper.c | 2 +- target/loongarch/gdbstub.c | 4 +- target/loongarch/helper.h | 566 +++ target/loongarch/insn_trans/trans_farith.c.inc | 72 +- target/loongarch/insn_trans/trans_fcmp.c.inc | 12 +- target/loongarch/insn_trans/trans_fmemory.c.inc | 37 +- target/loongarch/insn_trans/trans_fmov.c.inc | 31 +- target/loongarch/insn_trans/trans_lsx.c.inc | 4400 +++++++++++++++++++++++ target/loongarch/insns.decode | 811 +++++ target/loongarch/internals.h | 23 + target/loongarch/lsx_helper.c | 3004 ++++++++++++++++ target/loongarch/machine.c | 79 +- target/loongarch/meson.build | 1 + target/loongarch/translate.c | 55 +- target/loongarch/translate.h | 1 + 20 files changed, 9989 insertions(+), 58 deletions(-) create mode 100644 target/loongarch/insn_trans/trans_lsx.c.inc create mode 100644 target/loongarch/lsx_helper.c
