On 4/11/23 14:34, Philippe Mathieu-Daudé wrote:
+ if (tcg_out_movi_one(s, ret, arg)) {
return;
}
+
if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
Shouldn't this block be removed in this patch?
On 4/11/23 13:37, gaosong wrote:
static bool trans_vseteqz_v(DisasContext *ctx, arg_cv *a)
{
TCGv_i64 t1, t2, al, ah, zero;
al = tcg_temp_new_i64();
ah = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
zero = tcg_constant_i64(0);
get_vre
On Tue, Apr 11, 2023 at 10:44 PM Peter Xu wrote:
>
> On Tue, Apr 11, 2023 at 03:30:08PM +0100, Peter Maydell wrote:
> > On Tue, 11 Apr 2023 at 15:14, Peter Xu wrote:
> > >
> > > On Mon, Apr 10, 2023 at 11:32:08AM +0800, Jason Wang wrote:
> > > > @@ -222,9 +222,9 @@ static guint vtd_iotlb_hash(gco
On 4/11/23 04:29, Taylor Simpson wrote:
These variables could be moved to DisasContext and allocated on demand.
Even recently this was tedious, because of TCG temporary lifetime issues,
but no longer.
I'll work on this. The obvious advantage is to allow the TCG optimizer more
opportunity to f
On Wed, Apr 12, 2023 at 1:56 PM Jason Wang wrote:
>
> On Tue, Apr 11, 2023 at 8:34 PM Eugenio Perez Martin
> wrote:
> >
> > On Wed, Apr 5, 2023 at 1:37 PM Eugenio Perez Martin
> > wrote:
> > >
> > > Hi!
> > >
> > > As mentioned in the last upstream virtio-networking meeting, one of
> > > the fa
On Tue, Apr 11, 2023 at 8:34 PM Eugenio Perez Martin
wrote:
>
> On Wed, Apr 5, 2023 at 1:37 PM Eugenio Perez Martin
> wrote:
> >
> > Hi!
> >
> > As mentioned in the last upstream virtio-networking meeting, one of
> > the factors that adds more downtime to migration is the handling of
> > the gue
On 11/04/2023 23.04, Vikram Garhwal wrote:
Xen is supported for aarch64 via xenpvh machine. disable-tcg option fails the
build for aarch64 target.
Link for xen on arm patch series:
https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03979.html
Signed-off-by: Vikram Garhwal
---
.gitlab-c
On Thu, Apr 6, 2023 at 8:17 PM Yi Chen wrote:
>
> - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
> - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
> - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
> - Raise RISCV_EXCP_VIRT_INSTRUCTI
Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
version is higher than the priv version of C/F/D. So if we use check
for them instead of check for C/F/D totally, it will trigger new
problem when we try to disable the extensions based on the configured
priv version.
Signed-off
On 2023/4/12 10:12, Alistair Francis wrote:
On Fri, Apr 7, 2023 at 6:23 AM Daniel Henrique Barboza
wrote:
Hi,
This patch is going to break the sifive_u boot if I rebase
"[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
on top of it, as it is the case today with the current ri
On Tue, 2023-04-11 at 16:39 +0100, Peter Maydell wrote:
Dear Peter
Thank you for taking the time to reply to my email. I appreciate your
the valuable information you have provided.
> On Mon, 3 Apr 2023 at 13:51, zenghao wrote:
> >
> > opened file processor not closed,May cause file processor lea
On Thu, Apr 6, 2023 at 8:17 PM Yi Chen wrote:
>
> - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
> - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
> - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
> - Raise RISCV_EXCP_VIRT_INSTRUCTI
On Mon, Apr 10, 2023 at 1:36 PM Weiwei Li wrote:
>
> Move multi-letter extensions that may implicitly enabled from misa.EXT
> alone to prepare for following separation of implicitly enabled and
> explicitly enabled extensions.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed
Add ext_zfbfmin/zvfbfmin/zvfbfwma properties.
Add require check for BF16 extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 13 +
target/riscv/cpu.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cp
Add trans_* and helper function for Zvfbfmin instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/helper.h | 3 +
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 64 ++
tar
Specification for BF16 extensions can be found in:
https://github.com/riscv/riscv-bfloat16
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream
Weiwei Li (5):
target/riscv: Add properties for BF16 extensions
target/riscv: Add support for Zfbfmin extension
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c19bbb41fb..0265fae46f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -83,6 +83,7 @@ static const str
Add trans_* and helper function for Zfbfmin instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/fpu_helper.c | 12 +
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_tr
Add trans_* and helper function for Zvfbfwma instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 4 ++
target/riscv/insn_trans/trans_rvbf16.c.inc | 58 ++
ta
I have a CKD file, created with the Hercules dasdinit program.
It's a (hercules) 3350 uncompressed file.
I've put a small "hello world" IPL program on it, and it works fine with
Hercules
When I try to run it with qemu-system-s390x I get :
LOADPARM=[]
Using virtio-blk.
Using guessed DASD
On Fri, Apr 7, 2023 at 6:23 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This patch is going to break the sifive_u boot if I rebase
>
> "[PATCH v6 0/9] target/riscv: rework CPU extensions validation"
>
> on top of it, as it is the case today with the current riscv-to-apply.next.
>
> The reason is
On Tue, Apr 11, 2023 at 7:03 PM Bin Meng wrote:
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
> Some comments are also added
On 2023/4/11 17:02, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that pre
On Wed, Mar 29, 2023, 9:32 AM Daniel P. Berrangé
wrote:
> On Wed, Mar 29, 2023 at 03:27:53PM +0200, Paolo Bonzini wrote:
> > On 3/29/23 14:53, Daniel P. Berrangé wrote:
> > > I would love to see a day where configure isn't involved in the
> > > build process. Obviously we can't put this new logic
On Tue, Apr 11, 2023 at 7:03 PM Bin Meng wrote:
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
> Some comments are also added
Hi Peter,
On 3/27/23 9:26 PM, Igor Mammedov wrote:
On Fri, 17 Mar 2023 14:25:39 +0800
Gavin Shan wrote:
For arm64 and riscv architecture, the driver (/base/arch_topology.c) is
used to populate the CPU topology in the Linux guest. It's required that
the CPUs in one cluster can't span mutiple N
On 4/11/2023 5:02 PM, Bin Meng wrote:
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
I verified that 'csrr t3, 0x4' in user space didn't cause qemu exit but
raised illegal instruction after applying th
On 2023/4/11 17:02, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that pre
On 4/10/23 21:15, liweiwei wrote:
On 2023/4/10 21:48, Daniel Henrique Barboza wrote:
Hi,
On 4/10/23 00:35, Weiwei Li wrote:
The patch tries to separate the multi-letter extensions that may
implicitly-enabled by misa.EXT from the explicitly-enabled cases, so that the
misa.EXT can truely d
On 4/11/23 06:02, Bin Meng wrote:
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that pred
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
xen_do_ioreq_
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move han
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Signed-off-by
Hi,
Rebased and resending the series with latest QEMU as it's been quite sometime.
There are no code changes.
Also, this series has dependency on following gitlab-ci
patch: https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01641.html.
This series add xenpvh machine for aarch64. Motivation
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 52c3995c9d..eb5bb305a
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated XenIOS
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common ioreq functions in one
Add a new machine xenpvh which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest do
Replace g_malloc with g_new and perror with error_report.
Signed-off-by: Vikram Garhwal
Reviewed-by: Stefano Stabellini
Reviewed-by: Paul Durrant
---
hw/xen/xen-hvm-common.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hv
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 29f8644d6d..52c3995c9d 100644
--- a/meson.build
+++
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Paul Durrant
---
hw/
Xen is supported for aarch64 via xenpvh machine. disable-tcg option fails the
build for aarch64 target.
Link for xen on arm patch series:
https://mail.gnu.org/archive/html/qemu-devel/2023-02/msg03979.html
Signed-off-by: Vikram Garhwal
---
.gitlab-ci.d/crossbuilds.yml | 4 ++--
1 file changed,
On Tue, Apr 4, 2023 at 7:59 AM Markus Armbruster wrote:
>
> Commit 81cbfd50886 (block: remove dirty bitmaps 'status' field)
> removed deprecated BlockDirtyInfo member @status. It neglected to
> remove references to its enumeration values from the documentation of
> its replacements. Do that now.
On Apr 11 19:16, Peter Maydell wrote:
> On Mon, 6 Mar 2023 at 14:34, Klaus Jensen wrote:
> >
> > From: Jesper Devantier
> >
> > Add emulation of TP4146 ("Flexible Data Placement").
> >
> > Reviewed-by: Keith Busch
> > Signed-off-by: Jesper Devantier
> > Signed-off-by: Klaus Jensen
>
> Hi; Cov
From: Klaus Jensen
Fix two issues reported by Coverity (CID 1507979 and 1508281).
Klaus Jensen (2):
hw/nvme: fix memory leak in fdp ruhid parsing
hw/nvme: fix memory leak in nvme_dsm
hw/nvme/ctrl.c | 3 +++
hw/nvme/ns.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
--
2.39.2
From: Klaus Jensen
Coverity reports a memory leak of memory when parsing ruhids at
namespace initialization. Since this is just working memory, not needed
beyond the scope of the functions, fix this by adding a g_autofree
annotation.
Reported-by: Coverity (CID 1507979)
Fixes: 73064edfb864 ("hw/n
From: Klaus Jensen
The iocb (and the allocated memory to hold LBA ranges) leaks if reading
the LBA ranges fails.
Fix this by adding a free and an unref of the iocb.
Reported-by: Coverity (CID 1508281)
Fixes: d7d1474fd85d ("hw/nvme: reimplement dsm to allow cancellation")
Signed-off-by: Klaus Je
On 11.04.23 20:34, Hanna Czenczek wrote:
When processing vectored guest requests that are not aligned to the
storage request alignment, we pad them by adding head and/or tail
buffers for a read-modify-write cycle.
The guest can submit I/O vectors up to IOV_MAX (1024) in length, but
with this pad
Consider what happens when performing a migration between two host
machines connected to an NFS server serving multiple block devices to
the guest, when the NFS server becomes unavailable. The migration
attempts to inactivate all block devices on the source (a necessary
step before the destination
This command is used by tooling like libvirt to retrieve a list of
supported CPUs. Each entry returns a CpuDefinitionInfo object that
contains more information about each CPU.
This initial support includes only the name of the CPU and its typename.
Here's what the command produces for the riscv64
Hi,
In this v3 I removed patches 3 and 4 of v2.
Patch 3 now implements a new type that the generic CPUs (any, rv32,
rv64, x-rv128) were converted to. This type will be used by
query-cpu-definitions to determine if a given cpu is static or not based
on its type. This approach was suggested by Rich
QMP CPU commands are usually implemented by a separated file,
-qmp-cmds.c, to allow them to be build only for softmmu targets.
This file uses a CPU QOM header with basic QOM declarations for the
arch.
We'll introduce query-cpu-definitions for RISC-V CPUs in the next patch,
but first we need a cpu-
This new abstract type will be used to differentiate between static and
non-static CPUs in query-cpu-definitions.
All generic CPUs were changed to be of this type. Named CPUs are kept as
TYPE_RISCV_CPU and will still be considered static.
This is the output of query-cpu-definitions after this cha
In some cases of target independent code, it would be useful to have access
to the functions that swap endianess in case it differs between guest and
host. Thus re-implement the tswapXX() functions in a new header that can be
included separately. The check whether the swapping is needed continues t
The code in this file is not performance critical, so we can use
the target independent endianess functions to only compile this
file once for all targets.
Signed-off-by: Thomas Huth
---
softmmu/qtest.c | 12 ++--
softmmu/meson.build | 2 +-
2 files changed, 7 insertions(+), 7 delet
For being able to build universal binaries one day, we need certain
files to be independent from the emulated target. qtest.c is one of
these files. Rework the target specific code in there so we can
finally move it from "specific_ss" to "softmmu_ss".
Thomas Huth (3):
softmmu/qtest: Move the tar
Ideally, qtest.c should be independent from target specific code, so
we only have to compile it once for all targets. Thus start improving
the situation by moving the pseries related code to hw/ppc/spapr_rtas.c
instead and allow target code to register a callback handler for such
target specific co
On 11.04.23 16:39, Steven Sistare wrote:
On 4/11/2023 3:57 AM, David Hildenbrand wrote:
On 10.04.23 17:46, Steve Sistare wrote:
Guest RAM created with memory-backend-memfd is aligned to a
QEMU_VMALLOC_ALIGN=2M boundary, and memory-backend-memfd does not support
the "align" parameter to change t
On Mon, 6 Mar 2023 at 14:34, Klaus Jensen wrote:
>
> From: Jesper Devantier
>
> Add emulation of TP4146 ("Flexible Data Placement").
>
> Reviewed-by: Keith Busch
> Signed-off-by: Jesper Devantier
> Signed-off-by: Klaus Jensen
Hi; Coverity points out what looks like a memory leak
in this funct
> On Apr 11, 2023, at 8:24 AM, Peter Maydell wrote:
>
> On Mon, 10 Apr 2023 at 15:38, Bartell, Paul wrote:
>>
>> You can reproduce the problem by running gdb against an ARMv8M target
>> running secure mode code (the default).
>>
>> Running qemu with the following arguments : qemu-system-ar
On Tue, 7 Mar 2023 at 18:27, David Woodhouse wrote:
>
> From: David Woodhouse
>
> Now that we have an internal implementation of XenStore, we can populate
> the xenstore_backend_ops to allow PV backends to talk to it.
>
> Watches can't be processed with immediate callbacks because that would
> ca
On Tue, Mar 28, 2023 at 7:47 AM wrote:
>
> From: qianfan Zhao
>
> R40 has eight UARTs, support both 16450 and 16550 compatible modes.
>
> Signed-off-by: qianfan Zhao
> ---
> hw/arm/allwinner-r40.c | 31 ---
> include/hw/arm/allwinner-r40.h | 8
> 2
On Tue, Mar 28, 2023 at 7:47 AM wrote:
>
> From: qianfan Zhao
>
> TWI(i2c) is designed to be used as an interface between CPU host and the
> serial 2-Wire bus. It can support all standard 2-Wire transfer, can be
> operated in standard mode(100kbit/s) or fast-mode, supporting data rate
> up to 400
Hey Babis,
On Mon, 2023-04-03 at 12:52 +0200, Babis Chalios wrote:
> This patchset implements the entropy leak reporting feature proposal [1]
> for virtio-rng devices.
>
> Entropy leaking (as defined in the specification proposal) typically
> happens when we take a snapshot of a VM or while we re
On Tue, 7 Mar 2023 at 18:27, David Woodhouse wrote:
>
> From: David Woodhouse
>
> Now that we have an internal implementation of XenStore, we can populate
> the xenstore_backend_ops to allow PV backends to talk to it.
>
> Watches can't be processed with immediate callbacks because that would
> ca
bdrv_pad_request() was the main user of qemu_iovec_init_extended().
HEAD^ has removed that use, so we can remove qemu_iovec_init_extended()
now.
The only remaining user is qemu_iovec_init_slice(), which can easily
inline the small part it really needs.
Note that qemu_iovec_init_extended() offered
When processing vectored guest requests that are not aligned to the
storage request alignment, we pad them by adding head and/or tail
buffers for a read-modify-write cycle.
The guest can submit I/O vectors up to IOV_MAX (1024) in length, but
with this padding, the vector can exceed that limit. As
Test that even vectored IO requests with 1024 vector elements that are
not aligned to the device's request alignment will succeed.
Reviewed-by: Eric Blake
Reviewed-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Hanna Czenczek
---
tests/qemu-iotests/tests/iov-padding | 85 +
We want to inline qemu_iovec_init_extended() in block/io.c for padding
requests, and having access to qiov_slice() is useful for this. As a
public function, it is renamed to qemu_iovec_slice().
(We will need to count the number of I/O vector elements of a slice
there, and then later process this
RFC:
https://lists.nongnu.org/archive/html/qemu-block/2023-03/msg00446.html
v1:
https://lists.nongnu.org/archive/html/qemu-devel/2023-03/msg05049.html
As explained in the RFC’s cover letter, the problem this series
addresses is that we pad requests from the guest that are unaligned to
the underly
The code for these two devices seems to be independent from any
target specific macros. "riscv_htif.c" is used for both, riscv32 and
riscv64, so by moving this to the common code source set, we can
avoid to compile it twice every time.
"goldfish_tty.c" is only used for one target at the moment, but
11.04.2023 15:09, Peter Maydell wrote:
..
Frankly I would prefer to just say "we don't support x32".
It's a weird non-standard configuration that as far as I'm
aware is very little used. Its stats in the debian
popularity-contest graphs peaked at 18 users in 2017, and
have mostly been fluctuating
It's enabled on all platforms (even in the fork), so we can remove it
from here.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_elf.h| 1 -
bsd-user/elfcore.c| 3 ---
bsd-user/elfload.c| 5 -
bsd-user/i386/target_ar
When a system call returns ENOSYS, send a SIGSYS to the process (to
generate a core dump).
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/arm/target_arch_cpu.h | 8
1 file changed, 8 insertions(+)
diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/targe
SIGSYS creates a core by default if uncaught. Follow that here. Sort
with the same order as is in the kernel.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/signal.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/bsd-user/signal.c b/bsd
From: Stacey Son
Implement do_sysctl_kern_proc_filedesc. This pulls kern.proc.filedesc
out of the host kernel and converts it to the guest's format.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/os-sys.c | 193 +++
From: Stacey Son
Converts host's rusage to the guest's rusage.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/bsd-proc.c | 48
bsd-user/meson.build | 1 +
bsd-user/qemu-bsd.h | 30 ++
On BSD, all architectures have the same mmap flags. Since we don't
translate the flags, we don't need these defines here. We can't
cross-run different BSD binaries.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/syscall_defs.h | 36
1
Automatically generate syscall_nr.h from /usr/include/sys/syscall.h
since we can only run on a system that matches... This should reduce the
churn in the future.
Signed-off-by: Warner Losh
---
bsd-user/freebsd/os-syscall.h | 2 +-
bsd-user/meson.build | 4
bsd-user/syscallhdr.sh
The only diffs between bsd-user fork and qemu upstream is style. Make
mmap.c pass checkpatch.pl.
Signed-off-by: Warner Losh
Acked-by: Richard Henderson
---
bsd-user/mmap.c | 91 -
1 file changed, 60 insertions(+), 31 deletions(-)
diff --git a/bsd
It only defines the default system call scheme to use. However, that
feature was removed in a941a16f6f52.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/host-os.h | 25 -
bsd-user/main.c| 1 -
bsd-user/netbsd/host-os.h | 25 -
Nothing calls these routines now. In the bsd-user fork, though, they've
moved to openbsd/os-syscall.c, but those aren't ready for upstreaming.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 25 -
2 files ch
From: Stacey Son
Bring in the code that was originally copied from linxu-user/elfload.c
and moved to elfcore.c. This code then removed the Linux specific bits,
replacing them with FreeBSD specific bits. The commit history for this
is not at all what we'd like (it was done in one go by sson in
227
Move the include of the system calls to os-syscall.h. Include that from
syscall_defs.h. Use target_time_t and target_suseconds_t instead of the
variant that has _freebsd_ in the name. Define these for OpenBSD and
NetBSD based on comments in the file.
Signed-off-by: Warner Losh
Reviewed-by: Richar
From: Stacey Son
Use the recently committed conversion routines to implement all the
kern.proc flavors, except for the full path (the prereqs of which aren't
yet in qemu-project's master branch).
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user
It's generated now, so just remove it.
---
bsd-user/freebsd/syscall_nr.h | 515 --
1 file changed, 515 deletions(-)
delete mode 100644 bsd-user/freebsd/syscall_nr.h
diff --git a/bsd-user/freebsd/syscall_nr.h b/bsd-user/freebsd/syscall_nr.h
deleted file mode 100644
From: Stacey Son
Implement do_sysctl_kern_getprocs to retrieve proc info from the kernel.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/os-sys.c | 165 +-
bsd-user/qemu.h | 3 +
2 files
From: Stacey Son
Implement do_sysctl_kern_proc_vmmap. This pulls kern.proc.vmmap out of
the host kernel and converts it to the guest's format.
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/os-sys.c | 115 +
Nothing calls these routines now. In the bsd-user fork, though, they've
moved to netbsd/os-syscall.c, but those aren't ready for upstreaming.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/qemu.h | 5 -
bsd-user/strace.c | 17 -
2 files changed, 22
Make these functions public. Due to coming restructuring, we'll need to
call these from *bsd/os-syscall.c. Add declarations to qemu.h.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/qemu.h | 20
bsd-user/strace.c | 29 +
Move the system call table, and FreeBSD helper routines out of strace.c.
We do not support multiple BSD-types in one binary, so simplify things
by moving it.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/freebsd/os-syscall.c | 19 +++
bsd-user/qemu.h
This series is a number of misc cleanups.
First, this replaces my plans to remove netbsd and openbsd code entirely. I've
been in contact with the NetBSD folks that would like to make things work. The
plan is that I'll not remove it in qemu-project, and restore them in bsd-user
fork. These changes
MAP_GUARD, MAP_EXCL, and MAP_NOCORE are FreeBSD only. Define them to be
0 if they aren't defined, and rely on the compiler to optimize away
sections not relevant. Added only to the top of mmap.c since that's the
only place we need this.
Signed-off-by: Warner Losh
Reviewed-by: Richard Henderson
-
On Mon, Apr 10, 2023 at 7:37 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 4/10/23 11:20, Warner Losh wrote:
> > Update the system call list. We have one hokey thing in here for swapoff
> > that depends on the version number (so this is not completely generated
> > at the moment
On Tue, Apr 11, 2023 at 04:11:58AM +, Eiichi Tsukata wrote:
> Use linux specific PR_SET_VMA_ANON_NAME (introduced in v5.17) to set ram
> block name in the kernel. This makes each ram block distinguishable and
> can help debugging and inspection. The names of ram blocks are shown in
> /proc/pid/
On Tue, Apr 11, 2023 at 6:19 PM Amit Shah wrote:
>
> Hey Babis,
>
> On Mon, 2023-04-03 at 12:52 +0200, Babis Chalios wrote:
> > This patchset implements the entropy leak reporting feature proposal [1]
> > for virtio-rng devices.
> >
> > Entropy leaking (as defined in the specification proposal) ty
Given that this has been a holiday weekend for many people, I'm
going to postpone tagging rc4 until Wednesday evening UK time.
Could anybody who has any further release-critical bugfixes they want
to get into this release make sure they are in pull requests on
this list by about 1500 UTC tomorrow,
On Tue, 28 Mar 2023 11:59:26 -0400
Eric DeVolder wrote:
> Currently i386 QEMU generates MADT revision 3, and reports
> MADT revision 1. ACPI 6.3 introduces MADT revision 5.
>
> For MADT revision 4, that introduces ARM GIC structures, which do
> not apply to i386.
>
> For MADT revision 5, the Lo
On Mon, 7 Nov 2022 at 22:49, Michael S. Tsirkin wrote:
>
> From: Huai-Cheng Kuo
>
> The Data Object Exchange implementation of CXL Coherent Device Attribute
> Table (CDAT). This implementation is referring to "Coherent Device
> Attribute Table Specification, Rev. 1.03, July. 2022" and "Compute
>
On Fri, Apr 07, 2023 at 12:36:24PM +0200, Claudio Fontana wrote:
> On 4/6/23 18:46, Fabiano Rosas wrote:
> > Peter Xu writes:
> >
> >> On Tue, Apr 04, 2023 at 05:10:52PM +0200, Claudio Fontana wrote:
> >>> On 4/4/23 16:53, Peter Xu wrote:
> On Tue, Apr 04, 2023 at 10:00:16AM +0200, Claudio F
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