Specification for BF16 extensions can be found in: https://github.com/riscv/riscv-bfloat16
The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-bf16-upstream Weiwei Li (5): target/riscv: Add properties for BF16 extensions target/riscv: Add support for Zfbfmin extension target/riscv: Add support for Zvfbfmin extension target/riscv: Add support for Zvfbfwma extension target/riscv: Expose properties for BF16 extensions target/riscv/cpu.c | 20 +++ target/riscv/cpu.h | 3 + target/riscv/fpu_helper.c | 12 ++ target/riscv/helper.h | 10 ++ target/riscv/insn32.decode | 12 ++ target/riscv/insn_trans/trans_rvbf16.c.inc | 175 +++++++++++++++++++++ target/riscv/insn_trans/trans_rvzfh.c.inc | 13 +- target/riscv/translate.c | 1 + target/riscv/vector_helper.c | 17 ++ 9 files changed, 257 insertions(+), 6 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvbf16.c.inc -- 2.25.1
