I'm sorry for sending ill-formed thread twice.
This problem was because the SMTP server overwrites Message-ID,
and git-sendemail does not reflect it to In-Reply-To: and Reply-To: in the
header.
I will test well before sending the next patch.
The original cover letter was
https://lore.kernel.org/q
This patch series adds qemu_strerror() function, which is thread-safe
version of the libc strerror(). The first patch introduces the
qemu_strerror() function, and the second patch replaces strerror()
function in linux-user/* with qemu_strerror() function.
Because it involves thread safety, qemu_st
strerror() is not guaranteed to be thread-safe as described in
(https://gitlab.com/qemu-project/qemu/-/issues/416).
This commit changes files under /linux-user that call strerror() to call
the safer qemu_strerror().
Signed-off-by: Yohei Kojima
---
linux-user/elfload.c | 4 ++--
linux-user/main.
Add qemu_strerror() which follows the POSIX specification for
strerror(). While strerror() is not guaranteed to be thread-safe, this
function is thread-safe.
This function is added to solve the following issue:
https://gitlab.com/qemu-project/qemu/-/issues/416
Signed-off-by: Yohei Kojima
---
in
From: Ivan Klokov
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov
Reviewed-by: Philipp Tomsich
Acked-by: Alistair Francis
Messag
From: Mikhail Tyutin
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
instructions
Signed-off-by: Mikhail Tyutin
Reviewed-by: Alistair Francis
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc38...@yadro.com>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 19 ++--
From: Alistair Francis
The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
Merge tag 'win-socket-pull-request' of
https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17
+)
are available in the Git repository at:
https://github.com/alistair
On Tue, Mar 14, 2023 at 12:01:09AM -0400, Chuck Zmudzinski wrote:
> Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
> uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
> xenfv machine when the guest is configured for igd-passthru.
>
> A desired extension
Hi Jonathan,
On 3/3/23 16:09, Jonathan Cameron wrote:
Note there are several series ahead of this one and in particular
the RAS error injection series needs some QAPI review.
The QAPI stuff in this patch is similar but in essence very similar
to what we have in that series.
Whilst I'm an always
On 3/3/23 16:09, Jonathan Cameron wrote:
Very simple implementation to allow testing of corresponding
kernel code. Note that for now we track each 64 byte section
independently. Whilst a valid implementation choice, it may
make sense to fuse entries so as to prove out more complex
corners of the
On 3/13/23 7:40 PM, Philippe Mathieu-Daudé wrote:
On 25/2/23 07:35, Gavin Shan wrote:
For some architectures like ARM64, multiple CPUs in one cluster can be
associated with different NUMA nodes, which is irregular configuration
because we shouldn't have this in baremetal environment. The irregul
On 3/3/23 16:09, Jonathan Cameron wrote:
Inject poison using qmp command cxl-inject-poison to add an entry to the
poison list.
For now, the poison is not returned CXL.mem reads,
What do you mean?
but only via the
mailbox command Get Poison List.
See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison l
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the futur
On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich wrote:
>
> After the original Zicond support was stuck/fell through the cracks on
> the mailing list at v3 (and a different implementation was merged in
> the meanwhile), we need to refactor Zicond to prepare it to be reused
> by XVentanaCondOps.
>
>
On 3/3/23 16:09, Jonathan Cameron wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32 bit host native value.
The use of b, w, l, q as the size spe
On 3/3/23 16:09, Jonathan Cameron wrote:
Given the increasing usage of this mailbox return code type, now
is a good time to switch to QEMU style naming.
Reviewed-by: Ira Weiny
Reviewed-by: Fan Ni
Signed-off-by: Jonathan Cameron
---
v8: Picked up tag from Fan Ni
---
hw/cxl/cxl-mailbox-utils
On 9/3/23 08:13, Weiwei Li wrote:
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Dau
On 9/3/23 08:13, Weiwei Li wrote:
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
> directly.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/csr.c | 12
> 1 file chang
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use CPURISCVState as argument directly in riscv_cpu_update_mip and
> riscv_timer_write_timecmp, since type converts from CPURISCVState to
> RISCVCPU in many caller of them and then back to CPURISCVState in them.
>
> Signed-off-by: Weiwei Li
> Si
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use env_archcpu() to get RISCVCPU pointer from env directly.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/pmu.c | 8
> 1 file changed, 4 insertions(+), 4 d
On Thu, Mar 9, 2023 at 5:14 PM Weiwei Li wrote:
>
> Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu_helper.c | 9 -
> target/riscv/csr.c| 40
On Sat, Mar 11, 2023 at 5:00 AM Mikhail Tyutin wrote:
>
> Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg
> instructions
>
> Signed-off-by: Mikhail Tyutin
> Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> disas/riscv.c | 19 +++
On Tue, Mar 14, 2023 at 6:28 AM ~abordado wrote:
>
> From: Afonso Bordado
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly
This patch series consists of two patches. The first provides accessor
functions in pci.h to avoid direct access of slot_reserved_mask
according to the comment at the top of include/hw/pci/pci_bus.h. No
functional change is intended with this patch.
The second patch allows a pci bus to be configur
This patch provides accessor functions as replacements for direct
access to slot_reserved_mask according to the comment at the top
of include/hw/pci/pci_bus.h which advises that data structures for
PCIBus should not be directly accessed but instead be accessed using
accessor functions in pci.h.
Th
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel IGD for the
xenfv machine when the guest is configured for igd-passthru.
A desired extension to that commit is to allow use of the reserved slot
if the administrator ma
On 3/14/23 11:23, Dmitry Fomichev wrote:
>> @@ -3339,10 +3473,27 @@ static int coroutine_fn
>> raw_co_zone_mgmt(BlockDriverState *bs, BlockZoneOp op,
>> len >> BDRV_SECTOR_BITS);
>> ret = raw_thread_pool_submit(bs, handle_aiocb_zone_mgmt, &acb);
>> if (ret != 0) {
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> A zone append command is a write operation that specifies the first
> logical block of a zone as the write position. When writing to a zoned
> block device using zone append, the byte offset of writes is pointing
> to the write pointer of that zone
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
Looks good,
Reviewed-by: Dmitry Fomichev
> block/file-posix.c | 3 +++
> block/trace-events | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/block/file-posix.c b/block/file-posix.c
> index 2ba9174778..5187f81
On Fri, 2023-03-10 at 18:31 +0800, Sam Li wrote:
> Since Linux doesn't have a user API to issue zone append operations to
> zoned devices from user space, the file-posix driver is modified to add
> zone append emulation using regular writes. To do this, the file-posix
> driver tracks the wp locatio
Signed-off-by: Klaus Ripke
hw/usb/dev-smartcard-reader.c:
add multi option for a multislot smartcard reader, similar to audio
multi
---
hw/usb/dev-smartcard-reader.c | 106 +-
1 file changed, 103 insertions(+), 3 deletions(-)
diff --git a/hw/usb/dev-smartcard-re
On Tue, Mar 14, 2023 at 4:29 AM ~abordado wrote:
>
> From: Afonso Bordado
>
> RISC-V does not expose all extensions via hwcaps, thus some userspace
> applications may want to query these via /proc/cpuinfo.
>
> Currently when querying this file the host's file is shown instead
> which is slightly
Acked-by: Guo Ren
On Sat, Mar 11, 2023 at 2:03 AM Alex Bennée wrote:
>
> This replaces the previous attempt to add c-sky.com so I've dropped
> the review/ack tags. Group everything under Alibaba now.
>
> Added as requested by LIU Zhiwei.
>
> Signed-off-by: Alex Bennée
> Cc: LIU Zhiwei
> Cc: Xu
On Fri, 2023-03-10 at 18:24 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
> Reviewed-by: Stefan Hajnoczi
With one small nit below,
Reviewed-by: Dmitry Fomichev
> ---
> block/file-posix.c | 3 +++
> block/trace-events | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/block/file-posi
On Fri, 2023-03-10 at 18:23 +0800, Sam Li wrote:
> Add zoned device option to host_device BlockDriver. It will be presented only
> for zoned host block devices. By adding zone management operations to the
> host_block_device BlockDriver, users can use the new block layer APIs
> including Report Zon
On Fri, 2023-03-10 at 18:23 +0800, Sam Li wrote:
> Signed-off-by: Sam Li
> Reviewed-by: Stefan Hajnoczi
> Reviewed-by: Damien Le Moal
> Reviewed-by: Hannes Reinecke
Looks good to me.
Reviewed-by: Dmitry Fomichev
> ---
> include/block/block-common.h | 43
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by in2_ri2().
Reported-by: Nina Schoetterl-Glausch
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions
as targets.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target| 1 +
tests/tcg/s390x/ex-relative-long.c | 149 +
2 files changed, 150 insertions(+)
create mode 100644 tests/
Hi,
This series fixes EXECUTE of instructions like LARL, LGLR, etc.
Currently the address calculation uses EXECUTE's address as a base,
while it should be using that of the target instruction.
Patch 1 fixes the issue, patch 2 adds a test.
Best regards,
Ilya
Ilya Leoshkevich (2):
target/s390x:
Hi, David,
On Mon, Mar 13, 2023 at 4:45 AM David Woodhouse wrote:
>
> On Sun, 2023-03-12 at 15:19 -0400, Jason Andryuk wrote:
> >
> > This breaks dm_restrict=1 since the xs_open is not allowed by the
> > time
> > this is called. There are other evtchn errors before this as well:
> > # cat /var/l
On Mon, 2023-03-13 at 10:01 +, Peter Maydell wrote:
> On Mon, 13 Mar 2023 at 00:26, Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > Fixup a few minor typos
>
> Typo in patch subject line: should be 'block' :-)
Ha! already sent a V2 for this :)
>
> > Signed-off-by: Wilfred M
I'm attempting to implement the support of ACPI "generic port" detailed
in the ACPI r6.5 spec in QEMU. The spec section 5.2.16.7 details the
Generi Port Affinity Structure where it ties a Device Handle to a
Proximity Domain. And with section 6.2.28.4 for the HMAT table, the
latency and bandwidt
On Mon, 13 Mar 2023 at 19:21, Richard Henderson
wrote:
>
> On 3/13/23 04:44, Luis Machado wrote:
> >> Luis: I think that rather than doing (2) with a QEMU namespace,
> >> we should define a gdb namespace for this. That makes it clear
> >> that this is still a gdb-upstream-sanctioned way of exposin
On 3/13/23 12:49, Anup Patel wrote:
On Mon, Mar 13, 2023 at 7:49 AM Hang Xu wrote:
Because the starting address of ram is not necessarily 0,
the remaining free space in ram is
ram_size - (start - ram_base) instead of ram_size-start.
Signed-off-by: Hang Xu
What happens in-case a platform
TCG emulates ckc, cputm, last_break and prefix, and it's quite useful
to have them during debugging.
So move them into the new s390-virt-tcg.xml file.
pp, pfault_token, pfault_select and pfault_compare are not emulated,
so keep them in s390-virt.xml.
Signed-off-by: Ilya Leoshkevich
---
configs
On 2023-03-10 19:03, Alex Bennée wrote:
AMD recently acquired Xilinx and contributors have been transitioning
their emails across.
> Signed-off-by: Alex Bennée
Reviewed-by: Francisco Iglesias
Cc: Vikram Garhwal
Cc: Francisco Iglesias
Cc: Stefano Stabellini
Cc: Sai Pavan Boddu
Cc: To
+CodeSourcery folks
On 13/3/23 19:33, Thomas Huth wrote:
Marek and Chris haven't been active for Nios II since years
(the last time seems to have been in 2017), and we've got
unhandled severe Nios II bug tickets in the bug tracker since
a long time, so to avoid wrong expectations of people who a
On 13/3/23 17:18, Thomas Huth wrote:
https://gitlab.com/thuth/qemu/-/jobs/3920337136#L307
... but I think that was pre-existing and was caused by one of
Philippe's reworks, hopefully to be fixed soon ... Phillipe?
Jiaxun fixed this on little-endian hosts, but this is still
failing on big-e
From: Afonso Bordado
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a basic /proc/cpuinfo file
with mmu info and
On 3/13/23 08:10, Fabiano Rosas wrote:
We currently don't have the reading of pauth regs implemented for KVM
so wrap the pauth registration with CONFIG_TCG.
This avoids the build error when using --disable-tcg:
libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub64.c.o: in function
`aarch64_gdb_get_
Am 13.03.23 um 13:28 schrieb Dorinda Bassey:
Hi Volker,
Thanks for the patch, I've tested the patch and it works. I don't hear
the choppy audio with this option "qemu-system-x86_64 -device
ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
pipewire,id=audio0,out.frequency=96000,in.fr
From: Marc-André Lureau
ANGLE fails to compile shaders otherwise.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/shader/texture-blit-flip.vert | 1 -
ui/shader/texture-blit.frag | 1 -
ui/shader/texture-blit.vert | 1 -
3 files changed, 3 deletions(-)
diff
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
ui/egl-helpers.c | 54 ++--
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index 3a88245b67..b1183741
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
audio/audio_int.h | 2 +-
audio/dbusaudio.c | 7 +--
ui/dbus.c | 2 +-
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/audio/audio_int.h b/audio/audio_int.h
index d51d63f08d.
From: Marc-André Lureau
Enable SDL logging when QEMU_ENABLE_SDL_LOGGING variable is set, as
suggested by Sam Lantinga, upstream SDL maintainer.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/sdl2.c | 4
1 file changed, 4 insertions(+)
diff --git a/ui/sdl2.c b/ui
From: Marc-André Lureau
Allow to build & use the DBus display without 3d/GPU acceleration support.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
meson.build | 4 ++--
ui/dbus-listener.c | 15 +--
ui/dbus.c | 8
tests
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/console.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/ui/console.c b/ui/console.c
index 35f8274aab..f3783021e5 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -95,6 +95,7 @@ struct Qe
From: Marc-André Lureau
There is no guarantee to have a current GL context here. The current
code seems to rely on the renderer using a GL backend, and to set a
current GL context. But this is not always the case, for example if the
renderer backend is DirectX.
This change is enough to fix using
From: Marc-André Lureau
The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
Merge tag 'win-socket-pull-request' of
https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17
+)
are available in the Git repository at:
https://gitlab.com/marcand
From: Marc-André Lureau
Future patches will introduce EGL support on win32 (too late for 8.0
though). Having a common place for EGL initialization and error handling
will make it simpler.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/egl-helpers.h | 2 ++
ui
From: Marc-André Lureau
-display sdl,gl=es didn't actually use OpenGL ES.
Using OpenGL ES allows to use ANGLE, which works generally better than
Windows/OEM OpenGL driver.
(note: users can still bypass the QEMU choice with SDL_RENDER_DRIVER
environment variable)
(note: for some reason, specify
From: Marc-André Lureau
We can enable EGL later for non-GBM hosts.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/dbus-listener.c | 10 +-
ui/dbus.c | 12 +++-
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/ui/dbus-listener.c
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/console.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/ui/console.c b/ui/console.c
index 0dccbdd4be..35f8274aab 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1662,6 +1662,9 @@ void regi
From: Marc-André Lureau
The naming is more conventional in QEMU.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h| 2 +-
hw/display/qxl-render.c | 4 ++--
hw/display/qxl.c| 2 +-
hw/display/vmware_vga.c | 4 ++--
ui/cursor.c | 2
From: Marc-André Lureau
Fixes unregistration with p2p connections, since they don't have an
associated name owner.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
ui/dbus-clipboard.c | 18 +++---
1 file changed, 7 insertions(+), 11 deletions(-)
diff --git a/u
From: Marc-André Lureau
It's simply by luck that dbus-display header is built first before the
other units using it.
With sourceset, I can't find an easier way out than declaring an extra
dependency for dbus-display1 generate code.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berran
From: Marc-André Lureau
The naming is more conventional in QEMU code, and allows to simplify
some code by changing the API design, so it returns the input parameter,
instead of void.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h | 2 +-
ui/cursor.c
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
ui/dbus-console.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/ui/dbus-console.c b/ui/dbus-console.c
index 0bfaa2298d..f77bc49d2e 100644
--- a/ui/dbus-console.
From: Marc-André Lureau
Keeping the current cursor around is useful, not only for VNC, but for
other displays. Let's move it down, see the following patches for other
usages.
Signed-off-by: Marc-André Lureau
Reviewed-by: Daniel P. Berrangé
---
include/ui/console.h | 1 +
ui/vnc.h
From: Marc-André Lureau
Or else, we may randomly destroy some textures..
Signed-off-by: Marc-André Lureau
Reviewed-by: Philippe Mathieu-Daudé
---
include/ui/egl-helpers.h | 2 ++
ui/dbus-listener.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/ui/egl-help
On 3/13/23 08:38, Ilya Leoshkevich wrote:
Let branching happen and try to generate a new translation block with
an odd address. Generate a specification exception in
cpu_get_tb_cpu_state().
Reported-by: Harold Grovesteen
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
On 3/13/23 11:33, Thomas Huth wrote:
Marek and Chris haven't been active for Nios II since years
(the last time seems to have been in 2017), and we've got
unhandled severe Nios II bug tickets in the bug tracker since
a long time, so to avoid wrong expectations of people who are
looking at the MAI
Am 13.03.23 um 14:11 schrieb Dorinda Bassey:
Hi Volker,
To hear this,
start QEMU with qemu-system-x86_64 -machine pcspk-audiodev=audio0
-device ich9-intel-hda -device hda-duplex,audiodev=audio0 -audiodev
pipewire,id=audio0,out.mixing-engine=off ...
I hear the clipped audio strea
On 3/13/23 04:44, Luis Machado wrote:
Luis: I think that rather than doing (2) with a QEMU namespace,
we should define a gdb namespace for this. That makes it clear
that this is still a gdb-upstream-sanctioned way of exposing
the pauth registers.
That should be fine as well, and would work to s
>
> Are you sure about sizeof(n_bytes) here? That's 4. ;-)
>
my bad!
>
> Volker's point was that "silence" is the center of the wave range. With
> signed
> range that's zero, yes, but with unsigned range that's 2^(bitdepth) / 2.
>
> So you need to memset() the correct value to generate "silence".
xbzrle_encode_buffer_avx512() checks for overflows too scarcely in its
outer loop, causing out-of-bounds writes:
$ ../configure --target-list=aarch64-softmmu --enable-sanitizers
--enable-avx512bw
$ make tests/unit/test-xbzrle && ./tests/unit/test-xbzrle
==5518==ERROR: AddressSanitizer: heap-buff
__builtin_ctzll() produces undefined results when the argument is 0.
This can be seen through test-xbzrle, which produces the following
warning:
../migration/xbzrle.c:265: runtime error: passing zero to ctz(), which is not a
valid argument
Replace __builtin_ctzll() with our ctz64() wrapper which
ailable in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
acce
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.c | 14 ++
1 file changed, 6 insertions(
This patchset strives to fix two bugs at xvzrle when --enable-avx512 is
used: an out-of-bounds write and an invalid argument to __builtin_ctz().
Those two errors can be seen in the test suite running:
$ ../configure --target-list=aarch64-softmmu --enable-sanitizers
--enable-avx512bw
$ make tests
On Mon, Mar 13, 2023 at 5:58 AM Marc-André Lureau
wrote:
>
> Hi Gurchetan
>
> On Tue, Mar 7, 2023 at 2:41 AM Gurchetan Singh
> wrote:
> >
> > On Tue, Jan 31, 2023 at 3:15 PM Dmitry Osipenko
> > wrote:
> > >
> > > Hello,
> > >
> > > On 1/30/23 20:00, Alex Bennée wrote:
> > > >
> > > > Antonio Cag
Le 20/02/2023 à 22:24, Markus Armbruster a écrit :
Ben is no longer with intel. He told me he expected to get back to
CXL, but it's not happening as quickly as he'd like, and that it's
best to remove him as maintainer. So let's do that.
Thank you for serving as maintainer, Ben!
Signed-off-by:
Marek and Chris haven't been active for Nios II since years
(the last time seems to have been in 2017), and we've got
unhandled severe Nios II bug tickets in the bug tracker since
a long time, so to avoid wrong expectations of people who are
looking at the MAINTAINERS file, it's maybe best to mark
W dniu 13.03.2023 o 04:39, Chen Baozi pisze:
Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
Signed-off-by: Chen Baozi
Tested-by: Marcin Juszkiewicz
~ # cat
Le 13/02/2023 à 11:53, Damien Hedde a écrit :
Also update mailmap
Signed-off-by: Damien Hedde
---
MAINTAINERS | 2 +-
.mailmap| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..ceeda49d49 100644
--- a/MAINTAINERS
+++ b/MAINTA
On Mon, 13 Mar 2023 at 17:30, Peter Maydell wrote:
> So I think the problem here is not with Sphinx, but with the
> kernel-doc script. That script has an option "-Werror" which
> turns its warnings into errors, but our Sphinx extension
> docs/sphinx/kerneldoc.py does not set it. I think we need to
Add a virtio-fs-specific vhost-user interface to facilitate migrating
back-end-internal state. We plan to migrate the internal state simply
as a binary blob after the streaming phase, so all we need is a way to
transfer such a blob from and to the back-end. We do so by using a
dedicated area of s
A virtio-fs device's VM state consists of:
- the virtio device (vring) state (VMSTATE_VIRTIO_DEVICE)
- the back-end's (virtiofsd's) internal state
We get/set the latter via the new vhost-user operations FS_SET_STATE_FD,
FS_GET_STATE, and FS_SET_STATE.
Signed-off-by: Hanna Czenczek
---
hw/virtio
Hi,
Patch 1 of this RFC series adds virtio-fs-specific operations to vhost
for transferring a binary blob of back-end-internal state, and
implements those for vhost-user.
Patch 2 uses those operations to implement stateful migration for
vhost-user-fs devices, assuming the back-end (virtiofsd) sup
Le 02/02/2023 à 23:31, John Snow a écrit :
Signed-off-by: John Snow
---
qemu-options.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index d59d19704bc..52d477547f5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1606,7 +1606,7 @@
On Mon, 13 Mar 2023 at 17:14, Thomas Huth wrote:
>
> On 13/03/2023 18.03, Peter Maydell wrote:
> > On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
> >> I also keep running into this problem ... I wonder whether we should run
> >> sphinx with "-W" to turn warnings into errors when configure has b
Replace python 2 format string with f-strings
Signed-off-by: Marco Liebel
---
target/hexagon/gen_helper_funcs.py | 54 ++--
target/hexagon/gen_helper_protos.py | 10 +-
target/hexagon/gen_idef_parser_funcs.py | 8 +-
target/hexagon/gen_op_attribs.py| 4 +-
target/hexagon/g
On 230313 1608, Peter Maydell wrote:
> On Mon, 13 Mar 2023 at 15:41, Philippe Mathieu-Daudé
> wrote:
> > Now I wonder again if this is a good time to merge this change set.
>
> No, I don't think it is at this point in the release
> cycle. I would vote for merging it when we reopen for 8.1,
> so
On 13/03/2023 18.03, Peter Maydell wrote:
On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
On 10/03/2023 11.31, Alex Bennée wrote:
The kerneldoc processor complains about the mismatched variable name.
Fix it.
Signed-off-by: Alex Bennée
---
include/exec/memory.h | 2 +-
1 file changed,
On Mon, 13 Mar 2023 at 11:46, wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of
> https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00
> +)
>
> are avai
On Wed, Feb 22, 2023 at 03:37:51PM +0100, Paolo Bonzini wrote:
> Python 3.6 was EOL 2021-12-31. Newer versions of upstream libraries have
> begun dropping support for this version and it is becoming more
> cumbersome to support. Avocado-framework and qemu.qmp each have their
> own reasons for wanti
On Mon, 13 Mar 2023 at 17:00, Thomas Huth wrote:
>
> On 10/03/2023 11.31, Alex Bennée wrote:
> > The kerneldoc processor complains about the mismatched variable name.
> > Fix it.
> >
> > Signed-off-by: Alex Bennée
> > ---
> > include/exec/memory.h | 2 +-
> > 1 file changed, 1 insertion(+), 1
On 10/03/2023 11.31, Alex Bennée wrote:
The kerneldoc processor complains about the mismatched variable name.
Fix it.
Signed-off-by: Alex Bennée
---
include/exec/memory.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 6
Hello!
INC2534320 ([PATCH v1] hw/pvrdma: Protect against buggy or malicious guest
driver) has been updated.
Opened for: yuval.shaia...@gmail.com
Followers: qemu-devel@nongnu.org, soulchen8...@gmail.com, Mauro Matteo
Cascella, qemu-secur...@nongnu.org, yuval.shaia...@gmail.com,
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