On 09/01/2023 21.53, B wrote:
This made me wonder if a better approach here would be to move the logic that determines
if LOST_TICK_POLICY_SLEW is available into the "lost_tick_policy" property
setter defined at
https://gitlab.com/qemu-project/qemu/-/blob/master/hw/core/qdev-properties-syste
On 09/01/23 7:44 pm, Daniel P. Berrangé wrote:
On Mon, Dec 26, 2022 at 05:33:27AM +, Het Gala wrote:
From: Author Het Gala
Existing uri is encoded at multiple levels to extract the relevant
migration information.
The modified QAPI design maps migration parameters into MigrateChannel
str
On 09/01/23 7:37 pm, Daniel P. Berrangé wrote:
On Mon, Dec 26, 2022 at 05:33:25AM +, Het Gala wrote:
From: Author Het Gala
Existing 'migrate' QAPI design enforces transport mechanism, ip address
of destination interface and corresponding port number in the form
of a unified string 'uri'
On 9/1/23 23:49, Emilio Cota wrote:
To fix potential deadlocks as reported by tsan.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio Cota
---
plugins/core.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/1/23 20:03, Markus Armbruster wrote:
Signed-off-by: Markus Armbruster
---
ui/input.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/1/23 20:03, Markus Armbruster wrote:
Signed-off-by: Markus Armbruster
---
include/monitor/hmp.h | 1 +
include/ui/console.h | 2 +-
monitor/misc.c| 1 -
ui/input.c| 15 +++
ui/ui-hmp-cmds.c | 8
5 files changed, 17 insertions(+), 10
On 9/1/23 20:03, Markus Armbruster wrote:
hmp_mouse_set() doesn't bail out when it can't find a mouse.
Harmless, since qemu_input_check_mode_change() should be a no-op then.
Clean it up anyway.
Signed-off-by: Markus Armbruster
---
ui/input.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On 9/1/23 20:03, Markus Armbruster wrote:
Keys are int. HMP sendkey assigns them from the value strtoul(),
silently truncating values greater than INT_MAX. Fix to reject them.
Signed-off-by: Markus Armbruster
Reviewed-by: Daniel P. Berrangé
---
monitor/hmp-cmds.c | 8 ++--
1 file chan
On Jan 10 08:17, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Hi,
>
> The following changes since commit 528d9f33cad5245c1099d77084c78bb2244d5143:
>
> Merge tag 'pull-tcg-20230106' of https://gitlab.com/rth7680/qemu into
> staging (2023-01-08 11:23:17 +)
>
> are available in the Git rep
From: Klaus Jensen
The eventidx and doorbell value are not handling endianness correctly.
Fix this.
Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support")
Cc: qemu-sta...@nongnu.org
Reported-by: Guenter Roeck
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme
From: Klaus Jensen
Replace various ->parent_obj use with the equivalent QOM accessors.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 89 +++---
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/hw
From: Klaus Jensen
Rename the trace events related to writing the event index and reading
the doorbell value to make it more clear that the event is associated
with an actual update (write or read respectively).
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Keith Busch
Signed-off-by: Klaus
From: Klaus Jensen
Hi,
The following changes since commit 528d9f33cad5245c1099d77084c78bb2244d5143:
Merge tag 'pull-tcg-20230106' of https://gitlab.com/rth7680/qemu into staging
(2023-01-08 11:23:17 +)
are available in the Git repository at:
git://git.infradead.org/qemu-nvme.git tags
From: Klaus Jensen
Prior to reading the shadow doorbell cq head, we have to update the
eventidx. Otherwise, we risk that the driver will skip an mmio doorbell
write. This happens on riscv64, as reported by Guenter.
Adding the missing update to the cq eventidx fixes the issue.
Fixes: 3f7fe8de3d4
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
as noted in docs/igd-assign.txt in the Qemu source code.
Currently, when the xl toolstack is used to configure a Xen HVM guest with
Intel IGD passthrough to the guest with the Qemu upstream device model,
a Qemu emulated PCI devi
Hi John
On Tue, Jan 10, 2023 at 1:06 AM John Snow wrote:
>
> On Mon, Jul 25, 2022 at 7:23 AM Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Fri, Jul 1, 2022 at 2:51 AM John Snow wrote:
> >>
> >> On Thu, Jun 30, 2022 at 8:34 AM wrote:
> >> >
> >> > From: Marc-André Lureau
> >> >
> >> > Hi,
>
On 1/10/2023 12:27 AM, Michael S. Tsirkin wrote:
> On Mon, Jan 09, 2023 at 07:05:35PM -0500, Chuck Zmudzinski wrote:
> > On 1/9/23 6:33 PM, Michael S. Tsirkin wrote:
> > > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> > >> Intel specifies that the Intel IGD must occupy slot 2
On 1/9/23 14:42, Fabiano Rosas wrote:
We want to move sme_helper into the tcg directory, but the cpregs
accessor functions cannot go along, otherwise they would be separate
from the respective ARMCPRegInfo definition which needs to be compiled
with CONFIG_TCG=n as well.
Hmm. I would have hoped
On 1/9/23 14:42, Fabiano Rosas wrote:
-hw_breakpoint_update_all(cpu);
-hw_watchpoint_update_all(cpu);
+if (tcg_enabled()) {
+hw_breakpoint_update_all(cpu);
+hw_watchpoint_update_all(cpu);
+}
This and the other tcg_enabled() addition don't belong with code move
On 1/9/23 14:42, Fabiano Rosas wrote:
target/arm/cpu.c |1 +
target/arm/machine.c |1 +
target/arm/meson.build |1 +
target/arm/op_helper.c |1 +
target/arm/translate-a64.c |1 +
target/arm/translate.c |1 +
These additions of #include "
On Mon, Jan 09, 2023 at 09:11:22PM -0500, Chuck Zmudzinski wrote:
> On 1/9/2023 7:05 PM, Chuck Zmudzinski wrote:
> > On 1/9/23 6:33 PM, Michael S. Tsirkin wrote:
> > > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> > >> Intel specifies that the Intel IGD must occupy slot 2 on t
On Mon, Jan 09, 2023 at 07:05:35PM -0500, Chuck Zmudzinski wrote:
> On 1/9/23 6:33 PM, Michael S. Tsirkin wrote:
> > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> >> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> >> as noted in docs/igd-assign.txt in t
Hi Jason,
> From: Jason Wang
> Sent: Monday, December 5, 2022 10:25 PM
>
> A dumb question, any reason we need bother with virtio-net? It looks to me
> it's
> not a must and would complicate migration compatibility.
Virtio net vdpa device is processing the descriptors out of order.
This vdpa
On Mon, Jan 09, 2023 at 13:52:36 +, Alex Bennée wrote:
> Emilio Cota writes:
> > --- a/accel/tcg/cpu-exec.c
> > +++ b/accel/tcg/cpu-exec.c
> > @@ -504,6 +504,7 @@ static void cpu_exec_exit(CPUState *cpu)
> > if (cc->tcg_ops->cpu_exec_exit) {
> > cc->tcg_ops->cpu_exec_exit(cpu);
>
On 1/9/2023 7:05 PM, Chuck Zmudzinski wrote:
> On 1/9/23 6:33 PM, Michael S. Tsirkin wrote:
> > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> >> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> >> as noted in docs/igd-assign.txt in the Qemu source code.
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
Signed-off-by: David Reiss
---
target/arm/cpu.h | 4 +-
target/arm/gdbstub.c | 149 +
From: David Reiss
Follows a fairly similar pattern to the existing special register debug
support. Only reading is implemented, but it should be possible to
implement writes.
`v7m_mrs_control` was renamed `arm_v7m_mrs_control` and made
non-static so this logic could be shared between the MRS in
From: David Reiss
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
the Main Extension. However, the MRS instruction did not check this,
and the MSR instruction handled it inconsistently (warning BASEPRI, but
silently ignoring writes to BASEPRI_NS). Unify this behavior an
On 1/9/23 6:35 PM, Michael S. Tsirkin wrote:
> On Mon, Jan 09, 2023 at 06:28:44PM -0500, Chuck Zmudzinski wrote:
>> On 1/9/23 5:33 PM, Michael S. Tsirkin wrote:
>> > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
>> >> Intel specifies that the Intel IGD must occupy slot 2 on the
On 1/9/23 6:33 PM, Michael S. Tsirkin wrote:
> On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
>> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
>> as noted in docs/igd-assign.txt in the Qemu source code.
>>
>> Currently, when the xl toolstack is used to co
Am 9. Januar 2023 12:08:16 UTC schrieb "Philippe Mathieu-Daudé"
:
>The point of a getter() function is to not expose the structure
>internal fields. Otherwise callers could simply access the
>PFlashCFI01::mem field.
The getter also works with a typedef which doesn't need the structure exposed.
On Mon, Jan 09, 2023 at 06:28:44PM -0500, Chuck Zmudzinski wrote:
> On 1/9/23 5:33 PM, Michael S. Tsirkin wrote:
> > On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> >> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> >> as noted in docs/igd-assign.txt in t
On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> as noted in docs/igd-assign.txt in the Qemu source code.
>
> Currently, when the xl toolstack is used to configure a Xen HVM guest with
> Intel IGD passthroug
On 1/9/23 5:33 PM, Michael S. Tsirkin wrote:
> On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
>> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
>> as noted in docs/igd-assign.txt in the Qemu source code.
>>
>> Currently, when the xl toolstack is used to co
The default qemu upstream "xenfv" machine type that is used when an HVM
guest is configured for Intel IGD passthrough assigns slot 2 to the
xen platform pci device. It is a requirement that slot 2 be assigned to
the Intel IGD when it is passed through as the primary graphics adapter.
Using the "pc"
By default, except for the ich9-usb-uhci device which libxl assigns to
slot 29 (0xid), libxl defers to qemu upstream's automatic slot assignment
process, which is simply to assign each emulated device to the next
available slot on the pci bus. With this default behavior, libxl and
qemu will not con
Sorry for the length of this cover letter but it is helpful to put all
the pros and cons of the two different approaches to solving the problem
of configuring the Intel IGD with qemu upstream and libxl in one place,
which I attempt to do here. Of course the other approach involves a
patch to qemu [
It is possible for the administrator to manually specify the virtual
slot addresses of passed through pci devices on the guest's pci bus
using the @VSLOT parameter in xl.cfg. With this patch, libxl will by
default assign the Intel IGD to slot 2 when gfx_passthru is configured
for the Intel IGD so i
On Fri, Dec 30, 2022 at 12:26 PM ~elta wrote:
>
> From: Dongxue Zhang
>
> Should be cpu->cfg.elen in range [8, 64].
>
> Signed-off-by: Dongxue Zhang
> Reviewed-by: LIU Zhiwei
> Message-ID:
> Reviewed-by: Frank Chang
> Message-ID:
>
Reviewed-by: Alistair Francis
Thanks!
Applied to riscv-
On Mon, Jan 9, 2023 at 4:01 PM Qiang Liu wrote:
>
> This patch checks if the s->tx_fifo is full.
>
> Fixes: 58ac482a66de ("introduce xlnx-dp")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1424
> Reported-by: Qiang Liu
> Signed-off-by: Qiang Liu
Reviewed-by: Alistair Francis
Alist
On Mon, Jan 9, 2023 at 10:24 PM Philippe Mathieu-Daudé
wrote:
>
> Nothing here requires access to PFlashCFI01 internal fields:
> use the inherited generic DeviceState.
>
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Daniel Henrique Barboza
> Reviewed-by: Bin Meng
Reviewed-by: Alistair
On Thu, Dec 29, 2022 at 8:33 PM Bin Meng wrote:
>
> At present create_fdt() calls htif_uses_elf_symbols() to determine
> whether to insert a property for the HTIF. This unfortunately
> creates a hidden dependency to riscv_load_{firmware,kernel} that
> create_fdt() must be called after the ELF {fi
Per docs/system/deprecated.rst, a deprecated feature can be
removed after 2 releases. Since we commit when a class property
is deprecated, we can warn when the deprecation period is over.
See also commit ef1f5b0a96 ("docs: clarify deprecation schedule").
Signed-off-by: Philippe Mathieu-Daudé
---
Add qemu_version_delta() to compare 2 QEMU versions,
and qemu_version_delta_current() to compare with the
current QEMU version.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qemu/qemu-version.h | 36
util/meson.build| 1 +
util/qemu-version.c
Use the same property name than the TYPE_PFLASH_CFI01 model.
Deprecate the current 'width' property and add the 'device-width'
property pointing to the same field in PFlashCFI02.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/block/pflash_cfi02.c | 8 +++-
1 file changed, 7 insertions(+), 1 d
Introduce object_class_property_deprecate() to register
a QOM property as deprecated. When this property's getter /
setter is called, a deprecation warning is displayed on the
monitor.
Inspired-by: Daniel P. Berrange
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 17 ++
On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote:
>
> This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version
> instructions.
>
> Specification:
> https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
>
> The port is available here:
> https://github.com/plctlab/p
Hi,
There will always be a need to deprecate things. Here I'm
tackling the QOM (class) properties, since they can be set
from some CLI options (-object -device -global ...).
As an experiment, we add object_class_property_deprecate()
to register a class property as deprecated (since some version),
From: Claudio Fontana
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
This struct has no dependencies on TCG code and it is being used in
target/arm/ptw.c to simplify the passing around of page table walk
results. Those routines can be reached by KVM code via the gdbstub
breakpoint code, so take the structure out of CONFIG_TCG to make it
visible when building with --
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Signed-off-by: Fabiano Rosas
---
target/arm/meson.build | 1 -
target/arm/tcg/meson.build | 4
target/arm/{ => tcg}/psci.c | 0
3 files changed, 4 insertions(+), 1 deletion
Changes since v1:
- call g_free_rcu on tb_jmp_cache directly, and call
tcg_exec_unrealizefn after calling cpu_list_remove(cpu)
- add patch to de-const qemu_spin_destroy
- remove wrappers for qht_do_if_first_in_stripe
Thanks,
Emilio
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
Included {sme,mve}_helper.c and left a couple of files behind that
still have non-tcg code to be removed from them:
helper.c (and op_helper.h as a dep)
vfp_helper.c
Originally
Fixes this tsan crash, easy to reproduce with any large enough program:
$ tests/unit/test-qht
1..2
ThreadSanitizer: CHECK failed: sanitizer_deadlock_detector.h:67
"((n_all_locks_)) <
(((sizeof(all_locks_with_contexts_)/sizeof((all_locks_with_contexts_)[0]"
(0x40, 0x40) (tid=1821568)
#0
To fix potential deadlocks as reported by tsan.
Reviewed-by: Richard Henderson
Signed-off-by: Emilio Cota
---
plugins/core.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/plugins/core.c b/plugins/core.c
index ccb770a485..728bacef95 100644
--- a/plugins/co
Signed-off-by: Emilio Cota
---
include/qemu/thread.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/include/qemu/thread.h b/include/qemu/thread.h
index 7c6703bce3..7841084199 100644
--- a/include/qemu/thread.h
+++ b/include/qemu/thread.h
@@ -237,11 +237,10 @@ static inli
We forgot to add this one in "a890643958 util/qht: atomically set b->hashes".
Detected with tsan.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Emilio Cota
---
util/qht.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qht.c b/util/
Fixes the appended use-after-free. The root cause is that
during tb invalidation we use CPU_FOREACH, and therefore
to safely free a vCPU we must wait for an RCU grace period
to elapse.
$ x86_64-linux-user/qemu-x86_64 tests/tcg/x86_64-linux-user/munmap-pthread
==
This function is needed by common code (ptw.c), so move it along with
the other regime_* functions in internal.h. When we enable the build
without TCG, the tlb_helper.c file will not be present.
Signed-off-by: Fabiano Rosas
---
Richard: this cannot into ptw.c because that file is softmmu only
---
From: Claudio Fontana
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Si
From: Claudio Fontana
Skip the test_device_intro_concrete for now for ARM KVM-only build,
as on ARM we currently build devices for ARM that are not
compatible with a KVM-only build.
We can remove this workaround when we fix this in KConfig etc,
and we only list and build machines that are compat
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
I also moved translate-{m-noc
From: Claudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deleti
The hflags are used only for TCG code, so introduce a new file
hflags.c to keep that code.
Signed-off-by: Fabiano Rosas
---
target/arm/helper.c| 361 +---
target/arm/internals.h | 2 +
target/arm/tcg-stubs.c | 5 +
target/arm/tcg/hflags.c|
When TCG is disabled this part of the code should not be reachable, so
wrap it with an ifdef for now.
This allows us to start using CONFIG_TCG=n (--disable-tcg in the
configure line).
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/ptw.c | 4
1 file changed, 4 i
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
---
I extracted these into a separate patch so we can discuss. If I move
the tcg_enabled check to a header that would add overhead for all the
calls where we know for sure tha
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/helper.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9cc136b508..ddb0d76b70 1006
The debug_helper.c file will move into a tcg-specific directory, so
take the cpregs code out of it. That code needs to be present in KVM
builds as well.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.c | 383 ++
target/arm/cpu.c | 7 +-
ta
The tests under tests/tcg depend on the TCG accelerator. Do not build
them if --disable-tcg was given in the configure line.
Test against CONFIG_TCG='' instead of CONFIG_TCG=y to account for
CONFIG_TCG=m.
sample output:
$ make check-tcg
GIT ui/keycodemapdb meson dtc
SKIPPED x86_64-softmm
From: Claudio Fontana
on ARM we currently list and build all machines, even when
building KVM-only, without TCG.
Until we fix this (and we only list and build machines that are
compatible with KVM), only test specifically using the "virt"
machine in this case.
Signed-off-by: Claudio Fontana
Si
We want to move sme_helper into the tcg directory, but the cpregs
accessor functions cannot go along, otherwise they would be separate
from the respective ARMCPRegInfo definition which needs to be compiled
with CONFIG_TCG=n as well.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.c | 29 +
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/machine.c | 18 +-
1 file changed, 9 insert
This series makes the necessary changes to allow the use of
--disable-tcg for arm.
For the v2 I have taken a more strict approach to avoid introducing
changes in behavior, specially regarding the cpregs hash table.
changes:
patch 5:
Move all cpregs related code from helper.c into cpregs.c;
pa
On Mon, Jan 09, 2023 at 04:55:42PM -0500, Chuck Zmudzinski wrote:
> Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> as noted in docs/igd-assign.txt in the Qemu source code.
>
> Currently, when the xl toolstack is used to configure a Xen HVM guest with
> Intel IGD passthroug
On Sun, Jan 08, 2023 at 11:19:53 -0800, Richard Henderson wrote:
> On 1/8/23 08:39, Emilio Cota wrote:
(snip)
> > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> > index 356fe348de..ca95d21528 100644
> > --- a/accel/tcg/cpu-exec.c
> > +++ b/accel/tcg/cpu-exec.c
> > @@ -1070,7 +1070,6 @@
On Sun, Jan 08, 2023 at 11:51:44 -0800, Richard Henderson wrote:
> On 1/8/23 08:39, Emilio Cota wrote:
> > +static inline void qht_bucket_lock_init(const struct qht_map *map,
> > +struct qht_bucket *b)
> > +{
> > +qht_do_if_first_in_stripe(map, b, qemu_sp
Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
as noted in docs/igd-assign.txt in the Qemu source code.
Currently, when the xl toolstack is used to configure a Xen HVM guest with
Intel IGD passthrough to the guest with the Qemu upstream device model,
a Qemu emulated PCI devi
On Fri, 2022-12-30 at 12:12 +, David Woodhouse wrote:
>
> +static void *gpa_to_hva(uint64_t gpa)
> +{
> + MemoryRegionSection mrs;
> +
> + mrs = memory_region_find(get_system_memory(), gpa, 1);
> + return !mrs.mr ? NULL : qemu_map_ram_ptr(mrs.mr->ram_block,
> +
Hi,
On 1/9/23 14:24, Eric Auger wrote:
> Hi,
>
> we have a trouble with virtio-iommu and protected assigned devices
> downstream to a pcie-to-pci bridge. In that use case we observe the
> assigned devices are not put to any group. This is true on both x86 and
> aarch64. This use case works with i
On Mon, Jul 25, 2022 at 5:06 AM Daniel P. Berrangé wrote:
>
> On Fri, Jul 22, 2022 at 11:25:08AM -0700, Peter Delevoryas wrote:
> > On macOS, private $TMPDIR's are the default. These $TMPDIR's are
> > generated from a user's unix UID and UUID [1], which can create a
> > relatively long path:
> >
>
On 1/9/23 14:01, Stefan Berger wrote:
On 1/9/23 13:51, James Bottomley wrote:
On Mon, 2023-01-09 at 13:34 -0500, Stefan Berger wrote:
On 1/9/23 12:55, James Bottomley wrote:
On Mon, 2023-01-09 at 17:52 +, Dr. David Alan Gilbert
wrote:
* James Bottomley (j...@linux.ibm.com) wrote:
On Mon, Jul 25, 2022 at 7:23 AM Marc-André Lureau
wrote:
>
> Hi
>
> On Fri, Jul 1, 2022 at 2:51 AM John Snow wrote:
>>
>> On Thu, Jun 30, 2022 at 8:34 AM wrote:
>> >
>> > From: Marc-André Lureau
>> >
>> > Hi,
>> >
>> > As reported earlier by Richard Henderson ("virgl avocado hang" thread),
>>
Am 9. Januar 2023 20:12:29 UTC schrieb Thomas Huth :
>On 04/01/2023 09.55, Mark Cave-Ayland wrote:
>> On 03/01/2023 08:47, Thomas Huth wrote:
>>
>>> We want to get rid of the "#ifdef TARGET_I386" statements in the mc146818
>>> code, so we need a different way to decide whether the slew tick pol
The board doesn't seem to have an ISA bus at all.
Signed-off-by: Bernhard Beschow
---
hw/mips/mipssim.c | 1 -
hw/mips/Kconfig | 3 +--
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index 39f64448f2..f459550c13 100644
--- a/hw/mips/mipssim.
These devices should now be selected by their respective boards or
parent devices.
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 9 -
1 file changed, 9 deletions(-)
diff --git a/configs/devices/mips-softmmu/common.mak
b/configs/devices/mips-softmmu/commo
Allows to see more easily which board has which devices.
Signed-off-by: Bernhard Beschow
---
configs/devices/mips-softmmu/common.mak | 7 ---
configs/devices/mips64el-softmmu/default.mak | 3 ---
hw/mips/Kconfig | 12
3 files changed, 12 inser
isa-superio.c, managed by ISA_SUPERIO, instantiates TYPE_ISA_PARALLEL,
managed by PARALLEL.
Signed-off-by: Bernhard Beschow
---
hw/isa/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 040a18c070..58137f2702 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa
This series aims for cleaning up the dependency graphs of MIPS boards in order
to see much quicker which board uses which hardware -- and thus, which board
can be used to test which hardware.
The final patch has been compiled successfully multiple times for mips64el with
only one board enabled res
On Tue, Jan 10, 2023 at 2:25 AM Daniel P. Berrangé wrote:
>
> On Mon, Jan 09, 2023 at 05:14:38PM +, Peter Maydell wrote:
> > I've just noticed that our (optional) FreeBSD 13 CI job is
> > failing while running the qemu-iotests, like this:
> >
> > +ld-elf.so.1: /usr/local/bin/bash: Undefined sy
Split into per_branch_dest and per_branch_disp, which can be
used for direct and indirect. In preperation for TARGET_TB_PCREL,
call per_branch_* before indirect branches.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 30 +-
In db9aab5783a2 we broke the contract of s390_probe_access, in that it
no longer returned an exception code, nor set __excp_addr. Fix both.
Reported-by: David Hildenbrand
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 31 ++-
1 file changed, 18
The interface from probe_access_flags is void*, and matching
that will be helpful. We already rely on the gcc extension
for byte arithmetic on void*.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
When this code was written, it was using tlb_vaddr_to_host,
which does not handle TLB_DIRTY. Since then, it has been
converted to probe_access_flags, which does.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 74 +++
1 file changed, 22 inser
Ensure that the total length is in a local variable
across the byte loop. Compute size1 difference once.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s3
Passing a pointer from the caller down to access_prepare_nf
eliminates a structure copy.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 100 +-
1 file changed, 50 insertions(+), 50 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/ta
Always use a tcg branch, instead of movcond. The movcond
was not a bad idea before PER was added, but since then
we have either 2 or 3 actions to perform on each leg of
the branch, and multiple movcond is inefficient.
Reorder the taken branch to be fallthrough of the tcg branch.
This will be help
On 04/01/2023 09.55, Mark Cave-Ayland wrote:
On 03/01/2023 08:47, Thomas Huth wrote:
We want to get rid of the "#ifdef TARGET_I386" statements in the mc146818
code, so we need a different way to decide whether the slew tick policy
is available or not. Introduce a new property "slew-tick-policy-
All callers pass s->pc_tmp.
Reviewed-by: Ilya Leoshkevich
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/transla
Complicated because we may now require a runtime jump.
Reviewed-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
target/s390x/tcg/translate.c | 40 +---
1 file changed, 28 insertions(+), 12 deletions(-)
diff --git a/target/s390x/tcg/translate.c b/target
Assign to access struct immediately, rather than waiting
until the end of the function. This means we can pass
address of haddr struct members instead of allocating
extra space on the local stack.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 30 +-
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