On Wed, Nov 2, 2022 at 5:41 AM Bernhard Beschow wrote:
>
> GCC issues a false positive warning, resulting in build failure with -Werror:
>
> In file included from /usr/lib/glib-2.0/include/glibconfig.h:9,
>from /usr/include/glib-2.0/glib/gtypes.h:34,
>from
On 31/10/2022 20.10, Amarjargal Gundjalam wrote:
On 26/10/22 00:22, Thomas Huth wrote:
On 25/10/2022 16.28, Amarjargal Gundjalam wrote:
The TABs should be replaced with spaces, to make sure that we have a
consistent coding style with an indentation of 4 spaces everywhere.
Resolves: https://gi
On Wed, Nov 02, 2022 at 01:42:39PM +0800, Jason Wang wrote:
> On Tue, Nov 1, 2022 at 12:19 AM wrote:
> >
> > From: Hyman Huang(黄勇)
> >
> > For netdev device that can offload virtio-net dataplane to slave,
> > such as vhost-net, vhost-user and vhost-vdpa, exporting it's
> > capability information
On Tue, Nov 01, 2022 at 10:39:36PM +0100, Bernhard Beschow wrote:
> GCC issues a false positive warning, resulting in build failure with -Werror:
>
> In file included from /usr/lib/glib-2.0/include/glibconfig.h:9,
>from /usr/include/glib-2.0/glib/gtypes.h:34,
>
On 11/1/22 22:44, Philippe Mathieu-Daudé wrote:
Fix invalid string formats reported by Stefan:
https://lore.kernel.org/qemu-devel/78553699-00c1-ad69-1d58-02f75a1f4...@weilnetz.de/
Philippe Mathieu-Daudé (5):
disas/nanomips: Fix invalid PRId64 format calling img_format()
disas/nanomips: Fix
On 11/1/22 18:32, Song Gao wrote:
We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.
Signed-off-by: Song Gao
---
target/loongarch/cpu.c | 7 +++--
target/loongarch/cpu.h | 58 ++
2 files changed,
On 11/1/22 18:32, Song Gao wrote:
When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
#include
void (*func)(int *);
Reversed the sense of non-secure in get_phys_addr_lpae,
and failed to initialize attrs.secure for ARMMMUIdx_Phys_S.
Fixes: 48da29e4 ("target/arm: Add ptw_idx to S1Translate")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1293
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 15 +
On Tue, Nov 1, 2022 at 12:19 AM wrote:
>
> From: Hyman Huang(黄勇)
>
> For netdev device that can offload virtio-net dataplane to slave,
> such as vhost-net, vhost-user and vhost-vdpa, exporting it's
> capability information and acked features would be more friendly for
> developers. These infomati
On 11/1/22 17:42, Ake Koomsin wrote:
We need to check HCR_E2H and HCR_TGE to select the right MMU index for
the correct translation regime.
To check for EL2&0 translation regime:
- For S1E0*, S1E1* and S12E* ops, check both HCR_E2H and HCR_TGE
- For S1E2* ops, check only HCR_E2H
Signed-off-by:
> -Original Message-
> From: Christian Schoenebeck
> Sent: Wednesday, November 2, 2022 02:59
> To: qemu-devel@nongnu.org
> Cc: Greg Kurz ; Meng, Bin ; Shi,
> Guohuai
> Subject: Re: [PATCH 09/16] hw/9pfs: Disable unsupported flags and features
> for Windows
>
> [Please note: This e-mai
On Tue, Nov 01, 2022 at 03:00:31PM -0400, Stefan Hajnoczi wrote:
> /* Let's try to use the logical blocksize for the alignment. */
> -if (probe_logical_blocksize(fd, &bs->bl.request_alignment) < 0) {
> -bs->bl.request_alignment = 0;
> +if (!bs->bl.request_alignment) {
> +
> -Original Message-
> From: Christian Schoenebeck
> Sent: Wednesday, November 2, 2022 02:22
> To: qemu-devel@nongnu.org
> Cc: Greg Kurz ; Meng, Bin ; Shi,
> Guohuai
> Subject: Re: [PATCH 07/16] hw/9pfs: Implement Windows specific utilities
> functions for 9pfs
>
> [Please note: This
On Tue, Nov 01, 2022 at 07:27:16PM -0700, Eric Biggers wrote:
> On Tue, Nov 01, 2022 at 03:00:30PM -0400, Stefan Hajnoczi wrote:
> > Linux dm-crypt returns errno EIO from unaligned O_DIRECT pread(2) calls.
>
> Citation needed. For direct I/O to block devices, the kernel's block layer
> checks the
On Tue, Nov 01, 2022 at 03:00:30PM -0400, Stefan Hajnoczi wrote:
> Linux dm-crypt returns errno EIO from unaligned O_DIRECT pread(2) calls.
Citation needed. For direct I/O to block devices, the kernel's block layer
checks the alignment before the I/O is actually submitted to the underlying
block
On 2022/11/2 03:51, Michael S. Tsirkin wrote:
On Tue, Nov 01, 2022 at 06:37:26AM -0400, Michael S. Tsirkin wrote:
On Sat, Oct 08, 2022 at 04:50:27PM +0800, Lei He wrote:
virtio-crypto: Modify the current interface of virtio-crypto
device to support asynchronous mode.
Signed-off-by: lei he
---
On 7/12/2022 10:12 AM, Xiaoyao Li wrote:
The issue that fixed by Patch 1 looks fatal though it doesn't appear on
KVM because KVM always searches with assending order and hit with the
correct cpuid leaf 0.
Patch 2 removes the wrong constraint on CPUID leaf 1f
Kindly ping.
Xiaoyao Li (2):
i
On Mon, Oct 31, 2022 at 1:49 PM Anup Patel wrote:
>
> On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis wrote:
> >
> > On Fri, Oct 28, 2022 at 2:53 AM Anup Patel wrote:
> > >
> > > The time CSR will wrap-around immediately after reaching UINT64_MAX
> > > so we don't need to re-start QEMU timer wh
On 1/11/22 23:23, Stefan Hajnoczi wrote:
There is a report that this commit breaks an existing OVMF setup:
https://gitlab.com/qemu-project/qemu/-/issues/1290#note_1156507334
I'm not familiar with pflash. Please find a way to avoid a regression
in QEMU 7.2 here.
Long-standing problem with pflas
Am 31. Oktober 2022 11:53:57 UTC schrieb "Philippe Mathieu-Daudé"
:
>Signed-off-by: Philippe Mathieu-Daudé
Indeed there is `offset & ~0x3` in both sdhci_{read,write}, so:
Reviewed-by: Bernhard Beschow
>---
> hw/sd/sdhci.c | 4
> 1 file changed, 4 insertions(+)
>
>diff --git a/hw/sd/sdhci.c
Some SDHCI IP can be synthetized in various endianness:
https://github.com/u-boot/u-boot/blob/v2021.04/doc/README.fsl-esdhc
- CONFIG_SYS_FSL_ESDHC_BE
ESDHC IP is in big-endian mode. Accessing ESDHC registers can be
determined by ESDHC IP's endian mode or processor's endian mode.
Our curre
This is a respin of Bernhard's v4 with Freescale eSDHC implemented
as an 'UNIMP' region. See v4 cover here:
https://lore.kernel.org/qemu-devel/20221018210146.193159-1-shen...@gmail.com/
Since v5:
- Rebased (ppc-next merged)
- Properly handle big-endian
Since v4:
- Do not rename ESDHC_* definition
Adds missing functionality to e500plat machine which increases the
chance of given "real" firmware images to access SD cards.
Signed-off-by: Bernhard Beschow
Message-Id: <20221018210146.193159-8-shen...@gmail.com>
[PMD: Simplify using create_unimplemented_device("esdhc")]
Signed-off-by: Philippe
Tested-by: Bernhard Beschow
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sd/sdhci.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 306070c872..22c758ad91 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1332,6 +1332,10 @@ sdhci_write(void *opaque, h
There is a report that this commit breaks an existing OVMF setup:
https://gitlab.com/qemu-project/qemu/-/issues/1290#note_1156507334
I'm not familiar with pflash. Please find a way to avoid a regression
in QEMU 7.2 here.
Thank you!
Stefan
GCC issues a false positive warning, resulting in build failure with -Werror:
In file included from /usr/lib/glib-2.0/include/glibconfig.h:9,
from /usr/include/glib-2.0/glib/gtypes.h:34,
from /usr/include/glib-2.0/glib/galloca.h:34,
from /
Original Message
From: Philippe Mathieu-Daudé [mailto:phi...@linaro.org]
- simplify code, improve comments
- fix https://gitlab.com/qemu-project/qemu/-/issues/1263
This doesn't match GitLab issues closing pattern:
https://docs.gitlab.com/ee/user/project/issues/managing_is
Original Message
From: Philippe Mathieu-Daudé [mailto:phi...@linaro.org]> diff --git
a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c>
index a79f58c963..37b04a1b53 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -77,23 +77,25 @@ static void imx_epit_update_int(IMXEP
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Le 31/10/2022 à 09:40, Drew DeVault a écrit :
References: https://gitlab.com/qemu-project/qemu/-/issues/1007
Signed-off-by: Drew DeVault
---
linux-user/syscall.c | 50 ++--
1 file changed, 44 insertions(+), 6 deletions(-)
diff --git a/linux-user/syscal
On Tue, Nov 01, 2022 at 06:37:26AM -0400, Michael S. Tsirkin wrote:
> On Sat, Oct 08, 2022 at 04:50:27PM +0800, Lei He wrote:
> > virtio-crypto: Modify the current interface of virtio-crypto
> > device to support asynchronous mode.
> >
> > Signed-off-by: lei he
> > ---
> > backends/cryptodev-bui
QEMU has entered soft feature freeze for the upcoming 7.2 release.
https://wiki.qemu.org/Planning/SoftFeatureFreeze
v7.2.0-rc0 is scheduled for tagging on November 8th.
If you encounter a bug that needs to be fixed before the release, please
create a GitLab Issue with the "7.2" milestone:
https:/
Am 1. November 2022 17:43:46 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
>> On 1/11/22 17:01, Bernhard Beschow wrote:
>>> Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow
>>> :
On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé
>>
On Tue, Nov 01, 2022 at 10:19:44AM -0500, Michael Roth wrote:
> On Tue, Nov 01, 2022 at 07:37:29PM +0800, Chao Peng wrote:
> > On Mon, Oct 31, 2022 at 12:47:38PM -0500, Michael Roth wrote:
> > > On Tue, Oct 25, 2022 at 11:13:37PM +0800, Chao Peng wrote:
> >
> > >
> > > 3) Potentially useful for
Linux dm-crypt returns errno EIO from unaligned O_DIRECT pread(2) calls.
Alignment probing fails on dm-crypt devices because the code expects
EINVAL.
Treating any errno as an "unaligned" indicator would be easy, but breaks
commit 22d182e82b4b ("block/raw-posix: fix launching with failed
disks"). O
Linux commit 825cf206ed51 ("statx: add direct I/O alignment
information") added an interface to fetch O_DIRECT alignment values for
block devices and file systems.
Prefer STATX_DIOALIGN to older interfaces and probing, but keep them as
fallbacks in case STATX_DIOALIGN cannot provide the informatio
These patches fix alignment probing with dm-crypt and add support for the new
Linux statx(STATX_DIOALIGN) interface.
Stefan Hajnoczi (2):
file-posix: fix Linux alignment probing when EIO is returned
file-posix: add statx(STATX_DIOALIGN) support
block/file-posix.c | 96 +++
Hi Jiri, Peter,
Are you able to review the more recent version of this change?
Look for the subject "[PATCH v4 x/3] hw: misc: edu: ..."
I believe I addressed all concerns.
Cheers,
C
On Mon, Oct 17, 2022 at 12:36 PM Christopher Friedt
wrote:
>
> On Mon, Oct 17, 2022 at 2:23 AM Jiri Slaby wr
On Tuesday, November 1, 2022 4:34:54 PM CET Shi, Guohuai wrote:
>
> > -Original Message-
> > From: Christian Schoenebeck
> > Sent: Tuesday, November 1, 2022 23:04
> > To: qemu-devel@nongnu.org
> > Cc: Shi, Guohuai ; Greg Kurz ;
> > Meng, Bin
> > Subject: Re: [PATCH 09/16] hw/9pfs: Disabl
On Tuesday, November 1, 2022 4:20:53 PM CET Shi, Guohuai wrote:
>
[...]
> > > > Windows POSIX API and MinGW library do not provide the NO_FOLLOW
> > > > flag, and do not allow opening a directory by POSIX open(). This
> > > > causes all
> > > > xxx_at() functions cannot work directly. However, we
Updates to issues with earlier patches in the pull request:
tests: virt: Update expected *.acpihmatvirt tables
Signed-off-by: Hesham Almatary
---
tests/data/acpi/virt/APIC.acpihmatvirt | Bin 396 -> 412 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff --git a/tests/data/acpi/virt/APIC
Updates to issues with earlier patches in the pull request:
tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT
Signed-off-by: Hesham Almatary
---
tests/data/acpi/q35/DSDT.acpihmat-noinitiator | Bin 8553 -> 8691 bytes
1 file changed, 0 insertions(+), 0 deletions(-)
diff -
On 1/11/22 18:43, Philippe Mathieu-Daudé wrote:
On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
On 1/11/22 17:01, Bernhard Beschow wrote:
Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow
:
On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé
wrote:
This is a respin of Bernhard'
On 1/11/22 17:58, Philippe Mathieu-Daudé wrote:
On 1/11/22 17:01, Bernhard Beschow wrote:
Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow
:
On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé
wrote:
This is a respin of Bernhard's v4 with Freescale eSDHC implemented
as an 'UNIM
On Tue, Nov 01, 2022 at 09:10:14PM +0530, manish.mishra wrote:
>
> On 01/11/22 8:21 pm, Daniel P. Berrangé wrote:
> > On Tue, Nov 01, 2022 at 02:30:29PM +, manish.mishra wrote:
> > > Current logic assumes that channel connections on the destination side are
> > > always established in the same
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8 deletion
pci_add_capability() checks whether capabilities overlap, and notifies
its caller so that it can properly handle the case. However, in the
most cases, the capabilities actually never overlap, and the interface
incurred extra error handling code, which is often incorrect or
suboptimal. For such case
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Indeed
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 20 +---
include/hw/pci/pci.h | 12 ++--
2 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index cce57f572c..41de7643af 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2532,1
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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Description: PGP signature
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of a PCIe function which calls
pci_add_capability() in turn is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
Acked-by: Jonathan Cameron (for CXL parts)
---
docs/pcie_sriov.txt
On 01/11/22 9:15 pm, Daniel P. Berrangé wrote:
On Tue, Nov 01, 2022 at 09:10:14PM +0530, manish.mishra wrote:
On 01/11/22 8:21 pm, Daniel P. Berrangé wrote:
On Tue, Nov 01, 2022 at 02:30:29PM +, manish.mishra wrote:
Current logic assumes that channel connections on the destination side a
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci.h | 12 ++--
hw/pci/pci.c | 18 --
2 files changed, 6 insertions(+), 24 deletions(-)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 555ac03010..da414dc728 100644
--- a/include/hw/pci/pci.h
+++ b/i
Hey Vitaly,
On 10/31/22 6:07 AM, Vitaly Kuznetsov wrote:
Liang Yan writes:
With cpu.pmu=off, perfctr_core could still be seen in an AMD guest cpuid.
By further digging, I found cpu.perfctr_core did the trick. However,
considering the 'enable_pmu' in KVM could work on both Intel and AMD,
we ma
On Wed, 26 Oct 2022 16:59:13 -0400
Gregory Price wrote:
> Early-boot e820 records will be inserted by the bios/efi/early boot
> software and be reported to the kernel via insert_resource. Later, when
> CXL drivers iterate through the regions again, they will insert another
> resource and make th
On Tue, 1 Nov 2022 13:52:21 +
Jonathan Cameron wrote:
> On Mon, 31 Oct 2022 08:51:44 -0400
> "Michael S. Tsirkin" wrote:
>
> > From: Julia Suvorova
> >
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is corre
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Tue, Nov 01, 2022 at 02:30:29PM +, manish.mishra wrote:
> Current logic assumes that channel connections on the destination side are
> always established in the same order as the source and the first one will
> always be the default channel followed by the multifid or post-copy
> preemption
On 1/11/22 01:58, Akihiko Odaki wrote:
pci_add_capability() checks whether capabilities overlap, and notifies
its caller so that it can properly handle the case. However, in the
most cases, the capabilities actually never overlap, and the interface
incurred extra error handling code, which is oft
ping
On 9/19/22 22:48, Vladimir Sementsov-Ogievskiy wrote:
For now we only log the vhost device error, when virtqueue is actually
stopped. Let's add a QAPI event, which makes possible:
- collect statistics of such errors
- make immediate actions: take coredums or do some other debugging
Th
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/pci_bridge.h| 5 ++---
hw/pci-bri
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
On 19/10/22 12:20, Bin Meng wrote:
From: Bin Meng
Fix the logic in qemu_add_wait_object() to avoid adding the same
HANDLE twice, as the behavior is undefined when passing an array
that contains same HANDLEs to WaitForMultipleObjects() API.
Signed-off-by: Bin Meng
---
(no changes since v3)
C
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of shpc_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
include/hw/pci/shpc.h | 3 +--
hw/pci-bridge/pci_bridge_de
On 01/11/22 8:21 pm, Daniel P. Berrangé wrote:
On Tue, Nov 01, 2022 at 02:30:29PM +, manish.mishra wrote:
Current logic assumes that channel connections on the destination side are
always established in the same order as the source and the first one will
always be the default channel follo
The code generating errors in pci_add_capability has a comment which
says:
> Verify that capabilities don't overlap. Note: device assignment
> depends on this check to verify that the device is not broken.
> Should never trigger for emulated devices, but it's helpful for
> debugging these.
Indeed
On Monday, October 24, 2022 6:57:58 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> Windows does not provide the getuid() API. Let's create a local
> one and return a fixed value 0 as the uid for testing.
>
> Signed-off-by: Guohuai Shi
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
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Description: PGP signature
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msix_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msix.c | 8 ++--
1 file changed, 2 insertions(+), 6 deleti
Hi; I'm trying to find out what the UI layer's threading and
locking strategy is, at least as far as it applies to display
device models.
Specifically:
* is the device's GraphicHwOps::gfx_update method always called
from one specific thread, or might it be called from any thread?
* is that me
pci_add_capability appears most PCI devices. Its error handling required
lots of code, and led to inconsistent behaviors such as:
- passing error_abort
- passing error_fatal
- asserting the returned value
- propagating the error to the caller
- skipping the rest of the function
- just ignoring
The
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Tue, 1 Nov 2022 06:32:05 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Oct 31, 2022 at 04:06:03PM -0400, Stefan Hajnoczi wrote:
> > Here is another CI failure:
> >
> > qemu-system-i386: current -smp configuration requires kernel irqchip
> > and X2APIC API support.
> > Broken pipe
> > ../tests/q
> -Original Message-
> From: Shi, Guohuai
> Sent: Tuesday, November 1, 2022 23:13
> To: Christian Schoenebeck ; qemu-devel@nongnu.org
> Cc: Greg Kurz ; Meng, Bin
> Subject: RE: [PATCH 07/16] hw/9pfs: Implement Windows specific utilities
> functions for 9pfs
>
>
>
> > -Original Me
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of msi_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/msi.c | 9 +
1 file changed, 1 insertion(+), 8 deletion
On 1/11/22 11:10, Philippe Mathieu-Daudé wrote:
On 1/11/22 00:14, Philippe Mathieu-Daudé wrote:
On 25/10/22 18:39, Peter Maydell wrote:
From: Richard Henderson
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplica
On Monday, October 24, 2022 6:57:50 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> Windows POSIX API and MinGW library do not provide the NO_FOLLOW
> flag, and do not allow opening a directory by POSIX open(). This
> causes all xxx_at() functions cannot work directly. However, we
> can provide Wi
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate heare because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
pci_add_capability() checks whether capabilities overlap, and notifies
its caller so that it can properly handle the case. However, in the
most cases, the capabilities actually never overlap, and the interface
incurred extra error handling code, which is often incorrect or
suboptimal. For such case
On Monday, October 24, 2022 6:57:52 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> Some flags and features are not supported on Windows, like mknod,
> readlink, file mode, etc. Update the codes for Windows.
>
> Signed-off-by: Guohuai Shi
> Signed-off-by: Bin Meng
> ---
>
> hw/9pfs/9p-util.h
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On 1/11/22 17:01, Bernhard Beschow wrote:
Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow :
On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé
wrote:
This is a respin of Bernhard's v4 with Freescale eSDHC implemented
as an 'UNIMP' region. See v4 cover here:
https://lore.kernel
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Tue, Nov 1, 2022 at 8:03 PM Daniel P. Berrangé wrote:
>
> On Tue, Nov 01, 2022 at 09:14:55AM +0800, Bin Meng wrote:
> > Hi Daniel,
> >
> > On Wed, Oct 26, 2022 at 12:41 AM Bin Meng wrote:
> > >
> > > On Wed, Oct 19, 2022 at 6:20 PM Bin Meng wrote:
> > > >
> > > > From: Bin Meng
> > > >
> > >
On Mon, 31 Oct 2022 11:48:58 -0400
"Michael S. Tsirkin" wrote:
> On Mon, Oct 31, 2022 at 01:50:24PM +, Daniel P. Berrangé wrote:
> > On Mon, Oct 31, 2022 at 01:19:30PM +, Daniel P. Berrangé wrote:
> > > The TCO watchdog is unconditionally integrated into the Q35 machine
> > > type by de
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On 1/11/22 14:57, Akihiko Odaki wrote:
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 20 +---
include/hw/pci/pci.h | 12 ++--
2 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index cce57f572c..41de7643af 100644
---
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
Am 1. November 2022 10:41:51 UTC schrieb Bernhard Beschow :
>On Mon, Oct 31, 2022 at 12:54 PM Philippe Mathieu-Daudé
>wrote:
>
>> This is a respin of Bernhard's v4 with Freescale eSDHC implemented
>> as an 'UNIMP' region. See v4 cover here:
>>
>> https://lore.kernel.org/qemu-devel/20221018210146.1
On 1/11/22 14:57, Akihiko Odaki wrote:
pci_add_capability() checks whether capabilities overlap, and notifies
its caller so that it can properly handle the case. However, in the
most cases, the capabilities actually never overlap, and the interface
incurred extra error handling code, which is oft
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of slotid_cap_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci/slotid_cap.c | 8 ++--
1 file changed, 2 insertions(
Sorry for late patch on this. I mentioned i will send it last week itself, but
later reliased it was festival week in India, so was mostly holidays.
Thanks
Manish Mishra
On 01/11/22 8:00 pm, manish.mishra wrote:
Current logic assumes that channel connections on the destination side are
always
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. A caller of pci_bridge_ssvid_init(), which calls
pci_add_capability() in turn, is expected to ensure that will not
happen.
Signed-off-by: Akihiko Odaki
---
hw/pci-bridge/i82801b11.c | 14 ++
h
On Monday, October 24, 2022 6:57:54 AM CET Bin Meng wrote:
> From: Guohuai Shi
>
> When using 9p2000.L protocol, the errno should use the Linux errno.
> Currently magic numbers with comments are used. Replace these with
> macros for future expansion.
>
> Signed-off-by: Guohuai Shi
> Signed-off-
Omitting errp for pci_add_capability() causes it to abort if
capabilities overlap. This behavior is appropriate here because all of
the capabilities set in this device are defined in the program and
their overlap should not happen unless there is a programming error.
Signed-off-by: Akihiko Odaki
On Tue, Nov 1, 2022 at 19:22 Jonathan Cameron
wrote:
> On Mon, 31 Oct 2022 08:51:44 -0400
> "Michael S. Tsirkin" wrote:
>
> > From: Julia Suvorova
> >
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is correct.
> >
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