On Mon, 31 Oct 2022 at 14:55, Michael S. Tsirkin wrote:
>
> On Mon, Oct 31, 2022 at 02:44:11PM +0800, Cindy Lu wrote:
> > On Mon, 31 Oct 2022 at 14:38, Michael S. Tsirkin wrote:
> > >
> > > On Mon, Oct 31, 2022 at 11:10:19AM +0800, Cindy Lu wrote:
> > > > - Move the implement vfio_get_xlat_addr t
Hi Yicong,
On 2022/10/27 11:26, Yicong Yang wrote:
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few platfo
On Mon, Oct 31, 2022 at 02:44:11PM +0800, Cindy Lu wrote:
> On Mon, 31 Oct 2022 at 14:38, Michael S. Tsirkin wrote:
> >
> > On Mon, Oct 31, 2022 at 11:10:19AM +0800, Cindy Lu wrote:
> > > - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> > > change the name to memory_get_xlat_ad
On 29/10/2022 15.45, Bin Meng wrote:
Hi Thomas,
On Wed, Sep 21, 2022 at 8:24 PM Thomas Huth wrote:
On 21/09/2022 14.18, Bin Meng wrote:
Hi,
On Thu, Sep 8, 2022 at 9:28 PM Bin Meng wrote:
At present packaging the required DLLs of QEMU executables is a
manual process, and error prone.
Imp
On Mon, 31 Oct 2022 at 14:38, Michael S. Tsirkin wrote:
>
> On Mon, Oct 31, 2022 at 11:10:19AM +0800, Cindy Lu wrote:
> > - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> > change the name to memory_get_xlat_addr(). So we can use this
> > function on other devices, such as vD
On 29/10/2022 15.06, Bin Meng wrote:
Hi Thomas,
On Sat, Sep 24, 2022 at 5:20 PM Bin Meng wrote:
Hi Thomas,
On Sat, Sep 10, 2022 at 8:32 AM Bin Meng wrote:
On Sat, Sep 10, 2022 at 12:32 AM Thomas Huth wrote:
On 08/09/2022 15.28, Bin Meng wrote:
From: Bin Meng
At present the prerequis
On Fri, Oct 28, 2022 at 09:49:36PM +0800, Yi Liu wrote:
> On 2022/10/28 14:14, Jason Wang wrote:
> > This patch introduce ECAP_PASID via "x-pasid-mode". Based on the
> > existing support for scalable mode, we need to implement the following
> > missing parts:
> >
> > 1) tag VTDAddressSpace with PA
On Mon, Oct 31, 2022 at 11:10:19AM +0800, Cindy Lu wrote:
> - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> change the name to memory_get_xlat_addr(). So we can use this
> function on other devices, such as vDPA device.
> - Add a new function vfio_get_xlat_addr in vfio/common
On Fri, Oct 21, 2022 at 3:32 PM Ani Sinha wrote:
>
> A doc file is added under docs/devel that describes the purpose of the various
> test files and gives guidance to developers on where and how to make changes.
>
> Cc: Daniel P. Berrange"
> Cc: Paolo Bonzini
> Cc: Maydell Peter
> Cc: John Snow
On 10/27/22 21:26, Richard Henderson wrote:
The helpers for reset_rf, cli, sti, clac, stac are
completely trivial; implement them inline.
Drop some nearby #if 0 code.
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 5 -
target/i386/tcg/cc_helper.c | 41 --
On 10/27/22 21:02, Richard Henderson wrote:
As per #1269, this affects NetBSD installer boot.
The problem is that one of the x86 acpi callbacks modifies
env->eip during an mmio store, which means that the tracking
that translate.c does is thrown out of whack.
Introduce a method to extract unwin
On 10/29/22 21:42, Alex Bennée wrote:
Richard Henderson writes:
Add a tcg_ops hook to replace the restore_state_to_opc
function call. Because these generic hooks cannot depend
on target-specific types, temporarily, copy the current
target_ulong data[] into uint64_t d64[].
Reviewed-by: Claud
The value passed is always true.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 2 +-
accel/tcg/tb-maint.c | 4 ++--
accel/tcg/translate-all.c | 15 +++
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/accel/tcg/i
Since 9b9c37c36439, we have only supported sparc64 cpus.
Debian and Gentoo now only support 64-bit sparc64 userland,
so it is time to drop the 32-bit sparc64 userland: sparc32plus.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/sparc/tcg
With odd_ofs set, we weren't copying enough data.
Fixes: 09eb6d7025d1 ("target/arm: Move sve zip high_ofs into simd_data")
Reported-by: Idan Horowitz
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/s
With sparc64 we need not distinguish between registers that
can hold 32-bit values and those that can hold 64-bit values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 16 +
tcg/sparc64/tcg-target-con-str.h | 3 -
tcg/sparc64/tcg-targe
Add a way to examine the unwind data without actually
restoring the data back into env.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 4 +--
include/exec/exec-all.h | 21 ---
accel/tcg/translate-all.c | 74 ++
The value passed is always true, and if the target's
synchronize_from_tb hook is non-trivial, not exiting
may be erroneous.
Reviewed-by: Claudio Fontana
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 5 +
accel/tcg/cpu-exec-common.c | 2 +-
accel/tcg/tr
Avoid cpu_restore_state, and modifying env->eip out from
underneath the translator with TARGET_TB_PCREL. There is
some slight duplication from x86_restore_state_to_opc,
but it's just a few lines.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1269
Reviewed-by: Claudio Fontana
Signed-off
The helpers for reset_rf, cli, sti, clac, stac are
completely trivial; implement them inline.
Drop some nearby #if 0 code.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/helper.h| 5 -
target/i386/tcg/cc_helper.c |
The following changes since commit 75d30fde55485b965a1168a21d016dd07b50ed32:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2022-10-30 15:07:25 -0400)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221031
for yo
Emphasize that we only support full 64-bit code generation.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
tcg/{sparc => sparc64}/tcg-target-con-set.h | 0
tcg/{sparc => sparc64}/tcg-targ
Delay cpu_list_add until realize is complete, so that cross-cpu
interaction does not happen with incomplete cpu state. For this,
we must delay plugin initialization out of tcg_exec_realizefn,
because no cpu_index has been assigned.
Fixes a problem with cross-cpu jump cache flushing, when the
jump
Since we do not plan to exit, use cpu_unwind_state_data
and extract exactly the data requested.
This is a bug fix, in that we no longer clobber dflag.
Consider:
l.j L2 // branch
l.mfspr r1, ppc// delay
L1: boom
L2: l.lwa r3, (r4)
Here, dflag woul
From: Icenowy Zheng
When registering helpers via FFI for TCI, the inner loop that iterates
parameters of the helper reuses (and thus pollutes) the same variable
used by the outer loop that iterates all helpers, thus made some helpers
unregistered.
Fix this logic error by using a dedicated tempor
We have called cpu_restore_state asserting will_exit.
Do not go back on that promise. This affects icount.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/s
qga: Add initial OpenBSD support
Signed-off-by: Brad Smith
---
meson.build | 2 +-
qga/commands-bsd.c | 5 +
qga/commands-posix.c | 9 +++--
qga/main.c | 4 ++--
4 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
index 37737913d
On Fri, 28 Oct 2022, Bernhard Beschow wrote:
> The code currently assumes Q35 iff ICH9 and i440fx iff PIIX. Now that more
> AML generation has been moved into the south bridges and since the
> machines define themselves primarily through their north bridges, let's
> switch to resolving the nort
On Mon, Oct 31, 2022 at 6:25 AM Alistair Francis wrote:
>
> On Fri, Oct 28, 2022 at 2:53 AM Anup Patel wrote:
> >
> > The time CSR will wrap-around immediately after reaching UINT64_MAX
> > so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
> > in riscv_timer_write_timecmp().
>
>
On Mon, 31 Oct 2022 11:10:19 +0800
Cindy Lu wrote:
> - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> change the name to memory_get_xlat_addr(). So we can use this
> function on other devices, such as vDPA device.
> - Add a new function vfio_get_xlat_addr in vfio/common.c, a
- Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
change the name to memory_get_xlat_addr(). So we can use this
function on other devices, such as vDPA device.
- Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check
whether the memory is backed by a discard
These patches are to support vIOMMU in vdpa device
changes in V3
1. Move function vfio_get_xlat_addr to memory.c
2. Use the existing memory listener, while the MR is
iommu MR then call the function iommu_region_add/
iommu_region_del
changes in V4
1.make the comments in vfio_get_xlat_addr more gen
Add support for vIOMMU. add the new function to deal with iommu MR.
- during iommu_region_add register a specific IOMMU notifier,
and store all notifiers in a list.
- during iommu_region_del, compare and delete the IOMMU notifier from the list
Verified in vp_vdpa and vdpa_sim_net driver
Signed-o
On Mon, 31 Oct 2022 at 10:30, Alex Williamson
wrote:
>
> On Mon, 31 Oct 2022 09:56:04 +0800
> Cindy Lu wrote:
>
> > - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> > change the name to memory_get_xlat_addr(). So we can use this
> > function on other devices, such as vDPA de
On Mon, 31 Oct 2022 09:56:04 +0800
Cindy Lu wrote:
> - Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
> change the name to memory_get_xlat_addr(). So we can use this
> function on other devices, such as vDPA device.
> - Add a new function vfio_get_xlat_addr in vfio/common.c, a
From: Axel Heider
The compare timer will never fire if the reload value is less
than the compare value, so it must be disabled in this case.
The compare time fire exactly once when the compare value is
less than the current value, but the reload values is less
than the compare value.
Signed-off-
From: Axel Heider
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 42 +++--
include/
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 23 +--
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 37b04a1b53..d21cbf16f6 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@
From: Axel Heider
- simplify code, improve comments
- fix https://gitlab.com/qemu-project/qemu/-/issues/1263
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 139 +---
1 file changed, 65 insertions(+), 74 deletions(-)
diff --git a/hw/timer/imx_epit.
From: Axel Heider
remove unused defines, add needed defines
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 4 ++--
include/hw/timer/imx_epit.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 5915d4b3d4..196f
This is a follow-up on my initial work to fix https://gitlab.com/qemu-
project/qemu/-/issues/1263.
- fix #1263 for CR writes
- fix compare timer update
- software reset clears the interrupt
- do not persist CR.SWR bit
- general code cleanup and comment improvements
Axel Heider (11):
hw/timer/imx
From: Axel Heider
---
hw/timer/imx_epit.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index d21cbf16f6..2e4ff89613 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -97,6 +97,9 @@ static void imx_epit_reset(DeviceState *dev)
s
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 2e4ff89613..bba9c87cd4 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -175,9 +175,12 @
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index bba9c87cd4..5915d4b3d4 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -198,13 +198,
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 189
1 file changed, 103 insertions(+), 86 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index b6c013292f..a79f58c963 100644
--- a/hw/timer/imx_epit.c
+++ b
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 06785fe6f6..b6c013292f 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -352,8 +352,18 @@ static void
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index ec0fa440d7..06785fe6f6 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -254,7 +254,7 @@ static v
On Mon, 31 Oct 2022 at 01:35, Alex Williamson
wrote:
>
> On Mon, 31 Oct 2022 00:45:38 +0800
> Cindy Lu wrote:
>
> > - Move the function vfio_get_xlat_addr to softmmu/memory.c, and
> > change the name to memory_get_xlat_addr(). So we can use this
> > function on other devices, such as vDPA dev
- Move the implement vfio_get_xlat_addr to softmmu/memory.c, and
change the name to memory_get_xlat_addr(). So we can use this
function on other devices, such as vDPA device.
- Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check
whether the memory is backed by a discard
These patches are to support vIOMMU in vdpa device
changes in V3
1. Move function vfio_get_xlat_addr to memory.c
2. Use the existing memory listener, while the MR is
iommu MR then call the function iommu_region_add/
iommu_region_del
changes in V4
1.make the comments in vfio_get_xlat_addr more gen
Add support for vIOMMU. add the new function to deal with iommu MR.
- during iommu_region_add register a specific IOMMU notifier,
and store all notifiers in a list.
- during iommu_region_del, compare and delete the IOMMU notifier from the list
Verified in vp_vdpa and vdpa_sim_net driver
Signed-o
On 2022/10/30 19:12, Elliot Nunn wrote:
Akihiko,
Sounds like you've done a lot of work on ui/cocoa, with the goal of
improving the experience with modern Linux guests. My goal is to improve
the experience with antiquated Mac OS 9 guests.
My patch has been only tested with recent Linux, but it
get_relocated_path() did not have error handling for PathCchSkipRoot()
because a path given to get_relocated_path() was expected to be a valid
path containing a drive letter or UNC server/share path elements on
Windows, but sometimes it turned out otherwise.
The paths passed to get_relocated_path(
On Fri, Oct 28, 2022 at 2:53 AM Anup Patel wrote:
>
> The time CSR will wrap-around immediately after reaching UINT64_MAX
> so we don't need to re-start QEMU timer when timecmp == UINT64_MAX
> in riscv_timer_write_timecmp().
I'm not clear what this is fixing?
If the guest sets a timer for UINT64
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel wrote:
>
> Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we
> should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c
> for VSTIP.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel
R
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel wrote:
>
> The htimedelta[h] CSR has impact on the VS timer comparison so we
> should call riscv_timer_write_timecmp() whenever htimedelta changes.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel
Reviewed-by: A
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel wrote:
>
> We should use "&&" instead of "&" when checking hcounteren.TM and
> henvcfg.STCE bits.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/
On 10/31/22 04:21, Philippe Mathieu-Daudé wrote:
On 30/10/22 16:45, Peter Maydell wrote:
-#define TCG_TARGET_REG_BITS 64
Why do we delete this?
We get the default definition from include/tcg/tcg.h:
58 /* Default target word size to pointer size. */
59 #ifndef TCG_TARGET_REG_BITS
6
On 10/29/22 13:00, Jiaxun Yang wrote:
As per "Loongson-2F processor user manual", CP0St_{KX, SX, UX}
should is not writeable and hardcoded to 1.
Without those bits set, kernel is unable to access XKPHYS address
segmant. So just set them up on CPU reset.
Signed-off-by: Jiaxun Yang
---
target/m
On 10/31/22 09:50, Philippe Mathieu-Daudé wrote:
6 months ago Stefan Pejic stepped in as nanoMIPS maintainer
(see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS
ISA support in QEMU"), however today his email is bouncing:
** Message blocked **
Your message tostefan.pe...@syrmia.com
On 10/29/22 13:00, Jiaxun Yang wrote:
I don't have access to Octeon68XX hardware but accroading to
my investigation Octeon never had DSP ASE support.
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have
access to a Ubiquit
On 10/29/22 11:44, Icenowy Zheng wrote:
Ah I think this is a C99 feature. Is our C standard baseline high
enough to use it?
Yes, we use C2011. See the second line of meson.build:
default_options: ... 'c_std=gnu11'
r~
On 10/31/22 02:45, Peter Maydell wrote:
+/* We only support generating code for 64-bit mode. */
+#ifndef __arch64__
+#error "unsupported code generation mode"
We might as well be more specific:
"no support for generating code for 32-bit SPARC"
(though I guess that configure ought in theory to
6 months ago Stefan Pejic stepped in as nanoMIPS maintainer
(see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS
ISA support in QEMU"), however today his email is bouncing:
** Message blocked **
Your message to stefan.pe...@syrmia.com has been blocked. See technical
details below for
From: Bernhard Beschow
PIIX3 clears its reset control register, so do the same in PIIX4.
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-28-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/is
From: Milica Lazarevic
Change enums to typedef enums to keep naming clear.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-23-milica.lazare...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé
---
disas/nanomips.cpp |
From: Bernhard Beschow
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-9-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 3 ++-
hw/ide/piix.c | 5 +++--
hw/isa/pi
From: Bernhard Beschow
Signed-off-by: Bernhard Beschow
Message-Id: <20221022150508.26830-27-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
configs/devices/mips-softmmu/common.mak | 1 -
hw/isa/Kconfig | 6 ++
2 files changed, 6 insertions(+), 1 deleti
From: Bernhard Beschow
Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-19-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 1 -
1 file changed, 1 deleti
From: Milica Lazarevic
Now that everything has been converted to C code the nanomips.cpp file
has been renamed. Therefore, meson.build file is also changed.
Signed-off-by: Milica Lazarevic
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-25-milica.lazare...@syrmia.com>
Signed-o
From: Bernhard Beschow
Fixes the "extra-semi" clang-tidy check.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-4-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix3.c | 6 +++---
1 file c
From: Jiaxun Yang
PCIe port 0 and 1 had link_up set as false previously,
that makes those two ports effectively useless. It can
be annoying for users to find that the device they plug
on those buses won't work at all.
As link_up is true by default, just don't set it again in
boston platform code
From: Bernhard Beschow
This method post-loads the southbridge, not the IDE device.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-8-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/isa/piix4.c | 4 ++--
1 file changed, 2 i
From: Milica Lazarevic
Both versions of IMMEDIATE functions have been removed.
Before this patch, we'd been calling img_format twice, the first time
through the IMMEDIATE to get an appropriate string and the second time
to print that string. There's no more need for that. Therefore, calls to
IMM
From: Bernhard Beschow
According to good QOM practice, an object should only deal with objects
of its own sub tree. Having devices create an alias on the machine
object doesn't respect this good practice. To resolve this, create the
alias in the machine's code.
Signed-off-by: Bernhard Beschow
R
From: Bernhard Beschow
Rather than registering the reset handler via a function which
appends the handler to a global list, prefer to implement it as
a virtual method - PIIX4 does the same already.
Note that this means that piix3_reset can now also be called writing to
the relevant configuration
From: Bernhard Beschow
For the VIA south bridges there was a comment to have the call in board code.
Move it there for PIIX4 as well for consistency.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-29-shen...@gmail.com>
Signed-off-by: Phili
From: Bernhard Beschow
While at it, move the assignments closer to where they are used.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-26-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/mips/malta.c | 5 ++---
1 file chan
From: Bernhard Beschow
Just like in the real hardware (and in PIIX4), create the DMA
controllers in the south bridges.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-2-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/
From: Bernhard Beschow
get_system_memory() accesses global state while pci_address_space() uses
whatever has been passed to the device instance, so avoid the global.
Moreover, PIIX4 uses pci_address_space() here as well.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Messa
From: BALATON Zoltan
Several machines have an unused MAX_IDE_BUS define. Remove it from
these machines that don't need it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20220917115136.a32ef746...@zero.eik.bme.hu>
Signed-off-by: P
From: David Daney
disas/mips.c got added in commit 6643d27ea0 ("MIPS disas support")
apparently based on binutils tag 'gdb_6_1-branchpoint' [1].
Back then, MIPSr6 was not supported (added in binutils commit
7361da2c952 during 2014 [2]).
Binutils codebase diverged so much over the last 18 years,
From: Bernhard Beschow
According to the PIIX3 datasheet, the reset control register is one byte in
size.
Moreover, PIIX4 has it, so add it to PIIX3 as well.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20221022150508.26830-5-shen...@gmail.com>
Signed-off-by
From: Milica Lazarevic
Disassemble function that calls the other variant of it is deleted.
Where it is called, now we're directly calling the other implementation.
Signed-off-by: Milica Lazarevic
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-20-milica.lazare...@syrmia.com>
S
From: Milica Lazarevic
Since there's no support for exception handling in C, the try-catch
blocks have been deleted, and throw clauses are replaced. When a runtime
error happens, we're printing out the error message. Disassembling of
the current instruction interrupts. This behavior is achieved b
From: Milica Lazarevic
g_autofree attribute is added for every dynamically allocated string to
prevent memory leaking.
The implementation of the several functions that work with dynamically
allocated strings is slightly changed so we can add those attributes.
Signed-off-by: Milica Lazarevic
Re
From: Milica Lazarevic
Replaced argument passing by reference with passing by address.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-24-milica.lazare...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé
---
disas/na
From: Milica Lazarevic
Helper methods from NMD class like NMD::renumber_registers,
NMD::decode_gpr_gpr4... etc. are removed from the class. They're now
declared global static functions.
Following helper methods have been deleted because they're not used by
the nanomips disassembler:
- NMD::encod
From: Milica Lazarevic
The following is moved from the nanomips.h to nanomips.cpp file:
- #include line
- typedefs
- enums
- definition of the Pool struct.
Header file nanomips.h will be deleted to be consistent with the rest of
the disas/ code.
Signed-off-by: Milica Lazarevic
Reviewed-by: Phil
From: Milica Lazarevic
is a C++ library and it's not used by disassembler.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-13-milica.lazare...@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé
---
disas/nanomips.cpp
From: Milica Lazarevic
CPR functions has been removed.
Before this patch, we'd been calling img_format twice, the first time
through the CPR function to get an appropriate string and the second
time to print that formatted string. There's no more need for that.
Therefore, calls to CPR are remove
From: Milica Lazarevic
Following functions just wrap the decode_gpr_gpr3() function:
- encode_rs3_and_check_rs3_ge_rt3()
- encode_rs3_and_check_rs3_lt_rt3()
Therefore those have been deleted. Calls to these two functions have
been replaced with calls to decode_gpr_gpr3.
Signed-off-by: Milica Laz
From: Milica Lazarevic
Header file nanomips.h has been deleted for the nanomips disassembler to
stay consistent with the rest of the disassemblers which don't include
extra header files.
Signed-off-by: Milica Lazarevic
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message
From: Milica Lazarevic
NMD class methods with the conditional_function type like
NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD
class. They're now declared global static functions. Therefore, typedef
of the function pointer, conditional_function is defined outside of the
From: Milica Lazarevic
Pool tables are no longer declared as static fields of the NMD
class but as global static const variables. Pool struct is defined
outside of the class.
The NMD::Disassemble method is using the MAJOR Pool table variable, so
its implementation is moved to the end of the nano
From: Milica Lazarevic
NMD class has been deleted. The following methods are now declared as
static functions:
- public NMD::Disassemble method
- private NMD::Disassemble method
- private NMD::extract_op_code_value helper method
Also, the implementation of the print_insn_nanomips function and
na
From: Bernhard Beschow
The PM controller has activity bits which monitor activity of other
built-in devices in the host device.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Daniel Henrique Barboza
Message-Id: <20220901114127.53914-10-shen...@gmail.com>
Signed-
From: Bernhard Beschow
The previous patches moved most of this function into the via-isa device
model such that it has become fairly trivial. So inline it for
simplicity.
Suggested-by: BALATON Zoltan
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <202209011141
From: Bernhard Beschow
Establishes consistency with other (VIA) devices.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Daniel Henrique Barboza
Message-Id: <20220901114127.53914-6-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/via.c
From: Milica Lazarevic
Definitions of enums TABLE_ENTRY_TYPE and TABLE_ATTRIBUTE_TYPE are moved
out of the NMD class. The main goal is to remove NMD class completely.
Signed-off-by: Milica Lazarevic
Reviewed-by: Thomas Huth
Reviewed-by: Richard Henderson
Message-Id: <20220912122635.74032-3-mi
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