On Fri, Oct 28, 2022 at 2:52 AM Anup Patel <apa...@ventanamicro.com> wrote:
>
> We should use "&&" instead of "&" when checking hcounteren.TM and
> henvcfg.STCE bits.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel <apa...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5c9a7ee287..716f9d960e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -838,7 +838,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
> }
>
> if (riscv_cpu_virt_enabled(env)) {
> - if (!(get_field(env->hcounteren, COUNTEREN_TM) &
> + if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> get_field(env->henvcfg, HENVCFG_STCE))) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> --
> 2.34.1
>
>
