Re: [PATCH] ui: remove useless typecasts

On 22/10/22 16:12, Volker Rümelin wrote: Commit 8f9abdf586 ("chardev: src buffer const for write functions") changed the type of the second parameter of qemu_chr_be_write() from uint8_t * to const uint8_t *. Remove the now useless type casts from qemu_chr_be_write() function calls in ui/console.c

Re: [PATCH v2 21/43] hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4

On 22/10/22 17:04, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PATCH 14/16] hw/9pfs: Update synth fs driver for Windows

From: Guohuai Shi Adapt synth fs driver for Windows in preparation to running qtest 9p testing on Windows. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- hw/9pfs/9p-synth.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/9pfs/9p-synth.c b/hw/9pfs/9p-synth.c

[PATCH 15/16] tests/qtest: virtio-9p-test: Adapt the case for win32

From: Guohuai Shi Windows does not provide the getuid() API. Let's create a local one and return a fixed value 0 as the uid for testing. Signed-off-by: Guohuai Shi Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- tests/qtest/virtio-9p-test.c | 7 +++ 1 file changed, 7 insertions(

Re: [PATCH] accel/tcg/tcg-accel-ops-rr: fix trivial typo

On 21/10/22 19:36, Matheus Tavares Bernardino wrote: Signed-off-by: Matheus Tavares Bernardino --- accel/tcg/tcg-accel-ops-rr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v2] vhost-vdpa: add support for vIOMMU

On Thu, 20 Oct 2022 at 10:15, Jason Wang wrote: > > On Wed, Oct 19, 2022 at 2:39 PM Cindy Lu wrote: > > > > Add support for vIOMMU. Register a memory listener to dma_as in > > dev_start > > - during region_add register a specific IOMMU notifier, and store all > > notifiers in a list. > > - durin

[PATCH v6 05/14] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw

Separate S1 translation from the actual lookup. Will enable lpae hardware updates. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 41 ++--- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/target/arm/ptw.c b/

Re: [PATCH v2 23/43] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"

On 22/10/22 17:04, Bernhard Beschow wrote: The additional prefix aligns the function name with both other piix3-internal functions as well as QEMU conventions. Furthermore, it will help to distinguish the function from its PIIX4 counterpart once merged. Signed-off-by: Bernhard Beschow --- hw/

[PATCH v6 07/14] target/arm: Remove loop from get_phys_addr_lpae

The unconditional loop was used both to iterate over levels and to control parsing of attributes. Use an explicit goto in both cases. While this appears less clean for iterating over levels, we will need to jump back into the middle of this loop for atomic updates, which is even uglier. Reviewed

[PATCH v6 04/14] target/arm: Extract HA and HD in aa64_va_parameters

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c| 8 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2b6889073d..16d7989604 100644 --- a/target/arm/i

[PATCH v6 13/14] target/arm: Implement FEAT_HAFDBS, dirty bit portion

Perform the atomic update for hardware management of the dirty bit. Signed-off-by: Richard Henderson --- v5: Move the DB update before attributes are extracted and merged. --- target/arm/cpu64.c | 2 +- target/arm/ptw.c | 16 2 files changed, 17 insertions(+), 1 deletion(-)

[PATCH 11/16] hw/9pfs: Add Linux error number definition

From: Guohuai Shi When using 9p2000.L protocol, the errno should use the Linux errno. Currently magic numbers with comments are used. Replace these with macros for future expansion. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- hw/9pfs/9p-linux-errno.h | 151

[PATCH 1/1] tcg/riscv: Fix base regsiter for qemu_ld/st

When guest base is zero, we should use addr_regl as base regiser instead of the initial register TCG_REG_TMP0. Besides, we can remove the unnecessary use of base register. Signed-off-by: LIU Zhiwei --- tcg/riscv/tcg-target.c.inc | 20 1 file changed, 8 insertions(+), 12 dele

Re: [RFC PATCH v2 2/8] vdpa: Save emulated features list in vhost_vdpa

On Fri, Oct 21, 2022 at 4:56 PM Eugenio Perez Martin wrote: > > On Fri, Oct 21, 2022 at 4:57 AM Jason Wang wrote: > > > > On Thu, Oct 20, 2022 at 2:34 PM Eugenio Perez Martin > > wrote: > > > > > > On Thu, Oct 20, 2022 at 6:23 AM Jason Wang wrote: > > > > > > > > On Wed, Oct 19, 2022 at 8:52 PM

[PATCH 06/16] hw/9pfs: Add missing definitions for Windows

From: Guohuai Shi Some definitions currently used by the 9pfs codes are only available on POSIX platforms. Let's add our own ones in preparation to adding 9pfs support for Windows. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- fsdev/file-op-9p.h | 33

[PATCH v6 14/14] target/arm: Use the max page size in a 2-stage ptw

We had only been reporting the stage2 page size. This causes problems if stage1 is using a larger page size (16k, 2M, etc), but stage2 is using a smaller page size, because cputlb does not set large_page_{addr,mask} properly. Fix by using the max of the two page sizes. Reported-by: Marc Zyngier

[PATCH 03/16] hw/9pfs: Replace the direct call to xxxat() APIs with a wrapper

xxxat() APIs are only available on POSIX platforms. For future extension to Windows, let's replace the direct call to xxxat() APIs with a wrapper. Signed-off-by: Bin Meng --- hw/9pfs/9p-util.h | 15 +++ hw/9pfs/9p-local.c | 32 2 files changed, 27 i

[PATCH v6 6/7] hw/arm/virt: Add 'compact-highmem' property

After the improvement to high memory region address assignment is applied, the memory layout can be changed, introducing possible migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region is disabled or enabled when the optimization is applied or not, with the following configuration. The

[PATCH v6 01/14] target/arm: Introduce regime_is_stage2

Reduce the amount of typing required for this check. Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 + target/arm/helper.c| 14 +- target/arm/ptw.c | 14 ++ 3 files changed, 16

[PATCH v6 2/7] hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()

This renames variable 'size' to 'region_size' in virt_set_high_memmap(). Its counterpart ('region_base') will be introduced in next patch. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Tested-by: Zhenyu Zhang --- hw/arm/virt.c | 1

Re: [PATCH v2 19/43] hw/isa/piix3: Allow board to provide PCI interrupt routes

On 22/10/22 17:04, Bernhard Beschow wrote: PIIX3 initializes the PIRQx route control registers to the default values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4) April 1997 manual. PIIX4, however, initializes the routes according to the Malta™ User’s Manual, ch 6.6, which are IRQ

[PATCH v6 3/7] hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()

This introduces variable 'region_base' for the base address of the specific high memory region. It's the preparatory work to optimize high memory region address assignment. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Tested-by: Zh

Re: [PATCH v5 01/14] target/arm: Introduce regime_is_stage2

Richard Henderson writes: > Reduce the amount of typing required for this check. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée -- Alex Bennée

[PATCH v6 08/14] target/arm: Fix fault reporting in get_phys_addr_lpae

Always overriding fi->type was incorrect, as we would not properly propagate the fault type from S1_ptw_translate, or arm_ldq_ptw. Simplify things by providing a new label for a translation fault. For other faults, store into fi directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderso

Re: [PATCH v2] vhost-vdpa: add support for vIOMMU

On Mon, 24 Oct 2022 at 09:51, Jason Wang wrote: > > On Sun, Oct 23, 2022 at 10:46 PM Cindy Lu wrote: > > > > On Thu, 20 Oct 2022 at 10:15, Jason Wang wrote: > > > > > > On Wed, Oct 19, 2022 at 2:39 PM Cindy Lu wrote: > > > > > > > > Add support for vIOMMU. Register a memory listener to dma_as i

[PATCH v6 12/14] target/arm: Implement FEAT_HAFDBS, access flag portion

Perform the atomic update for hardware management of the access flag. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Raise permission fault if pte read-only and atomic update reqd. Split out dirty bit portion. Prepare for a single update for AF + DB. v5: Fix s1ns typ

[PATCH 12/16] hw/9pfs: Translate Windows errno to Linux value

From: Guohuai Shi Some of Windows error numbers have different value from Linux ones. For example, ENOTEMPTY is defined to 39 in Linux, but is defined to 41 in Windows. So deleting a directory from a Linux guest on top of QEMU from a Windows host complains: # rmdir tmp rmdir: 'tmp': Unknown

[PATCH 01/16] qemu/xattr.h: Exclude for Windows

Windows does not have . Signed-off-by: Bin Meng --- include/qemu/xattr.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/qemu/xattr.h b/include/qemu/xattr.h index f1d0f7be74..b08a934acc 100644 --- a/include/qemu/xattr.h +++ b/include/qemu/xattr.h @@ -25,7 +25,9 @@

[PATCH v6 06/14] target/arm: Add ARMFault_UnsuppAtomicUpdate

This fault type is to be used with FEAT_HAFDBS when the guest enables hw updates, but places the tables in memory where atomic updates are unsupported. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 4 1 file changed, 4 insertions(+) diff --git a/

[PATCH v6 11/14] target/arm: Tidy merging of attributes from descriptor and table

Replace some gotos with some nested if statements. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 34 -- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8004ca86df..282828992e 100644 --- a/target/a

Re: [PATCH v3 1/2] hw/registerfields: add `FIELDx_1CLEAR()` macro

On Mon, Oct 17, 2022 at 3:59 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Adds a helper macro that implements the register `w1c` > functionality. > > Ex: > uint32_t data = FIELD32_1CLEAR(val, REG, FIELD); > > If ANY bits of the specified `FIELD` is set > then the respective field is

Re: [PATCH v2 37/43] hw/isa/piix: Harmonize names of reset control memory regions

On 22/10/22 17:05, Bernhard Beschow wrote: There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-b

[PATCH v6 10/14] target/arm: Consider GP an attribute in get_phys_addr_lpae

Both GP and DBM are in the upper attribute block. Extend the computation of attrs to include them, then simplify the setting of guarded. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++ 1 file changed, 2 insertions

[PATCH v6 03/14] target/arm: Add isar predicates for FEAT_HAFDBS

The MMFR1 field may indicate support for hardware update of access flag alone, or access flag and dirty bit. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index

Re: [PATCH v2 22/43] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4

On 22/10/22 17:04, Bernhard Beschow wrote: Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] ui: remove useless typecasts

Volker Rümelin writes: > Commit 8f9abdf586 ("chardev: src buffer const for write functions") > changed the type of the second parameter of qemu_chr_be_write() > from uint8_t * to const uint8_t *. Remove the now useless type > casts from qemu_chr_be_write() function calls in ui/console.c and > ui/

[PATCH 08/16] hw/9pfs: Handle current directory offset for Windows

From: Guohuai Shi On Windows 'struct dirent' does not have current directory offset. We have to save current directory offset and update offset when reading directory. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- hw/9pfs/9p.c| 16 hw/9pfs/codir.c | 15 +

[PATCH v2 23/43] hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"

The additional prefix aligns the function name with both other piix3-internal functions as well as QEMU conventions. Furthermore, it will help to distinguish the function from its PIIX4 counterpart once merged. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insert

[PATCH 02/16] hw/9pfs: Drop unnecessary *xattr wrapper API declarations

These are not used anywhere in the source tree. Drop them. Signed-off-by: Bin Meng --- hw/9pfs/9p-util.h | 11 --- 1 file changed, 11 deletions(-) diff --git a/hw/9pfs/9p-util.h b/hw/9pfs/9p-util.h index c3526144c9..ccfc8b1cb3 100644 --- a/hw/9pfs/9p-util.h +++ b/hw/9pfs/9p-util.h @@ -

[PATCH v6 00/14] target/arm: Implement FEAT_HAFDBS

Changes for v6: * Fix rebase error wrt xn bit extract. Changes for v5: * Rebase, including 12 patches. * Add regime_is_stage2, which I should have done ages ago. * Reorg attribute extraction/merging vs descriptor modifications. Patches lacking review: 02-target-arm-Add-ptw_idx-to-S1Tran

Re: [PATCH v4] m68k: write bootinfo as rom section and re-randomize on reboot

On Sat, Oct 22, 2022 at 8:41 AM Richard Henderson wrote: > > On Sat, 22 Oct 2022, 08:33 Laurent Vivier, wrote: >> >> Le 17/10/2022 à 22:29, Jason A. Donenfeld a écrit : >> >> >> Notes: >> - don't send your patch as a reply to a previous version >> - add an history: >> >> v4: replace (void *)(((u

Re: [PATCH v2 34/43] hw/isa/piix4: Rename reset control operations to match PIIX3

On 22/10/22 17:04, Bernhard Beschow wrote: Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PATCH 10/16] hw/9pfs: Update the local fs driver to support Windows

From: Guohuai Shi At present there is no Windows support for 9p file system. This commit adds initial Windows support for 9p file system. 'local' file system backend driver is supported on Windows, including open, read, write, close, rename, remove, etc. All security models are supported. The ma

[PATCH v6 4/7] hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper

This introduces virt_get_high_memmap_enabled() helper, which returns the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will be used in the subsequent patches. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: Eric Auger Reviewed-by: Cornelia Huck Tested-by: Zhe

Re: [PATCH v2 24/43] hw/isa/piix3: Rename typedef PIIX3State to PIIXState

On 22/10/22 17:04, Bernhard Beschow wrote: This commit marks the finalization of the PIIX3 preparations to be merged with PIIX4. In particular, PIIXState is prepared to be reused in piix4.c. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c| 58 +--

Re: [PATCH v3 0/2] implement `FIELDx_1CLEAR() macro

On Mon, Oct 17, 2022 at 3:52 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > This patch series implements a `FIELDx_1CLEAR()` macro and implements it > in the `hw/ssi/ibex_spi.c` model. > > *** Changelog *** > Since v2: > - change the macro arguments name to ma

Re: [PATCH v4 0/7] ppc/e500: Add support for two types of flash, cleanup

Am 18. Oktober 2022 21:01:39 UTC schrieb Bernhard Beschow : >Cover letter: > >~ > > > >This series adds support for -pflash and direct SD card access to the > >PPC e500 boards. The idea is to increase compatibility with "real" firmware > >images where only the bare minimum of drivers is

Re: [PATCH 3/3] Drop more useless casts from void * to pointer

Le 23/09/2022 à 14:00, Markus Armbruster a écrit : Signed-off-by: Markus Armbruster --- bsd-user/elfload.c | 2 +- contrib/plugins/cache.c | 8 contrib/vhost-user-blk/vhost-user-blk.c | 2 +- hw/core/qdev-clock.c| 2 +- hw/h

[PATCH v2 41/43] hw/isa/piix: Share PIIX3 base class with PIIX4

Having a common base class allows for substituting PIIX3 with PIIX4 and vice versa. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface. Signed-off-by: Bernhard Beschow --- hw/isa/piix.c | 53 +++ 1 file changed, 24 insertions(+), 29 dele

[PATCH v6 0/7] hw/arm/virt: Improve address assignment for high memory regions

There are three high memory regions, which are VIRT_HIGH_REDIST2, VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses are floating on highest RAM address. However, they can be disabled in several cases. (1) One specific high memory region is disabled by developer by toggling vms-

[PATCH v4 1/2] Refactoring: refactor TFR() macro to RETRY_ON_EINTR()

Rename macro name to more transparent one and refactor it to expression. Signed-off-by: Nikita Ivanov --- chardev/char-fd.c | 2 +- chardev/char-pipe.c| 8 +--- include/qemu/osdep.h | 8 +++- net/tap-bsd.c | 6 +++--- net/tap-linux.c| 2 +- net/tap-solaris.c

[PATCH v6 09/14] target/arm: Don't shift attrs in get_phys_addr_lpae

Leave the upper and lower attributes in the place they originate from in the descriptor. Shifting them around is confusing, since one cannot read the bit numbers out of the manual. Also, new attributes have been added which would alter the shifts. Reviewed-by: Peter Maydell Signed-off-by: Richa

Re: [RFC PATCH v2 6/8] vdpa: handle VIRTIO_NET_CTRL_ANNOUNCE in vhost_vdpa_net_handle_ctrl_avail

On Fri, Oct 21, 2022 at 5:05 PM Eugenio Perez Martin wrote: > > On Fri, Oct 21, 2022 at 5:02 AM Jason Wang wrote: > > > > On Thu, Oct 20, 2022 at 3:01 PM Eugenio Perez Martin > > wrote: > > > > > > On Thu, Oct 20, 2022 at 6:35 AM Jason Wang wrote: > > > > > > > > On Wed, Oct 19, 2022 at 8:52 PM

[PATCH 13/16] fsdev: Disable proxy fs driver on Windows

From: Guohuai Shi We don't plan to support 'proxy' file system driver for 9pfs on Windows. Disable it for Windows build. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- fsdev/qemu-fsdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fsdev/qemu-fsdev.c b/fsdev/qemu-fsdev.c ind

[PATCH v6 02/14] target/arm: Add ptw_idx to S1Translate

Hoist the computation of the mmu_idx for the ptw up to get_phys_addr_with_struct and get_phys_addr_twostage. This removes the duplicate check for stage2 disabled from the middle of the walk, performing it only once. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 71 +

[PATCH 04/16] hw/9pfs: Introduce an opaque type 9P_FILE_ID

Introduce an opaque type to represent a file in the 9pfs. This is file descriptor on POSIX systems. In the upcoming patches, we can extend it to support Windows. With this new opaque type, it significantly reduces the number of deviated code paths when adding Windows support. Signed-off-by: Bin M

Re: [PATCH v2 25/43] hw/mips/malta: Reuse dev variable

On 22/10/22 17:04, Bernhard Beschow wrote: While at it, move the assignments closer to where they are used. Signed-off-by: Bernhard Beschow --- hw/mips/malta.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

[PATCH 00/16] hw/9pfs: Add 9pfs support for Windows

At present there is no Windows support for 9p file system. This series adds initial Windows support for 9p file system. 'local' file system backend driver is supported on Windows, including open, read, write, close, rename, remove, etc. All security models are supported. The mapped (mapped-xattr)

[PATCH 07/16] hw/9pfs: Implement Windows specific utilities functions for 9pfs

From: Guohuai Shi Windows POSIX API and MinGW library do not provide the NO_FOLLOW flag, and do not allow opening a directory by POSIX open(). This causes all xxx_at() functions cannot work directly. However, we can provide Windows handle based functions to emulate xxx_at() functions (e.g.: opena

[PATCH v6 1/7] hw/arm/virt: Introduce virt_set_high_memmap() helper

This introduces virt_set_high_memmap() helper. The logic of high memory region address assignment is moved to the helper. The intention is to make the subsequent optimization for high memory region address assignment easier. No functional change intended. Signed-off-by: Gavin Shan Reviewed-by: E

[OUTREACHY] Asking about contribution ideas

Hi team, I am an outreachy applicant and I would like to know how I can make my first contribution and what the contribution should be. Best Regards, Wilberforce

[PATCH 16/16] meson.build: Turn on virtfs for Windows

From: Guohuai Shi Enable virtfs configuration option for Windows host. Signed-off-by: Guohuai Shi Signed-off-by: Bin Meng --- meson.build | 10 +- fsdev/meson.build | 1 + hw/9pfs/meson.build | 8 +--- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/m

[PATCH 05/16] hw/9pfs: Update P9_FILE_ID to support Windows

On Windows P9_FILE_ID points to a file handle. Signed-off-by: Bin Meng --- hw/9pfs/9p-file-id.h | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/9pfs/9p-file-id.h b/hw/9pfs/9p-file-id.h index 60cbfbf4dd..00903048e6 100644 --- a/hw/9pfs/9p-file-id.h +++ b/hw/9pfs/

[PATCH v4 0/2] Refactoring: expand usage of TFR() macro

At the moment, TFR() macro has a vague name and is not used where it possibly could be. In order to make it more transparent and useful, it was decided to refactor it to make it closer to the similar one in glibc: TEMP_FAILURE_RETRY(). Now, macro evaluates into an expression and is named RETRY_ON_E

[PATCH v6 5/7] hw/arm/virt: Improve high memory region address assignment

There are three high memory regions, which are VIRT_HIGH_REDIST2, VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses are floating on highest RAM address. However, they can be disabled in several cases. (1) One specific high memory region is likely to be disabled by code by toggl

Re: [PATCH v12 6/7] qemu-iotests: test new zone operations

On Tue, 2022-10-18 at 16:41 +0800, Sam Li wrote: > Dmitry Fomichev 于2022年10月17日周一 08:57写道： > > > > On Sun, 2022-10-16 at 22:51 +0800, Sam Li wrote: > > > We have added new block layer APIs of zoned block devices. > > > Test it with: > > > Create a null_blk device, run each zone operation on it an

Re: [PATCH] target/riscv: Fix PMP propagation for tlb

On Wed, Oct 12, 2022 at 4:01 PM LIU Zhiwei wrote: > > Only the pmp index that be checked by pmp_hart_has_privs can be used > by pmp_get_tlb_size to avoid an error pmp index. > > Before modification, we may use an error pmp index. For example, > we check address 0x4fc, and the size 0x4 in pmp_hart_

Re: [PATCH v2] vhost-vdpa: add support for vIOMMU

On Sun, Oct 23, 2022 at 10:46 PM Cindy Lu wrote: > > On Thu, 20 Oct 2022 at 10:15, Jason Wang wrote: > > > > On Wed, Oct 19, 2022 at 2:39 PM Cindy Lu wrote: > > > > > > Add support for vIOMMU. Register a memory listener to dma_as in > > > dev_start > > > - during region_add register a specific I

Re: [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits

On Sat, Oct 22, 2022 at 22:15 Michael S. Tsirkin wrote: > On Fri, Oct 21, 2022 at 09:47:04PM +0530, Ani Sinha wrote: > > > > > > On Fri, Oct 21, 2022 at 21:36 Alex Bennée > wrote: > > > > > > Ani Sinha writes: > > > > > > > > > > We have added a mirror of biosbits to the QEMU

Re: [PATCH v7 1/8] ppc440_uc.c: Move DDR2 SDRAM controller model to ppc4xx_sdram.c

On 10/21/22 21:09, BALATON Zoltan wrote: On Fri, 21 Oct 2022, Daniel Henrique Barboza wrote: diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c new file mode 100644 index 00..b49a7ed60a --- /dev/null +++ b/hw/ppc/ppc4xx_sdram.c @@ -0,0 +1,348 @@ +/* + * DDR2 SDRAM controller:

[PATCH v5] m68k: write bootinfo as rom section and re-randomize on reboot

Rather than poking directly into RAM, add the bootinfo block as a proper ROM, so that it's restored when rebooting the system. This way, if the guest corrupts any of the bootinfo items, but then tries to reboot, it'll still be restored back to normal as expected. Then, since the RNG seed needs to

[PATCH v2 08/43] hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers

Suggested-by: Mark Cave-Ayland Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 3 ++- hw/ide/piix.c | 5 +++-- hw/isa/piix4.c| 3 ++- include/hw/ide/piix.h | 7 +++ 4 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 include/hw/ide/piix.h diff -

Re: [PATCH v4 1/7] target/arm: Don't add all MIDR aliases for cores that immplement PMSA

On 10/24/22 01:36, tobias.roeh...@rwth-aachen.de wrote: From: Tobias Röhmel Typo "implement" in subject. @@ -8038,6 +8035,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn = access_aa64_tid1, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },

Re: [PATCH v3 2/2] hw/ssi/ibex_spi: implement `FIELD32_1CLEAR` macro

On Mon, Oct 17, 2022 at 3:55 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > use the `FIELD32_1CLEAR` macro to implement register > `rw1c` functionality to `ibex_spi`. > > This change was tested by running the `SPI_HOST` from TockOS. > > Signed-off-by: Wilfred Mallawa Reviewed-by: Alist

[PATCH] tests/tcg/nios2: Tweak 10m50-ghrd.ld

More closely follow the default linker script for nios2. This magically fixes a problem resolving .got relocs from the toolchain's libgcc.a. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1258 Signed-off-by: Richard Henderson --- tests/tcg/nios2/10m50-ghrd.ld | 14 +- 1 file

Re: [PATCH v2 1/2] tests/qtest: migration-test: Fix [-Werror=format-overflow=] build warning

Le 17/10/2022 à 15:20, Bin Meng a écrit : From: Bin Meng When tmpfs is NULL, a build warning is seen with GCC 9.3.0. It's strange that GCC 11.2.0 on Ubuntu 22.04 does not catch this, neither did the QEMU CI. While we are here, improve the error message as well. Reported-by: Shengjiang Wu Fix

[PATCH v2 15/43] hw/isa/piix3: Create ISA PIC in host device

Use the newly introduced i8259 proxy "isa-pic" which allows for wiring up devices in the southbridge where the virtualization technology used (KVM, TCG, Xen) is not yet known. Signed-off-by: Bernhard Beschow --- hw/i386/pc_piix.c | 15 +-- hw/isa/Kconfig|

Re: [PATCH v2] target/i386: Fix caculation of LOCK NEG eflags

Typo "calculation" in subject. On 22/10/22 08:12, Qi Hu wrote: In sequence: --- lock negl -0x14(%rbp) pushf pop%rax --- %rax will obtain the wrong value becasue the "lock neg" caculates the wrong eflags. The "s->T0" is updated by the wrong value. You can use this to do some test: --- #incl

[PATCH v2] hw/mem/nvdimm: fix error message for 'unarmed' flag

In the ACPI specification [1], the 'unarmed' bit is set when a device cannot accept a persistent write. This means that when a memdev is read-only, the 'unarmed' flag must be turned on. The logic is correct, just changing the error message. [1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM Sta

Re: [PATCH] target/riscv: Fix PMP propagation for tlb

On Wed, Oct 12, 2022 at 4:01 PM LIU Zhiwei wrote: > > Only the pmp index that be checked by pmp_hart_has_privs can be used > by pmp_get_tlb_size to avoid an error pmp index. > > Before modification, we may use an error pmp index. For example, > we check address 0x4fc, and the size 0x4 in pmp_hart_

[PATCH v6 7/7] hw/arm/virt: Add properties to disable high memory regions

These 3 high memory regions are usually enabled by default, but they may be not used. For example, VIRT_HIGH_GIC_REDIST2 isn't needed by GICv2. This leads to waste in the PA space. Add properties to allow users selectively disable them if needed: "highmem-redists", "highmem-ecam", "highmem-mmio".

Re: [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits

On Sat, Oct 22, 2022 at 22:11 Michael S. Tsirkin wrote: > On Fri, Oct 21, 2022 at 05:12:07PM +0530, Ani Sinha wrote: > > > > > > On Fri, Oct 21, 2022 at 13:50 Michael S. Tsirkin wrote: > > > > On Fri, Oct 21, 2022 at 05:10:43AM +0530, Ani Sinha wrote: > > > > > > > > > On Fri, Oc

[PATCH v2 02/43] hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge

The next patches will need to take advantage of it. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell --- hw/i386/pc_piix.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 7a55b9ca8e..5caef9bfc9 100644 --- a/hw/i386/pc_p

Re: [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits

On Sat, Oct 22, 2022 at 22:05 Michael S. Tsirkin wrote: > On Sat, Oct 22, 2022 at 06:28:32AM +0530, Ani Sinha wrote: > > > > > > On Fri, Oct 21, 2022 at 21:32 Alex Bennée > wrote: > > > > > > Ani Sinha writes: > > > > > On Fri, 21 Oct, 2022, 5:52 pm Ani Sinha, wrote: > > > > >

Re: [PATCH 2/4] vhost: toggle device callbacks using used event idx

On Fri, Oct 21, 2022 at 4:15 PM Michael S. Tsirkin wrote: > > On Fri, Oct 21, 2022 at 09:45:14AM +0200, Eugenio Perez Martin wrote: > > On Fri, Oct 21, 2022 at 5:40 AM Jason Wang wrote: > > > > > > On Thu, Oct 20, 2022 at 11:53 PM Eugenio Pérez > > > wrote: > > > > > > > > Actually use the new

Re: [PATCH v4 0/3] PowerPC interrupt rework

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 10/21/22 11:21, Matheus Ferst wrote: This version fixes the problems found by Daniel with e500 tests and rebases on ppc-next. Based-on: https://gitlab.com/danielhb/qemu/-/tree/ppc-next Matheus Ferst (3): target/ppc: intro

[PATCH v4 2/2] error handling: Use RETRY_ON_EINTR() macro where applicable

There is a defined RETRY_ON_EINTR() macro in qemu/osdep.h which handles the same while loop. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/415 Signed-off-by: Nikita Ivanov --- block/file-posix.c| 37 - chardev/char-pty.c| 4 +--- hw/

Re: [PATCH 0/3] Drop useless casts from void * to pointer

Le 20/10/2022 à 14:12, Markus Armbruster a écrit : Could this go via qemu-trivial now? Yes, sorry for the delay. I think there is a problem with PATCH 3. Thanks, Laurent

[PATCH v2 33/43] hw/isa/piix4: Reuse struct PIIXState from PIIX3

Now that PIIX4 also uses the "isa-pic" proxy, both implementations can share the same struct. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 61 -- 1 file changed, 19 insertions(+), 42 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.

[PATCH v2 34/43] hw/isa/piix4: Rename reset control operations to match PIIX3

Both implementations are the same and will be shared upon merging. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a7d52c5294..2f5b6fc934 100644 --- a/hw/isa/piix4.c +++ b/hw

[PATCH v2 32/43] hw/isa/piix4: Use ISA PIC device

Aligns the code with PIIX3 such that PIIXState can be used in PIIX4, too. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 28 ++-- hw/mips/malta.c | 11 +-- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c inde

[PATCH v2 29/43] hw/isa/piix4: Make PIIX4's ACPI and USB functions optional

This aligns PIIX4 with PIIX3. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 44 hw/mips/malta.c | 6 -- 2 files changed, 36 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a7389ff193..fc698c23be 100644 -

[PATCH v4 2/7] target/arm: Make RVBAR available for all ARMv8 CPUs

From: Tobias Röhmel RVBAR shadows RVBAR_ELx where x is the highest exception level if the highest EL is not EL3. This patch also allows ARMv8 CPUs to change the reset address with the rvbar property. Signed-off-by: Tobias Röhmel --- target/arm/cpu.c| 6 +- target/arm/helper.c | 23 +++

Re: [PATCH v6 00/10] Introduce new acpi/smbios avocado tests using biosbits

On Fri, Oct 21, 2022 at 09:47:04PM +0530, Ani Sinha wrote: > > > On Fri, Oct 21, 2022 at 21:36 Alex Bennée wrote: > > > Ani Sinha writes: > > > > > >  We have added a mirror of biosbits to the QEMU project so there is no > >  reason why we can't track changes and modific

[PATCH] tcg/riscv: Fix base register for user-only qemu_ld/st

When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set b

[PATCH v2 03/43] hw/isa/piix3: Remove extra ';' outside of functions

Fixes the "extra-semi" clang-tidy check. Signed-off-by: Bernhard Beschow Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/isa/piix3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 44a9998752..04895ce2e5 1006

[PATCH v2 22/43] hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4

Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 8dbf22eaab..5214a75891 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -156,7 +156,7 @@ static void piix3_write_config_xen(PCIDevice

Re: [PATCH v2 18/43] hw/isa/piix3: Remove unused include

On 22/10/22 17:04, Bernhard Beschow wrote: Ammends commit 988fb613215993dd0ce642b89ca8182c479d39dd. Signed-off-by: Bernhard Beschow --- hw/isa/piix3.c | 1 - 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH] vmstate-static-checker:remove this redundant return

Le 28/09/2022 à 11:03, dinglimin a écrit : Jump statements, such as return and continue let you change the default flow of program execution, but jump statements that direct the control flow to the original direction are just a waste of keystrokes. Signed-off-by: dinglimin --- scripts/vmstate

Re: [RFC PATCH] contrib/plugins: enable debug on CONFIG_DEBUG_TCG

On 21/10/22 17:51, Alex Bennée wrote: We used to rely on QEMU_CFLAGS to expose the debug flags but now this is synthesised by meson and only available to the main build. Add our own flags if we detect the build has been enabled with CONFIG_DEBUG_TCG (which is the default for --enable-debug anyway

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