Re: [PATCH v2 19/43] hw/isa/piix3: Allow board to provide PCI interrupt routes

[Philippe Mathieu-Daudé]

On 22/10/22 17:04, Bernhard Beschow wrote:

PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are IRQs 10 and 11. In order to
allow the reset methods to be consolidated, allow board code to specify
the routes.

Signed-off-by: Bernhard Beschow <shen...@gmail.com>
---
  hw/isa/piix3.c                | 12 ++++++++----
  include/hw/southbridge/piix.h |  1 +
  2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 1f22eb1444..df3e0084c5 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -54,6 +54,7 @@ struct PIIXState {

/* This member isn't used. Just for save/load compatibility */

      int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+    uint8_t pci_irq_reset_mappings[PIIX_NUM_PIRQS];

pci_irq_reset_mappings[PCI_NUM_PINS]?

ISAPICState pic;

      RTCState rtc;