On Thu, Oct 20, 2022 at 6:30 AM Jason Wang wrote:
>
> On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
> >
> > At this moment this code path is not reached, but vdpa devices can offer
> > VIRTIO_NET_F_STATUS unconditionally.
>
> So I guess what you mean is that, for the parent that doesn't su
On Thu, Oct 20, 2022 at 6:23 AM Jason Wang wrote:
>
> On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
> >
> > At this moment only _F_LOG is added there.
> >
> > However future patches add features that depend on the kind of device.
> > In particular, only net devices can add VIRTIO_F_GUEST_A
On 19/10/2022 14.56, Christian Borntraeger wrote:
Ilya has volunteered to review TCG patches for s390x.
Signed-off-by: Christian Borntraeger
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3d5b7e09c46..ae5e8c8ecbb6 100644
--- a/MAINTAINERS
"Christian A. Ehrhardt" writes:
> Fix memset argument order: The second argument is
> the value, the length goes last.
Impact of the bug?
> Cc: Eric DeVolder
> Cc: qemu-sta...@nongnu.org
> Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature")
> Signed-off-by: Christian A. Ehrhardt
>
> In the ACPI specification [1], the 'unarmed' bit is set when a device
> cannot accept a persistent write. This means that when a memdev is
> read-only, the 'unarmed' flag must be turned on. The logic is correct,
> just changing the error message.
>
> [1] ACPI NFIT NVDIMM Region Mapping Structure
On 10/12/22 01:18, Gavin Shan wrote:
> This introduces virt_get_high_memmap_enabled() helper, which returns
> the pointer to vms->highmem_{redists, ecam, mmio}. The pointer will
> be used in the subsequent patches.
>
> No functional change intended.
>
> Signed-off-by: Gavin Shan
> Tested-by: Zh
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> Temporal, as this affects other vhost backends and we must check status
> feature first.
>
> Signed-off-by: Eugenio Pérez
> ---
> hw/net/vhost_net.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/net/vhost_net.c b/hw/n
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> Since this capability is emulated by qemu shadowed CVQ cannot forward it
> to the device.
I wonder what happens for a device that has GUEST_ANNOUNCE support on its own?
> Process all that command within qemu.
>
> Signed-off-by: Eugenio Pér
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> The guest will see undefined behavior if it issue not negotiate
> commands, bit it is expected somehow.
>
> Simplify code deleting this check.
>
> Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
> ---
> net/vhost-vdpa.c | 48 -
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> At this moment this code path is not reached, but vdpa devices can offer
> VIRTIO_NET_F_STATUS unconditionally.
So I guess what you mean is that, for the parent that doesn't support
VIRTIO_NET_F_STATUS, emulate one for making sure the ANNOU
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> A gratuitous ARP is recommended after a live migration to reduce the amount of
> time needed by the network links to be aware of the new location.
A question: I think we need to deal with the case when GUSET_ANNOUNCE
is not negotiated? E.d
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> At this moment only _F_LOG is added there.
>
> However future patches add features that depend on the kind of device.
> In particular, only net devices can add VIRTIO_F_GUEST_ANNOUNCE. So
> let's allow vhost_vdpa creator to set custom emulat
On Fri, Oct 14, 2022 at 9:20 PM Laurent Vivier wrote:
>
> When virtio_net_flush_tx() reaches the tx_burst value all
> the queue is not flushed and nothing restart the timer.
>
> Fix that by doing for TX timer as we do for bottom half TX:
> rearming the timer if we find any packet to send during th
On Wed, Oct 19, 2022 at 8:52 PM Eugenio Pérez wrote:
>
> This entry was duplicated on referenced commit. Removing it.
>
> Fixes: 402378407dbd ("vhost-vdpa: multiqueue support")
> Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
> ---
> net/vhost-vdpa.c | 1 -
> 1 file changed, 1 deletion(-)
On Wed, Oct 19, 2022 at 10:54 PM Peter Xu wrote:
>
> On Wed, Oct 19, 2022 at 04:12:22PM +0200, Eric Auger wrote:
> > Hi Peter,
> >
> > On 10/19/22 16:01, Peter Xu wrote:
> > > Hi, Eric,
> > >
> > > On Wed, Oct 19, 2022 at 01:24:15PM +0200, Eric Auger wrote:
> > >>> @@ -1484,6 +1485,13 @@ static in
On Wed, Oct 19, 2022 at 8:27 PM Eric Auger wrote:
>
> Since b68ba1ca5767 ("memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP
> IOMMUTLBNotificationType"), vhost attempts to register DEVIOTLB_UNMAP
> notifier. This latter is supported by the intel-iommu which supports
> device-iotlb if the corresponding op
A simple helper to retrieve the length of the current insn.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 5 +
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
d
Signed-off-by: Richard Henderson
---
v7: Introduce DisasLabel to clean up pc_save frobbing.
Adjust pc_save around tcg_remove_ops_after.
---
target/arm/cpu-param.h| 1 +
target/arm/translate.h| 50 +++-
target/arm/cpu.c | 23
target/arm/tra
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 5 +++--
target/arm/translate-a64.c| 28 ++-
target/arm/translate-m-nocp.c | 6 ++---
target
On 10/17/22 20:01, Peter Maydell wrote:
On Tue, 11 Oct 2022 at 04:30, Richard Henderson
wrote:
Hoist the computation of the mmu_idx for the ptw up to
get_phys_addr_with_struct and get_phys_addr_twostage.
This removes the duplicate check for stage2 disabled
from the middle of the walk, performi
In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate-a32.h | 2 +-
target/arm/translate.h | 6 ++--
target/arm/translate-a64.c | 32 +---
This is the Arm specific changes required to reduce the
amount of translation for address space randomization.
Changes for v8:
* Add a comment to both gen_goto_tb concerning the ordering
of the pc update vs the goto_tb opcode.
r~
Richard Henderson (9):
target/arm: Introduce curr_insn_len
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 40 --
target/arm/translate.c | 10 ++
2 files changed, 27 insertions(+), 23 delet
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 10 ++
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 41 +++---
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a6
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/target/arm/transla
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/tar
On 10/20/22 01:06, Paolo Bonzini wrote:
The only issue with FMA instructions is that there are _a lot_ of them
(30 opcodes, each of which comes in up to 4 versions depending on VEX.W
and VEX.L).
We can reduce the number of helpers to one third by passing four operands
(one output and three input
On 10/20/22 01:06, Paolo Bonzini wrote:
F16C only consists of two instructions, which are a bit peculiar
nevertheless.
First, they access only the low half of an YMM or XMM register for the
packed-half operand; the exact size still depends on the VEX.L flag.
This is similar to the existing avx_m
On 10/20/22 01:06, Paolo Bonzini wrote:
If the destination is a memory register, op->n is -1. Going through
tcg_gen_gvec_dup_imm path is both useless (the value has been stored
by the gen_* function already) and wrong because of the out-of-bounds
access.
Signed-off-by: Paolo Bonzini
---
targ
On 10/20/22 01:06, Paolo Bonzini wrote:
VROUND, FSTCW and STMXCSR all have to perform the same conversion from
x86 rounding modes to softfloat constants. Since the ISA is consistent
on the meaning of the two-bit rounding modes, extract the common code
into a wrapper for set_float_rounding_mode.
On 10/20/22 01:16, Greg Kurz wrote:
When QEMU is started with `-daemonize`, all stdio descriptors get
redirected to `/dev/null`. This basically means that anything
printed with error_report() and friends is lost.
One could hope that passing `-D ${logfile}` would cause the messages
to go to `${lo
On 10/19/22 22:56, Christian Borntraeger wrote:
Ilya has volunteered to review TCG patches for s390x.
Signed-off-by: Christian Borntraeger
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3d5b7e09c46..ae5e8c8ecbb6 100644
--- a/MAINTAINERS
+
On Wed, Oct 19, 2022 at 2:39 PM Cindy Lu wrote:
>
> Add support for vIOMMU. Register a memory listener to dma_as in
> dev_start
> - during region_add register a specific IOMMU notifier, and store all
> notifiers in a list.
> - during region_del, compare and delete the IOMMU notifier from the list
Ping...
On Fri, 2022-10-07 at 21:27 +0800, Robert Hoo wrote:
> Ping...
> On Tue, 2022-09-27 at 08:30 +0800, Robert Hoo wrote:
> > On Mon, 2022-09-26 at 15:22 +0200, Igor Mammedov wrote:
> > > > > 0800200c9a66"), One, 0x05, Local0, One)
> > > > > +CreateDWordField (Local3, Zero,
On 10/19/22 22:50, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Used gvec to translate XVTSTDCSP and XVTSTDCDP.
xvtstdcsp:
reptloopimm master version prev versioncurrent version
25 40000 0,2062000,040730 (-80.2%)0,0407
When number of CPUs utilized by guest Windows is less than defined in
QEMU (i.e., desktop versions of Windows severely limits number of CPU
sockets), patch_and_save_context routine accesses non-existent PRCB and
fails. So, limit number of processed PRCBs by NumberProcessors taken
from guest Windows
On 10/19/22 21:35, Alex Bennée wrote:
The s390x EXecute instruction is a bit weird as we synthesis the
executed instruction from what we have stored in memory. When plugins
are enabled this breaks because we detect the ld_code2() loading from
a non zero offset without the rest of the instruction
Hi Eric,
On 10/20/22 4:18 AM, Eric Auger wrote:
On 10/12/22 01:18, Gavin Shan wrote:
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is disabled o
Thanks Paul & Julien for reviewing. I will update this in v2.
Regards,
Vikram
From: Paul Durrant
Date: Wednesday, October 19, 2022 at 9:16 AM
To: Garhwal, Vikram , qemu-devel@nongnu.org
Cc: Stabellini, Stefano , Stefano Stabellini
, Anthony Perard , Michael
S. Tsirkin , Marcel Apfelbaum ,
P
Hi Connie,
On 10/19/22 10:00 PM, Cornelia Huck wrote:
On Wed, Oct 12 2022, Gavin Shan wrote:
After the improvement to high memory region address assignment is
applied, the memory layout can be changed, introducing possible
migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
is
Hi Eric,
On 10/20/22 4:07 AM, Eric Auger wrote:
On 10/12/22 01:18, Gavin Shan wrote:
There are three high memory regions, which are VIRT_HIGH_REDIST2,
VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
are floating on highest RAM address. However, they can be disabled
in several
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 74
2 files changed, 251 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index ad149adbe1..b56b216110 100644
--- a
This patch series improves change-of-flow handling.
Currently, we set the PC to a new address before exiting a TB. The
ultimate goal is to use direct block chaining. However, several steps
are needed along the way.
1)
When a packet has more than one change-of-flow (COF) instruction, only
the fi
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 59
2 files changed, 67 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tc
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 190 +++
target/hexagon/genptr.c | 75
2 files changed, 265 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index b56b216110..dbafcae2de 100644
--- a
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Recall that Hexagon allows packets with multiple jumps where only the first
one with a true predicate will actually jump. So, we can only use direct
block chaining when the packet c
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Hexagon inner loops end with the endloop0 instruction
To go back to the beginning of the loop, this instructions writes to PC
from register SA0 (start address 0). To use direct bloc
When a packet has more than one change-of-flow instruction, only the first
one to branch is considered. We use the branch_taken variable to keep
track of this.
However, when there is a single cof instruction, we don't need the same
amount of bookkeeping.
We add the pkt_has_multi_cof member to th
The imported files don't properly mark all CONDEXEC instructions, so
we add some logic to hex_common.py to add the attribute.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 6 ++
target/hexagon/macros.h | 2 +-
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 +++
target/hexagon/insn.h
Matheus,
This series fails 'make check-avocado' in an e500 test. This is the error
output:
& make -j && \
make check-avocado
AVOCADO_TESTS=tests/avocado/replay_kernel.py:ReplayKernelNormal.test_ppc64_e500
(...)
Fetching asset from
tests/avocado/replay_kernel.py:ReplayKernelNormal.t
Alistair Francis writes:
>> @@ -310,10 +311,17 @@ bool pmp_hart_has_privs(CPURISCVState *env,
>> target_ulong addr,
>> }
>>
>> if (size == 0) {
>> -if (riscv_feature(env, RISCV_FEATURE_MMU)) {
>> +if (riscv_cpu_mxl(env) == MXL_RV32) {
>> +satp_mode = SATP32_M
On 10/6/22 17:06, Matheus Ferst wrote:
Signed-off-by: Matheus Ferst
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/insn32.decode | 5 ++
target/ppc/translate.c| 34 +
.../ppc/translate/processor-ctrl-impl.c.inc | 70 +++
On 10/6/22 17:06, Matheus Ferst wrote:
Signed-off-by: Matheus Ferst
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/insn32.decode | 1 +
target/ppc/translate.c | 14 --
target/ppc/translate/processor-ctrl-impl.c.inc | 9
Matheus,
This patch fails ppc-softmmu emulation:
FAILED: libqemu-ppc-softmmu.fa.p/target_ppc_translate.c.o
cc -m64 -mcx16 -Ilibqemu-ppc-softmmu.fa.p -I. -I.. -Itarget/ppc -I../target/ppc -I../dtc/libfdt
-Iqapi -Itrace -Iui -Iui/shader -I/usr/include/pixman-1 -I/usr/include/glib-2.0
-I/usr/lib
On Tue, Oct 18, 2022 at 6:23 AM Peter Maydell wrote:
>
> If you run this single avocado test:
>
> while ./build/x86/tests/venv/bin/avocado run
> build/x86/tests/avocado/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd
> ; do true; done
>
> then on my machine it will fail within 4 or 5
Hi Gavin,
On 10/12/22 01:18, Gavin Shan wrote:
> After the improvement to high memory region address assignment is
> applied, the memory layout can be changed, introducing possible
> migration breakage. For example, VIRT_HIGH_PCIE_MMIO memory region
> is disabled or enabled when the optimization i
Hi Gavin
On 10/12/22 01:18, Gavin Shan wrote:
> There are three high memory regions, which are VIRT_HIGH_REDIST2,
> VIRT_HIGH_PCIE_ECAM and VIRT_HIGH_PCIE_MMIO. Their base addresses
> are floating on highest RAM address. However, they can be disabled
> in several cases.
>
> (1) One specific high m
On 19/10/22 13:35, Alex Bennée wrote:
The s390x EXecute instruction is a bit weird as we synthesis the
executed instruction from what we have stored in memory. When plugins
are enabled this breaks because we detect the ld_code2() loading from
a non zero offset without the rest of the instruction
On 19/10/22 17:06, Paolo Bonzini wrote:
If the destination is a memory register, op->n is -1. Going through
tcg_gen_gvec_dup_imm path is both useless (the value has been stored
by the gen_* function already) and wrong because of the out-of-bounds
access.
Signed-off-by: Paolo Bonzini
---
targ
On 10/19/22 14:37, Philippe Mathieu-Daudé wrote:
On 19/10/22 21:15, Christian A. Ehrhardt wrote:
Fix memset argument order: The second argument is
the value, the length goes last.
Cc: Eric DeVolder
Cc: qemu-sta...@nongnu.org
Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature")
Si
On 19/10/22 17:06, Paolo Bonzini wrote:
VROUND, FSTCW and STMXCSR all have to perform the same conversion from
x86 rounding modes to softfloat constants. Since the ISA is consistent
on the meaning of the two-bit rounding modes, extract the common code
into a wrapper for set_float_rounding_mode.
On 19/10/22 21:15, Christian A. Ehrhardt wrote:
Fix memset argument order: The second argument is
the value, the length goes last.
Cc: Eric DeVolder
Cc: qemu-sta...@nongnu.org
Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature")
Signed-off-by: Christian A. Ehrhardt
---
hw/acpi/ers
On Tue, Oct 18, 2022 at 6:49 PM Michael S. Tsirkin wrote:
>
> On Tue, Oct 18, 2022 at 06:17:55PM +0200, Philippe Mathieu-Daudé wrote:
> > On 18/10/22 17:25, Julia Suvorova wrote:
> > > In the ACPI specification [1], the 'unarmed' bit is set when a device
> > > cannot accept a persistent write. Thi
Fix memset argument order: The second argument is
the value, the length goes last.
Cc: Eric DeVolder
Cc: qemu-sta...@nongnu.org
Fixes: f7e26ffa590 ("ACPI ERST: support for ACPI ERST feature")
Signed-off-by: Christian A. Ehrhardt
---
hw/acpi/erst.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
These are exercising core QEMU features and don't actually run code.
Not specifying a machine will fail when avocado chooses the native
arch binary to run. Be explicit.
Signed-off-by: Alex Bennée
---
tests/avocado/info_usernet.py | 3 +++
tests/avocado/vnc.py | 1 +
2 files changed, 4 i
On Wed, Oct 19, 2022 at 5:09 PM Sean Christopherson wrote:
>
> On Wed, Oct 19, 2022, Fuad Tabba wrote:
> > > > > This sounds good. Thank you.
> > > >
> > > > I like the idea of a separate Kconfig, e.g.
> > > > CONFIG_KVM_GENERIC_PRIVATE_MEM or
> > > > something. I highly doubt there will be any
On Wed, 2022-10-19 at 17:39 +0200, Pierre Morel wrote:
>
> On 10/18/22 18:43, Cédric Le Goater wrote:
[...]
> >
> > > diff --git a/hw/s390x/cpu-topology.c b/hw/s390x/cpu-topology.c
> > > new file mode 100644
> > > index 00..42b22a1831
> > > --- /dev/null
> > > +++ b/hw/s390x/cpu-topology.
On Wed, Oct 19, 2022 at 05:26:28PM +0100, Peter Maydell wrote:
> On Tue, 18 Oct 2022 at 20:21, Daniel P. Berrangé wrote:
> >
> > On Tue, Oct 18, 2022 at 06:55:08PM +0100, Peter Maydell wrote:
> > > How is this intended to work? I guess the socket ought to go
> > > into some kind of "disconnecting"
On Tue, 18 Oct 2022 at 20:21, Daniel P. Berrangé wrote:
>
> On Tue, Oct 18, 2022 at 06:55:08PM +0100, Peter Maydell wrote:
> > How is this intended to work? I guess the socket ought to go
> > into some kind of "disconnecting" state, but not actually do
> > a tcp_chr_disconnect() until all the data
On 15/10/2022 06:07, Vikram Garhwal wrote:
xenstore_record_dm_state() will also be used in aarch64 xenpv machine.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Paul Durrant
On 15/10/2022 06:07, Vikram Garhwal wrote:
[snip]
+qemu_add_vm_change_state_handler(xen_hvm_change_state_handler, state);
+
+state->memory_listener = xen_memory_listener;
+memory_listener_register(&state->memory_listener, &address_space_memory);
+
+state->io_listener = xen_io_list
On 15/10/2022 06:07, Vikram Garhwal wrote:
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also move handle_vmport_ioreq to arch_handle_ioreq.
NOTE: This patch breaks th
On Wed, Oct 19, 2022, Fuad Tabba wrote:
> > > > This sounds good. Thank you.
> > >
> > > I like the idea of a separate Kconfig, e.g.
> > > CONFIG_KVM_GENERIC_PRIVATE_MEM or
> > > something. I highly doubt there will be any non-x86 users for multiple
> > > years,
> > > if ever, but it would allow
This resolves the target_ulong dependency that's clearly wrong and was
also noted in a fixme comment.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdr
On Wed, Oct 19, 2022 at 04:30:57PM +0100, Alex Bennée wrote:
>
> Ani Sinha writes:
>
> > PSS tests in acpi test suite seems to be failing in biosbits. This is
> > because
> > the test is unable to find PSS support in QEMU bios. Let us disable
> > them for now so that make check does not fail. W
On Wed, Oct 19, 2022 at 06:43:46PM +0300, Nikolay Borisov wrote:
>
>
> On 18.10.22 г. 13:06 ч., Daniel P. Berrangé wrote:
> > On Mon, Oct 10, 2022 at 04:34:00PM +0300, Nikolay Borisov wrote:
> > > This is required so that migration stream configuration is written
> > > to the migration stream. Th
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c | 352
hw/ppc/ppc4xx_sdram.c | 365 ++
2 files changed, 365 insertions(+), 352 deletions(-)
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 12af
Do not exit from ppc4xx_sdram_banks() but report error via an errp
parameter instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/ppc4xx_sdram.c | 28 +++-
1 file changed, 19 insertions(+), 9 deletions(-)
diff --git a/hw/ppc/ppc4xx_sdram
This is the end of the QOMify series originially started by Cédric
rebased on master now only including patches not yet merged. Patches
that still need review are 1-3 (these only move code to
ppc4xx_sdram.c) and 6-7 (unify DDR and DDR2 models to share code where
possible).
Regards,
BALATON Zoltan
Currently only base and size are set on initial bank creation and bcr
value is computed on mapping the region. Set bcr at init so the bcr
encoding method becomes local to the controller model and mapping and
unmapping can operate on the bank so it can be shared between
different controller models.
This function is only used by the ppc4xx memory controller models so
it can be made static.
Signed-off-by: BALATON Zoltan
---
hw/ppc/ppc4xx_devs.c| 62 -
hw/ppc/ppc4xx_sdram.c | 61
include/hw/ppc/ppc4xx.h | 2
Rename the sdram local state variable to s in dcr read/write functions
and reset methods for better readability and to match realize methods.
Other places not converted will be changed or removed in subsequent
patches.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc
In order to move PPC4xx SDRAM controller models together move out the
DDR2 controller model from ppc440_uc.c into a new ppc4xx_sdram.c file.
Signed-off-by: BALATON Zoltan
---
hw/ppc/meson.build| 3 +-
hw/ppc/ppc440_uc.c| 332
hw/ppc/ppc4xx_sdram
Use the generic bank handling introduced in previous patch in the DDR
SDRAM controller too. This also fixes previously broken region unmap
due to sdram_ddr_unmap_bcr() ignoring container region so it crashed
with an assert when the guest tried to disable the controller.
Signed-off-by: BALATON Zolt
On 15/10/2022 06:07, Vikram Garhwal wrote:
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the
On Wed, Oct 19, 2022 at 05:16:50PM +0200, Greg Kurz wrote:
> A subsequent patch needs to be able to differentiate the main QEMU
> thread from other threads. An obvious way to do so is to compare
> log_thread_id() and getpid(), based on the fact that they are equal
> for the main thread on systems t
On 15/10/2022 06:07, Vikram Garhwal wrote:
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the
> From: Qemu-devel bounces+yishaih=nvidia@nongnu.org> On Behalf Of Jason Gunthorpe
> Sent: Tuesday, 18 October 2022 15:23
> To: Joao Martins
> Cc: quint...@redhat.com; Alex Williamson ;
> Eric Blake ; Stefan Hajnoczi ;
> Fam Zheng ; qemu-s3...@nongnu.org; Cornelia Huck
> ; Thomas Huth ; Vladi
On 10/19/22 11:03, Cornelia Huck wrote:
On Tue, Oct 18 2022, Cédric Le Goater wrote:
On 10/12/22 18:21, Pierre Morel wrote:
S390 CPU topology is only allowed for s390-virtio-ccw-7.3 and
newer S390 machines.
We keep the possibility to disable the topology on these newer
machines with the pr
On Wed, Oct 19, 2022 at 9:01 PM Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
> > PSS tests in acpi test suite seems to be failing in biosbits. This is
> > because
> > the test is unable to find PSS support in QEMU bios. Let us disable
> > them for now so that make check does not fail. We can fix
On 18.10.22 г. 13:06 ч., Daniel P. Berrangé wrote:
On Mon, Oct 10, 2022 at 04:34:00PM +0300, Nikolay Borisov wrote:
This is required so that migration stream configuration is written
to the migration stream. This would allow analyze-migration to
parse enabled capabilities for the migration an
On Dienstag, 18. Oktober 2022 10:43:40 CEST Nikita Ivanov wrote:
> Rename macro name to more transparent one and refactor
> it to expression.
>
> Signed-off-by: Nikita Ivanov
> ---
> chardev/char-fd.c | 2 +-
> chardev/char-pipe.c| 8 +---
> include/qemu/osdep.h | 8 +++-
> ne
On Wed, Oct 19, 2022 at 9:04 PM Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
> > Add a README file that describes the purpose of the various test files and
> > gives
> > guidance to developers on where and how to make changes.
> >
> > Cc: Daniel P. Berrange"
> > Cc: Paolo Bonzini
> > Cc: Mayde
On 10/18/22 18:43, Cédric Le Goater wrote:
Hello Pierre,
On 10/12/22 18:20, Pierre Morel wrote:
In the S390x CPU topology the core_id specifies the CPU address
and the position of the core withing the topology.
Let's build the topology based on the core_id.
s390x/cpu topology: core_id sets
Ani Sinha writes:
> smilatency test is latency sensitive and does not pass deterministically when
> run in QEMU environment under biosbits. Disable the test suite for now.
>
> Example failure:
>
> SMI latency test
> Warning: touching the keyboard can affect the results of this test.
>
On Tue, Oct 18, 2022 at 07:12:10PM +0530, Vishal Annapurve wrote:
> On Tue, Oct 18, 2022 at 3:27 AM Kirill A . Shutemov
> wrote:
> >
> > On Mon, Oct 17, 2022 at 06:39:06PM +0200, Gupta, Pankaj wrote:
> > > On 10/17/2022 6:19 PM, Kirill A . Shutemov wrote:
> > > > On Mon, Oct 17, 2022 at 03:00:21PM
On Wed, Oct 19, 2022 at 9:02 PM Alex Bennée wrote:
>
>
> Ani Sinha writes:
>
> > Added the SPDX license identifier for smilatency tests.
> > Also added a comment indicating that smilatency test is run from within the
> > biosbits environment/VM and hence is not subjected to QEMU build/test
> > en
Ani Sinha writes:
> Add a README file that describes the purpose of the various test files and
> gives
> guidance to developers on where and how to make changes.
>
> Cc: Daniel P. Berrange"
> Cc: Paolo Bonzini
> Cc: Maydell Peter
> Cc: John Snow
> Cc: Thomas Huth
> Cc: Alex Bennée
> Cc:
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