From: Eugenio Pérez
We can restore the device state in the destination via CVQ now. Remove
the migration blocker.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Signed-off-by: Jason Wang
---
hw/virtio/vhost-vdpa.c | 15 ---
include/hw/virtio/vhost-vdpa.h | 1 -
net/vh
From: Eugenio Pérez
It was easier to allow vhost_svq_add to handle the memory. Now that we
will allow qemu to add elements to a SVQ without the guest's knowledge,
it's better to handle it in the caller.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Signed-off-by: Jason Wang
---
hw/virtio
From: Eugenio Pérez
Since QEMU will be able to inject new elements on CVQ to restore the
state, we need not to depend on a VirtQueueElement to know if a new
element has been used by the device or not. Instead of check that, check
if there are new elements only using used idx on vhost_svq_flush.
From: Eugenio Pérez
Reduce code duplication.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Signed-off-by: Jason Wang
---
hw/virtio/vhost-vdpa.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index e208
From: Eugenio Pérez
Nothing actually reads the return value, but an error in cleaning some
entries could cause device stop to abort, making a restart impossible.
Better ignore explicitely the return value.
Reported-by: Lei Yang
Fixes: 34e3c94eda ("vdpa: Add custom IOTLB translations to SVQ")
Si
From: Eugenio Pérez
As discussed in previous series [1], this memory barrier is useless with
the atomic read of used idx at vhost_svq_more_used. Deleting it.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02616.html
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Signed-off
From: Eugenio Pérez
We can unbind twice a file descriptor if we call twice
vhost_svq_set_svq_kick_fd because of this. Since it comes from vhost and
not from SVQ, that file descriptor could be a different thing that
guest's vhost notifier.
Likewise, it can happens the same if a guest start and st
The following changes since commit 7dd9d7e0bd29abf590d1ac235c0a00606ef81153:
Merge tag 'pull-ppc-20220831' of https://gitlab.com/danielhb/qemu into
staging (2022-09-01 13:53:20 -0400)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you
From: Eugenio Pérez
Next patch will skip the registering of dma maps that the vdpa device
rejects in the iova tree. We need to consider that here or we cause a
SIGSEGV accessing result.
Reported-by: Lei Yang
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Signed-off-by: Jason Wang
---
hw/
From: Eugenio Pérez
It's convenient to call iova_tree_remove from a map returned from
iova_tree_find or iova_tree_find_iova. With the current code this is not
possible, since we will free it, and then we will try to search for it
again.
Fix it making accepting the map by value, forcing a copy of
From: Eugenio Pérez
If a map fails for whatever reason, it must not be saved in the tree.
Otherwise, qemu will try to unmap it in cleanup, leaving to more errors.
Fixes: 34e3c94eda ("vdpa: Add custom IOTLB translations to SVQ")
Reported-by: Lei Yang
Signed-off-by: Eugenio Pérez
Acked-by: Jason
On Fri, Sep 02, 2022 at 08:07:20AM +0200, Gerd Hoffmann wrote:
> On Fri, Sep 02, 2022 at 08:10:00AM +0800, Xiaoyao Li wrote:
> > On 9/2/2022 12:17 AM, Gerd Hoffmann wrote:
> > > On Thu, Sep 01, 2022 at 10:36:19PM +0800, Xiaoyao Li wrote:
> > > > On 9/1/2022 9:58 PM, Gerd Hoffmann wrote:
> > > >
>
QEMU use qemu_add_opts() and qemu_add_drive_opts() to add config options
when initialization. Extract the same logic in both functions to a
seperate function fill_config_groups() to reduce code redundency.
Signed-off-by: Wang, Lei
---
util/qemu-config.c | 39 -
On Fri, Sep 02, 2022 at 08:10:00AM +0800, Xiaoyao Li wrote:
> On 9/2/2022 12:17 AM, Gerd Hoffmann wrote:
> > On Thu, Sep 01, 2022 at 10:36:19PM +0800, Xiaoyao Li wrote:
> > > On 9/1/2022 9:58 PM, Gerd Hoffmann wrote:
> > >
> > > > > Anyway, IMO, guest including guest firmware, should always consul
On Fri, Sep 02, 2022 at 02:52:25AM +, Sean Christopherson wrote:
> On Fri, Sep 02, 2022, Xiaoyao Li wrote:
> > On 8/26/2022 1:57 PM, Gerd Hoffmann wrote:
> > >Hi,
> > > > For TD guest kernel, it has its own reason to turn SEPT_VE on or off.
> > > > E.g.,
> > > > linux TD guest requires SEP
On Wed, Aug 24, 2022 at 4:52 PM Bin Meng wrote:
>
> From: Bin Meng
>
> The maximum number of wait objects for win32 should be
> MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v3:
> - move the check of adding the same HANDLE twice to a separet
Ztso, the RISC-V extension that provides the TSO memory model, was
recently frozen. This provides support for Ztso on targets that are
themselves TSO.
Signed-off-by: Palmer Dabbelt
---
My first thought was to just add the TCG barries to load/store and AMOs
that as defined by Ztso, but after po
> ping
Apologies for the late review - busy week. First pass looks good but will review
comprehensively tomorrow or over the weekend.
On Fri, Sep 02, 2022, Xiaoyao Li wrote:
> On 8/26/2022 1:57 PM, Gerd Hoffmann wrote:
> >Hi,
> > > For TD guest kernel, it has its own reason to turn SEPT_VE on or off.
> > > E.g.,
> > > linux TD guest requires SEPT_VE to be disabled to avoid #VE on syscall gap
> > > [1].
> >
> > Why is that a
On 8/26/2022 1:57 PM, Gerd Hoffmann wrote:
Hi,
For TD guest kernel, it has its own reason to turn SEPT_VE on or off. E.g.,
linux TD guest requires SEPT_VE to be disabled to avoid #VE on syscall gap
[1].
Why is that a problem for a TD guest kernel? Installing exception
handlers is done q
On 9/1/22 23:57, Markus Armbruster wrote:
> Sam Li writes:
>
>> Markus Armbruster 于2022年8月31日周三 16:35写道：
>>>
>>> Sam Li writes:
>>>
Markus Armbruster 于2022年8月30日周二 19:57写道：
>
> Sam Li writes:
>
>> By adding zone management operations in BlockDriver, storage controller
>>>
On 9/1/2022 7:55 PM, Alex Bennée wrote:
>
> "Wang, Lei" writes:
>
>> On 9/1/2022 4:12 PM, Daniel P. Berrangé wrote:
>>> On Thu, Sep 01, 2022 at 09:08:33AM +0800, Wang, Lei wrote:
On 8/31/2022 6:39 PM, Daniel P. Berrangé wrote:
> On Wed, Aug 31, 2022 at 05:18:34PM +0800, Wang, Lei wrote:
Hi,
On Wed, Jul 13, 2022 at 8:45 PM Paolo Bonzini wrote:
>
> From: Mauro Matteo Cascella
>
> Set current_req to NULL, not current_req->req, to prevent reusing a free'd
> buffer in case of repeated SCSI cancel requests. Also apply the fix to
> CLEAR QUEUE and BUS DEVICE RESET messages as well, s
1. Adds fields to hold the value of mtime in timer_upper0 and timer_lower0.
2. Changes the read and write functions to use the mtime fields.
3. Updates the value of mtime in update_mtime() by extrapolating the
time elapsed. This will need to change if/when the prescalar is
implemented.
Signed-of
This commit adds most of an implementation of the OpenTitan Always-On
Timer. The documentation for this timer is found here:
https://docs.opentitan.org/hw/ip/aon_timer/doc/
The implementation includes most of the watchdog features; it does not
implement the wakeup timer.
An important note: the O
This patch series does three things:
1) Adds an implementation of the OpenTitan Always-On Timer's watchdog
functionality
2) Fixes a bug encountered with the SiFive PLIC device during development
3) Updates the register addresses and adds support for writes to mtime
for the Ibex timer
(2) is necess
Updates the register addresses to match the OpenTitan spec.
These changes were made in this commit:
https://github.com/lowRISC/opentitan/commit/a25e162b8f91bd0ca32258c83d1d480f93327204
Signed-off-by: Tyler Ng
---
hw/timer/ibex_timer.c | 20 ++--
1 file changed, 10 insertions(+),
Fixes a bug in which the index of the interrupt priority is off by 1.
For example, using an IRQ number of 3 with a priority of 1 is supposed to set
plic->source_priority[2] = 1, but instead it sets
plic->source_priority[3] = 1. When an interrupt is claimed to be
serviced, it checks the index 2 inst
Do you have any comments about this patch set?
Thanks
在 2022/8/25 16:08, Kangjie Xu 写道:
The virtio queue reset function has already been defined in the virtio spec 1.2.
The relevant virtio spec information is here:
https://github.com/oasis-tcs/virtio-spec/issues/124
https://github.co
The following scenario can happen if QEMU sets more RESET flags while
the KVM_RESET_DIRTY_RINGS ioctl is ongoing on another host CPU:
CPU0 CPU1 CPU2
--
On 9/2/2022 12:17 AM, Gerd Hoffmann wrote:
On Thu, Sep 01, 2022 at 10:36:19PM +0800, Xiaoyao Li wrote:
On 9/1/2022 9:58 PM, Gerd Hoffmann wrote:
Anyway, IMO, guest including guest firmware, should always consult from
CPUID leaf 0x8008 for physical address length.
It simply can't for the
On 1/9/22 07:32, Richard Henderson wrote:
On 9/1/22 02:02, Wilfred Mallawa wrote:
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the res
On 1/9/22 18:25, Bernhard Beschow wrote:
According to the PIIX3 datasheet, the reset control register is one byte in
size.
Moreover, PIIX4 has it, so add it to PIIX3 as well.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
Revi
Some registers are defined to have immutable bits, this commit
will implement that behavior.
Signed-off-by: Brian Cain
---
target/hexagon/gen_masked.c | 44
target/hexagon/gen_masked.h | 26
target/hexagon/genptr.c | 33 -
target/hexagon/hex
clang builds are failing:
clang -m64 -mcx16 -Ilibqemu-alpha-softmmu.fa.p -I. -I.. -Itarget/alpha
-I../target/alpha -Iqapi -Itrace -Iui -Iui/shader
-I/usr/include/pixman-1 -I/usr/include/capstone
-I/usr/include/spice-server -I/usr/include/spice-1
-I/usr/include/cacard -I/usr/include/glib-2.0
-I/usr
Describe how multiple TCG plugins can interact using the QEMU
Plugin-to-Plugin API (QPP) with both callbacks and direct
function calls.
Signed-off-by: Andrew Fasano
---
docs/devel/tcg-plugins.rst | 76 ++
1 file changed, 76 insertions(+)
diff --git a/docs/dev
Expand tcg-plugin system to allow for plugins to export functions
and callbacks that can be used by other plugins. Exported functions
can be called at runtime by other loaded plugins. Loaded plugins
can register functions with exported callbacks and have these
functions run whenever the callback is
The first plugin, qpp_srv exposes two functions and one callback that other
plugins can leverage. These functions are described in the corresponding
header file.
The second plugin, qpp_client, imports this header file, registers its
own function to run on a qpp_srv-provided callback, and directly
Use plugin filenames to set the preprocessor variable CURRENT_PLUGIN
as a string during plugin compilation.
Signed-off-by: Andrew Fasano
---
contrib/plugins/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/contrib/plugins/Makefile b/contrib/plugins/Makefile
index df34
Hello,
I'm requesting comments on the following series of patches expanding the
TCG plugin system to add the "QEMU Plugin-to-Plugin (QPP)" interface
that allows for interactions between TCG plugins. The goal of this
interface is to enable plugins to expand on other plugins and reduce
code duplicat
On 1/9/22 18:26, Bernhard Beschow wrote:
Resolving the PIIX ISA bridge rather than the PIIX ACPI controller mirrors
the ICH9 code one line below.
Signed-off-by: Bernhard Beschow
---
hw/i386/acpi-build.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.c
On Fri, 19 Aug 2022, BALATON Zoltan wrote:
Hello,
This is based on gitlab.com/danielhb/qemu/tree/ppc-7.2
Now that the queue is flushed it should apply on master so
Ping
Regards,
BALATON Zoltan
This is the end of the QOMify series started by Cédric. This series
handles the SDRAM controller
On 1/9/22 18:26, Bernhard Beschow wrote:
This method post-loads the southbridge, not the IDE device.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 1/9/22 18:25, Bernhard Beschow wrote:
PIIX3 initializes the PIRQx route control registers to the default
values as described in the 82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)
April 1997 manual. PIIX4, however, initializes the routes according to
the Malta™ User’s Manual, ch 6.6, which are IRQs
On 1/9/22 18:25, Bernhard Beschow wrote:
For the VIA south bridges there was a comment to have the call in board code.
Move it there for PIIX4 as well for consistency.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c | 1 -
hw/mips/malta.c | 10 ++
2 files changed, 6 insertions(
On 1/9/22 18:25, Bernhard Beschow wrote:
While at it, move the assignments closer to where they are used.
Signed-off-by: Bernhard Beschow
---
hw/mips/malta.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 1/9/22 18:25, Bernhard Beschow wrote:
get_system_memory() accesses global state while pci_address_space() uses
whatever has been passed to the device instance, so avoid the global.
Moreover, PIIX4 uses pci_address_space() here as well.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 2
On 1/9/22 18:25, Bernhard Beschow wrote:
Rather than registering the reset handler via a function which
appends the handler to a global list, prefer to implement it as
a virtual method - PIIX4 does the same already.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix3.c | 8 +++-
1 file chan
On 1/9/22 18:25, Bernhard Beschow wrote:
Fixes the "extra-semi" clang-tidy check.
Signed-off-by: Bernhard Beschow
Reviewed-by: Peter Maydell
---
hw/isa/piix3.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any
user-visible changes.
signature.asc
Description: PGP signature
On Thu, Sep 1, 2022, 14:09 Daniel Henrique Barboza
wrote:
>
>
> On 8/30/22 18:12, Stefan Hajnoczi wrote:
> > Hi,
> > Richard Henderson has tagged QEMU 7.1 and handed over to me for the 7.2
> > release cycle. Thanks to Richard and Michael Roth their work on 7.1!
>
> Are you going to handle the pul
On 1/9/22 18:25, Bernhard Beschow wrote:
The USB controller is an integral part of PIIX3 (function 2). So create
it as part of the south bridge.
Note that the USB function is optional in QEMU. This is why it gets
object_initialize_child()'ed in realize rather than in instance_init.
Signed-off-b
On 1/9/22 18:25, Bernhard Beschow wrote:
Just like in the real hardware (and in PIIX4), create the DMA
controllers in the south bridges.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc.c | 3 ---
hw/i386/pc_piix.c | 2 ++
hw/isa/Kconfig| 2 ++
hw/isa/lpc_ich9.c | 3 +++
hw/isa/pii
From: Paul Brook
Fixup various vector helpers that either trivially exten to 256 bit,
or don't have 256 bit variants.
No functional changes to existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-19-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo B
From: Paul Brook
AVX includes an additional set of comparison predicates, some of which
our softfloat implementation does not expose as separate functions.
Rewrite the helpers in terms of floatN_compare for future extensibility.
Signed-off-by: Paul Brook
Reviewed-by: Richard Henderson
Message-
From: Paul Brook
Perpare the horizontal atithmetic vector helpers for AVX
These currently use a dummy Reg typed variable to store the result then
assign the whole register. This will cause 128 bit operations to corrupt
the upper half of the register, so replace it with explicit temporaries
and e
From: Paul Brook
Rewrite the "simple" vector integer helpers in preperation for AVX support.
While the current code is able to use the same prototype for unary
(a = F(b)) and binary (a = F(b, c)) operations, future changes will cause
them to diverge.
No functional changes to existing helpers
S
From: Paul Brook
Make the pclmulqdq helper AVX ready
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-21-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 29 ++---
1 file changed, 22 insertions(+), 7 d
From: Paul Brook
More preparatory work for AVX support in various integer vector helpers
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-13-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops
From: Paul Brook
Rewrite the vector shift helpers in preperation for AVX support (3 operand
form and 256 bit vectors).
For now keep the existing two operand interface.
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-11-p...@nowt.org>
Re
From: Paul Brook
Rewrite the blendv helpers so that they can easily be extended to support
the AVX encodings, which make all 4 arguments explicit.
No functional changes to the existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-20-p...@nowt.org>
Reviewed-by: Richard
Use a union to store the various possible kinds of function pointers, and
access the correct one based on the flags.
SSEOpHelper_table6 and SSEOpHelper_table7 right now only have one case,
but this would change with AVX's 3- and 4-argument operations. Use
unions there too, to keep the code more s
From: Paul Brook
Make the AES vector helpers AVX ready
No functional changes to existing helpers
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-22-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 41 ++---
1 file chang
Remove use of the MOVE macro, since it will be purged from
MMX/SSE as well.
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index f603981ab8
From: Paul Brook
These helpers need to take special care to avoid overwriting source values
before the wole result has been calculated. Currently they use a dummy
Reg typed variable to store the result then assign the whole register.
This will cause 128 bit operations to corrupt the upper half o
From: Paul Brook
Add a convenience macro to get the address of an xmm_regs element within
CPUX86State.
This was originally going to be the basis of an implementation that broke
operations into 128 bit chunks. I scrapped that idea, so this is now a purely
cosmetic change. But I think a worthwhile
From: Paul Brook
Reject invalid VEX encodings on MMX instructions.
Signed-off-by: Paul Brook
Reviewed-by: Richard Henderson
Message-Id: <20220424220204.2493824-7-p...@nowt.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 26 ++
1 file changed, 26 in
From: Paul Brook
Make the dpps and dppd helpers AVX-ready
I can't see any obvious reason why dppd shouldn't work on 256 bit ymm
registers, but both AMD and Intel agree that it's xmm only.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-17-p...@nowt.org>
Reviewed-by: Richard Hende
For AVX we're going to need both 128 bit (xmm) and 256 bit (ymm) variants of
floating point helpers. Add the register type suffix to the existing
*PS and *PD helpers (SS and SD variants are only valid on 128 bit vectors)
No functional changes.
Signed-off-by: Paul Brook
Message-Id: <2022042422020
From: Paul Brook
Prepare the "easy" floating point vector helpers for AVX
No functional changes to existing helpers.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-16-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 138 ++
From: Paul Brook
Add a flags field to each row in sse_op_table1.
Initially this is only used as a replacement for the magic
SSE_SPECIAL and SSE_DUMMY pointers, the other flags are mostly
relevant for the AVX implementation but can be applied to SSE as well.
Signed-off-by: Paul Brook
Message-Id
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 52 +++--
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.
From: Paul Brook
Handle 3DNOW instructions early to avoid complicating the MMX/SSE logic.
Signed-off-by: Paul Brook
Message-Id: <20220424220204.2493824-25-p...@nowt.org>
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 30 +
Write down explicitly the load/store sequence.
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/
Put more flags to work to avoid hardcoding lists of opcodes. The op7 case
for SSE_OPF_CMP is included for homogeneity and because AVX needs it, but
it is never used by SSE or MMX.
Extracted from a patch by Paul Brook .
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 75 +
The computation must not overwrite neither the destination
nor the source before the last element has been computed.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/ops_sse.h | 49 +--
1 file changed, 29 insertions(+), 20 delet
Cover all BMI1 and BMI2 instructions, both 32- and 64-bit.
Due to the use of inlines, the test now has to be compiled with -O2.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 1 +
tests/tcg/i386/test-i386-bmi2.c | 169 +++
Extracted from a patch by Paul Brook .
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 3237c1d8f9..25a2539d59 10
From: Paul Brook
Add a flags field each row in sse_op_table6 and sse_op_table7.
Initially this is only used as a replacement for the magic SSE41_SPECIAL
pointer. The other flags are mostly relevant for the AVX implementation
but can be applied to SSE as well.
Signed-off-by: Paul Brook
Message
Found with "muon analyze".
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
plugins/meson.build | 2 +-
tests/fp/meson.build | 2 +-
tests/qapi-schema/meson.build | 24
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/
The DPPS (Dot Product) instruction is defined to first sum pairs of
intermediate results, then sum those values to get the final result.
i.e. (A+B)+(C+D)
We incrementally sum the results, i.e. ((A+B)+C)+D, which can result
in incorrect rouding.
For consistency, also change the variable names to t
From: Vitaly Kuznetsov
kvm_put_sregs2() fails to reset 'locked' CR4/CR0 bits upon vCPU reset when
it is in VMX root operation. Do kvm_put_msr_feature_control() before
kvm_put_sregs2() to (possibly) kick vCPU out of VMX root operation. It also
seems logical to do kvm_put_msr_feature_control() befo
The KVM_DIRTY_GFN_F_DIRTY flag ensures that the entry is valid. If
the read of the fields are not ordered after the read of the flag,
QEMU might see stale values.
Cc: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Xu
Signed-off-by: Paolo Bonzini
---
accel/kvm/kvm-all.c | 6
Include test-i386-bmi2, and specify manually the tests (only one for now)
that need -cpu max.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
tests/tcg/i386/Makefile.target | 2 +-
tests/tcg/x86_64/Makefile.target | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
dif
From: Vitaly Kuznetsov
Make sure env->nested_state is cleaned up when a vCPU is reset, it may
be stale after an incoming migration, kvm_arch_put_registers() may
end up failing or putting vCPU in a weird state.
Reviewed-by: Maxim Levitsky
Signed-off-by: Vitaly Kuznetsov
Message-Id: <20220818150
From: Anton Kochkov
While Meson buildsystem accepts the 'false' as a value
for boolean options, it's not covered by the specification
and in general invalid. Some alternative Meson implementations,
like Muon, do not accept 'false' or 'true' as a valid value
for the boolean options.
See https://m
Found with "muon analyze".
Reviewed-by: Marc-André Lureau
Signed-off-by: Paolo Bonzini
---
meson.build | 2 --
pc-bios/keymaps/meson.build | 1 -
qapi/meson.build| 15 ---
target/riscv/meson.build| 2 --
4 files changed, 20 deletions(-)
diff --git
From: John Millikin
When a SCSI command is received from the guest, the CDB length implied
by the first byte might exceed the number of bytes the guest sent. In
this case scsi_req_new() will read uninitialized data, causing
unpredictable behavior.
Adds the buf_len parameter to scsi_req_new() and
Instead of using feature_not_found(), which is not a good match because
there is no "remedy" to fix the lack of makecontext(), just print a
custom error.
This happens to remove the last use of feature_not_found(), so remove
the definition and the documentation.
Signed-off-by: Paolo Bonzini
---
From: John Millikin
In scsi_req_parse_cdb(), if the CDB length implied by the command type
exceeds the initialized portion of the command buffer, reject the request.
Rejected requests are recorded by the `scsi_req_parse_bad` trace event.
On example of a bug detected by this check is SunOS's use
From: John Millikin
Per investigation on the linked ticket, SunOS issues a SCSI bus reset
to the ESP as part of its boot sequence. If this ESP command doesn't
cause devices to assert sense flag UNIT ATTENTION, SunOS will consider
the CD-ROM device to be non-compliant with Common Command Set (CCS)
The following changes since commit e93ded1bf6c94ab95015b33e188bc8b0b0c32670:
Merge tag 'testing-pull-request-2022-08-30' of https://gitlab.com/thuth/qemu
into staging (2022-08-31 18:19:03 -0400)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
f
On 8/30/22 18:12, Stefan Hajnoczi wrote:
Hi,
Richard Henderson has tagged QEMU 7.1 and handed over to me for the 7.2
release cycle. Thanks to Richard and Michael Roth their work on 7.1!
Are you going to handle the pull requests for this release cycle? I saw
that you've handled Thomas' PRs.
From: Hyman Huang(黄勇)
v1:
- make parameter vcpu-dirty-limit experimental
- switch dirty limit off when cancel migrate
- add cancel logic in migration test
Please review, thanks,
Yong
Abstract
This series added a new migration capability called "dirtylimit". It can
be enabled when
From: Hyman Huang(黄勇)
Introduce migration dirty-limit capability, which can
be turned on before live migration and limit dirty
page rate durty live migration.
Introduce migrate_dirty_limit function to help check
if dirty-limit capability enabled during live migration.
Meanwhile, refactor vcpu_d
From: Hyman Huang(黄勇)
Guestperf tool does not cover the dirty-limit migration
currently, support this feature.
To enable dirty-limit, setting x-vcpu-dirty-limit-period
as 500ms and x-vcpu-dirty-limit as 10MB/s:
$ ./tests/migration/guestperf.py \
--dirty-limit --x-vcpu-dirty-limit-period 500
From: Hyman Huang(黄勇)
Implement dirty-limit convergence algo for live migration,
which is kind of like auto-converge algo but using dirty-limit
instead of cpu throttle to make migration convergent.
Signed-off-by: Hyman Huang(黄勇)
---
migration/migration.c | 1 +
migration/ram.c| 53 ++
From: Hyman Huang(黄勇)
Export dirty limit throttle time and estimated ring full
time, through which we can observe the process of dirty
limit during live migration.
Signed-off-by: Hyman Huang(黄勇)
---
include/sysemu/dirtylimit.h | 2 ++
migration/migration.c | 10 ++
monitor/hmp-c
From: Hyman Huang(黄勇)
Guestperf tool does not enable diry ring feature when test
migration by default.
To support dirty ring migration performance test, introduce
dirty-ring-size option into guestperf tools, which ranges in
[1024, 65536].
To set dirty ring size with 4096 during migration test:
From: Hyman Huang(黄勇)
Introduce "x-vcpu-dirty-limit" migration parameter used
to limit dirty page rate during live migration.
"x-vcpu-dirty-limit" and "x-vcpu-dirty-limit-period" are
two dirty-limit-related migration parameters, which can
be set before and during live migration by qmp
migrate-se
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