Re: [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check

On Sun, Jul 10, 2022 at 6:30 PM Weiwei Li wrote: > > Just add 1 to the effective privledge level when in HS mode, then reuse the > check > 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege > level > related check in hmode. Then, hmode will only check whether H extension i

Re: [PATCH 5/6] target/riscv: fix checks in hmode/hmode32

On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li wrote: > > - It seems that there is no explicitly description about whether > the Hypervisor CSRs requires S extension > - Csrs only existed in RV32 will not trigger virtual instruction fault > when not in RV32 > > Signed-off-by: Weiwei Li > Signed-off-by

Re: [PATCH 4/6] target/riscv: add check for csrs existed with U extension

On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li wrote: > > - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 25 ++--- > 1 file changed,

Re: [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table

On Sun, Jul 10, 2022 at 6:28 PM Weiwei Li wrote: > > - line over 80 characters will trigger warning when running checkpatch > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > --- > target/riscv/csr.c | 362 - > 1 file changed, 196 insertion

Re: [PATCH v4 01/12] qga: treat get-guest-fsinfo as "best effort"

On Fri, Jul 8, 2022 at 8:16 PM John Snow wrote: > In some container environments, there may be references to block devices > witnessable from a container through /proc/self/mountinfo that reference > devices we simply don't have access to in the container, and cannot > provide information about.

Re: [PATCH 2/6] target/riscv: H extension depends on I extension

On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li wrote: > > - add check for "H depends on an I base integer ISA with 32 x registers" > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ > 1 file changed, 6 inserti

Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations

On Sun, Jul 10, 2022 at 6:25 PM Weiwei Li wrote: > > - There are 3 suggested privilege modes conbinations listed in the spec: > 1) M, 2) M, U 3) M, S, U > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ >

Re: [PATCH] hw/riscv: virt: pass random seed to fdt

On Mon, Jul 11, 2022 at 10:28 AM Jason A. Donenfeld wrote: > > On 7/11/22, Alistair Francis wrote: > > On Fri, Jul 8, 2022 at 7:56 PM Jason A. Donenfeld wrote: > >> > >> Hi Alistair, > >> > >> On 7/8/22, Alistair Francis wrote: > >> > >> >> > but I think that's just the way things go unfortunat

[PATCH] linux-user/aarch64: Do not clear PROT_MTE on mprotect

The documentation for PROT_MTE says that it cannot be cleared by mprotect. Further, the implementation of the VM_ARCH_CLEAR bit, contains PROT_BTI confiming that bit should be cleared. Introduce PAGE_TARGET_STICKY to allow target/arch/cpu.h to control which bits may be reset during page_set_flags

[PATCH] vfio/migration: Fix incorrect initialization value for parameters in VFIOMigration

The structure VFIOMigration of a VFIODevice is allocated and initialized in vfio_migration_init(). "device_state" and "vm_running" are initialized to 0, indicating that VFIO device is_STOP and VM is not-running. The initialization value is incorrect. According to the agreement, default state of VFI

Re: [PATCH] hw/riscv: virt: pass random seed to fdt

On 7/11/22, Alistair Francis wrote: > On Fri, Jul 8, 2022 at 7:56 PM Jason A. Donenfeld wrote: >> >> Hi Alistair, >> >> On 7/8/22, Alistair Francis wrote: >> >> >> > but I think that's just the way things go unfortunately. >> > >> > Hmm... That's a pain. So there is a bug in older kernels where

Re: [PATCH] hw/riscv: virt: pass random seed to fdt

On Fri, Jul 8, 2022 at 7:56 PM Jason A. Donenfeld wrote: > > Hi Alistair, > > On 7/8/22, Alistair Francis wrote: > > >> > but I think that's just the way things go unfortunately. > > > > Hmm... That's a pain. So there is a bug in older kernels where they > > won't boot if we specify this? > > > >

Minor tweak to wiki Linux build instructions.

On https://wiki.qemu.org/Hosts/Linux the list of recommended packages currently is a mix of RedHat and Debian names.  I suggest the following instead: Recommended additional packages Package names are for Debian(RedHat).* git-email, used for sending patches* libsdl2-dev(libsdl2-devel), need

[PATCH v2 11/11] MAINTAINERS: add myself as the maintainer for acpi biosbits pytests

I wrote the biosbits test framework, the pytest for testing QEMU with biosbits and all the related changes. Making myself as the maintainer for biosbits related files and test scripts. Signed-off-by: Ani Sinha --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b

[PATCH v2 06/11] acpi/tests/bits: disable smilatency test since it does not pass everytime

smilatency test is latency sensitive and does not pass deterministically when run in QEMU environment under biosbits. Disable the test suite for now. Example failure: SMI latency test Warning: touching the keyboard can affect the results of this test. Starting test. Wait here, I will be

[PATCH v2 05/11] acpi/tests/bits: add SPDX license identifiers for bios bits smilatency tests

Added the SPDX license identifier based on the following output from the licensee tool for bios bits: $ licensee detect bits/ License:NOASSERTION Matched files: COPYING COPYING: Content hash: 7a1fdfa894728ea69588977442c92073aad69e50 License: NOASSERTION Closest non-matching l

[PATCH v2 08/11] acpi/tests/bits: add biosbits config file for running bios tests

This change adds initial biosbits config file that instructs biosbits to run bios test suits in batch mode. Additionally acpi and smbios structures are also dumped. Signed-off-by: Ani Sinha --- .../pytest/acpi-bits/bits-config/bits-cfg.txt | 18 ++ tests/pytest/acpi-bits/bits-co

[PATCH v2 07/11] acpi/tests/bits: add python test that exercizes QEMU bios tables using biosbits

This change adds python based test environment that can be used to run pytest from within a virtual environment. A bash script sets up a virtual environment and then runs the python based tests from within that environment. All dependent python packages are installed in the virtual environment usin

[PATCH v2 09/11] acpi/tests/bits: add a README file describing bits pytests

A README file is added describing the directory structure and the purpose of every file it contains. It also describes the test added, how to add new tests, make changes to existing tests or bits config files or regenerate the bios bits software binaries. Signed-off-by: Ani Sinha --- tests/pytes

[PATCH v2 03/11] acpi/tests/bits: disable acpi PSS tests that are failing in biosbits

PSS tests in acpi test suite seems to be failing in biosbits. This is because the test is unable to find PSS support in QEMU bios. Let us disable them for now so that make check does not fail. We can fix the tests and re-enable them later. Example failure: ACPI _PSS (Pstate) table conformanc

[PATCH v2 04/11] acpi/tests/bits: add smilatency test suite from bits in order to disable it

smilatency tests does not reliably pass every time it is run from QEMU. This change adds the test file unchanged from bits so that the next change can disable the test. Signed-off-by: Ani Sinha --- tests/pytest/acpi-bits/bits-tests/meson.build | 2 +- .../pytest/acpi-bits/bits-tests/smilatency

[PATCH v2 10/11] pytest: add pytest to the meson build system

Integrate the pytest framework with the meson build system. This will make meson run all the pytests under the pytest directory. Signed-off-by: Ani Sinha --- tests/Makefile.include | 4 +++- tests/meson.build| 1 + tests/pytest/meson.build | 49 +++

[PATCH v2 01/11] acpi/tests/bits: initial commit of test scripts that are run by biosbits

This is initial commit of cpuid, acpi and smbios python test scripts for biosbits to execute. No change has been made to them from the original code written by the biosbits author Josh Triplett. They are required to be installed into the bits iso file and then run from within the virtual machine bo

[PATCH v2 02/11] acpi/tests/bits: add SPDX license identifiers for bios bits tests

Added the SPDX license identifiers based on the following output from the licensee tool for bios bits: $ licensee detect bits/ License:NOASSERTION Matched files: COPYING COPYING: Content hash: 7a1fdfa894728ea69588977442c92073aad69e50 License: NOASSERTION Closest non-matching

[PATCH v2 00/11] Introduce new acpi/smbios python tests using biosbits

Changelog: v2: - a new class of python based tests introduced that is separate from avocado tests or qtests. Can be run by using "make check-pytest". - acpi biosbits tests are the first tests to use pytest environment. - bios bits tests now download the bits binary archives from a remote r

Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c

在 2022/7/10 下午7:04, Frédéric Pétrot 写道: For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Frédéric Pé

[PATCH] util/aio: Defer disabling poll mode as long as possible

When we measure FIO read performance (cache=writethrough, bs=4k, iodepth=64) in VMs, ~80K/s notifications (e.g., EPT_MISCONFIG) are observed from guest to qemu. It turns out those frequent notificatons are caused by interference from worker threads. Worker threads queue bottom halves after complet

[PATCH v2] target/riscv: fix shifts shamt value for rv128c

For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Frédéric Pétrot --- target/riscv/insn16.decode | 7 +

[PATCH] Add support for SMBIOS type 8 (Port Connector Information)

This patch adds support for SMBIOS type 8 to qemu. internal_reference: internal reference designator external_reference: external reference designator connector_type: hex value for port connector type (see SMBIOS 7.9.2) port_type: hex value for port type (see SMBIOS 7.9.3) After studying variou

[PATCH] target/riscv: move zmmul out of the experimental properties

- Zmmul is ratified and is now version 1.0 Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..6301871fdf 100644 --- a/target/riscv/cpu.c +++

[PATCH 0/6] Improve the U/S/H extension related check

This patchset tries to improve the U/S/H related check: * add check for the supported privilege modes conbinations: only supporting M, S mode is not a suggested combination * add check for "H extension depends on I extension" * add check for csrs only existed when U mode is supported * fix and simp

[PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check

Just add 1 to the effective privledge level when in HS mode, then reuse the check 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege level related check in hmode. Then, hmode will only check whether H extension is supported. when accessing Hypervior CSRs: 1) if access f

[PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table

- line over 80 characters will trigger warning when running checkpatch Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 362 - 1 file changed, 196 insertions(+), 166 deletions(-) diff --git a/target/riscv/csr.c b/target/

[PATCH 4/6] target/riscv: add check for csrs existed with U extension

- add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9bda1ff993..0d8

[PATCH 2/6] target/riscv: H extension depends on I extension

- add check for "H depends on an I base integer ISA with 32 x registers" Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dad6906bc..4e40f26e13 100644 --- a/targe

[PATCH 5/6] target/riscv: fix checks in hmode/hmode32

- It seems that there is no explicitly description about whether the Hypervisor CSRs requires S extension - Csrs only existed in RV32 will not trigger virtual instruction fault when not in RV32 Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/csr.c | 9 ++--- 1 file ch

[PATCH 1/6] target/riscv: add check for supported privilege modes conbinations

- There are 3 suggested privilege modes conbinations listed in the spec: 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..0dad