On Sun, Jul 10, 2022 at 6:24 PM Weiwei Li <liwei...@iscas.ac.cn> wrote:
>
> - add check for "H depends on an I base integer ISA with 32 x registers"
>
> Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0dad6906bc..4e40f26e13 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -642,6 +642,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
> + error_setg(errp,
> + "H depends on an I base integer ISA with 32 x
> registers");
> + return;
> + }
> +
> if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> --
> 2.17.1
>
>
