> On May 31, 2022, at 2:45 PM, Alex Williamson
> wrote:
>
> On Tue, 31 May 2022 22:03:14 +0100
> Stefan Hajnoczi wrote:
>
>> On Tue, 31 May 2022 at 21:11, Alex Williamson
>> wrote:
>>>
>>> On Tue, 31 May 2022 15:01:57 +
>>> Jag Raman wrote:
>>>
> On May 25, 2022, at 10:53 AM, Ste
On 5/31/22 23:49, Daniel Henrique Barboza wrote:
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is
On 5/31/22 21:07, Philippe Mathieu-Daudé wrote:
On 31/5/22 11:19, Cédric Le Goater wrote:
On 5/30/22 21:37, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Rebase/respin of Cédric RFC:
https://lore.kernel.org/qemu-devel/20220318132824.1134400-1-...@kaod.org/
(sorry it took me so lo
On 6/1/22 11:57, Sam Li wrote:
> Hi Stefan,
>
> Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
>
>
>>
>> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
>>>
>>> Hi everyone,
>>> I'm Sam Li, working on the Outreachy project which is to add zoned
>>> device support to QEMU's virtio-blk emulation.
>>>
>>> Fo
On Tue, May 31, 2022 at 8:36 PM Julia Suvorova wrote:
>
> On Tue, May 31, 2022 at 3:14 PM Ani Sinha wrote:
> >
> > On Tue, May 31, 2022 at 5:53 PM Julia Suvorova wrote:
> > >
> > > On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
> > > >
> > > >
> > > >
> > > > On Fri, 27 May 2022, Julia Suvoro
On Fri, May 27, 2022 at 10:27 PM Julia Suvorova wrote:
>
> The new test is run with a large number of cpus and checks if the
> core_count field in smbios_cpu_test (structure type 4) is correct.
>
> Choose q35 as it allows to run with -smp > 255.
>
> Signed-off-by: Julia Suvorova
Reviewed-by: Ani
On Wed, May 25, 2022 at 7:54 PM Tsukasa OI wrote:
>
> This commit reorganizes riscv_cpu_properties for clarity.
>
> Signed-off-by: Tsukasa OI
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 64 +++---
> 1 file changed, 37 insertions
On Fri, May 27, 2022 at 6:35 AM Atish Patra wrote:
>
> fw_cfg DT node is generated after the create_fdt without any check
> if the DT is being loaded from the commandline. This results in
> FDT_ERR_EXISTS error if dtb is loaded from the commandline.
>
> Generate fw_cfg node only if the DT is not l
>
> From: Alistair Francis
>
> Since commit ad40be27 "target/riscv: Support start kernel directly by KVM" we
> have been overflowing the addr_config on "M,MS..."
> configurations, as reported
> https://gitlab.com/qemu-project/qemu/-/issues/1050.
>
> This commit changes the loop in sifive_plic_
Hi Stefan,
Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
>
> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
> >
> > Hi everyone,
> > I'm Sam Li, working on the Outreachy project which is to add zoned
> > device support to QEMU's virtio-blk emulation.
> >
> > For the first goal, adding QEMU block layer A
On Tue, May 31, 2022 at 7:28 PM Vitaly Cheptsov wrote:
>
> Hi Jason,
>
> This patch fixes socket communication with QEMU -> host and QEMU <--> QEMU on
> macOS, which was originally impossible due to QEMU and host program having to
> bind to the same ip/port in a way not supported by BSD sockets.
On 5/31/22 12:08, Jue Wang wrote:
On Mon, May 30, 2022 at 8:49 AM Peter Xu wrote:
On Mon, May 30, 2022 at 07:33:35PM +0800, zhenwei pi wrote:
A VM uses RAM of 2M huge page. Once a MCE(@HVAy in [HVAx,HVAz)) occurs, the
2M([HVAx,HVAz)) of hypervisor becomes unaccessible, but the guest poisons 4
On Fri, May 27, 2022 at 6:35 AM Atish Patra wrote:
>
> fw_cfg DT node is generated after the create_fdt without any check
> if the DT is being loaded from the commandline. This results in
> FDT_ERR_EXISTS error if dtb is loaded from the commandline.
>
> Generate fw_cfg node only if the DT is not l
On Wed, May 25, 2022 at 1:56 AM Andrea Bolognani wrote:
>
> On Mon, May 23, 2022 at 08:16:40PM -0700, Atish Patra wrote:
> > On Sun, May 22, 2022 at 10:59 PM Alistair Francis
> > wrote:
> > > On Wed, May 18, 2022 at 4:38 PM Atish Patra wrote:
> > > > 1. virt machine is not well documented and a
On Tue, May 31, 2022 at 1:08 PM Weiwei Li wrote:
>
> - includes all multiplication operations for M extension
The commit message should be full sentences and understandable outside
of the commit title.
I changed the commit message to:
Add support for the zmmul extension v0.1. This extension in
On 5/31/22 20:08, Gonglei (Arei) wrote:
-Original Message-
From: zhenwei pi [mailto:pizhen...@bytedance.com]
Sent: Tuesday, May 31, 2022 9:48 AM
To: Gonglei (Arei)
Cc: qemu-devel@nongnu.org; m...@redhat.com;
virtualizat...@lists.linux-foundation.org; helei.si...@bytedance.com;
berra..
From: Alistair Francis
There are currently two types of RISC-V CPUs:
- Generic CPUs (base or any) that allow complete custimisation
- "Named" CPUs that match existing hardware
Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.
We originally e
From: Alistair Francis
Since commit ad40be27 "target/riscv: Support start kernel directly by
KVM" we have been overflowing the addr_config on "M,MS..."
configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.
This commit changes the loop in sifive_plic_create() from iterat
> -Original Message-
> From: Alex Bennée
> Sent: Tuesday, May 31, 2022 10:46 PM
> To: Liu, Changpeng
> Cc: qemu-devel@nongnu.org
> Subject: Re: [PATCH 1/2] hw/virtio/vhost-user: don't use uninitialized
> variable
>
>
> Changpeng Liu writes:
>
> > Variable `vdev` in `struct vhost_de
Hi David,
On Mon, May 30, 2022 at 9:19 AM David Hildenbrand wrote:
>
> On 27.04.22 22:51, Tong Zhang wrote:
> > assert(dbs->acb) is meant to check the return value of io_func per
> > documented in commit 6bee44ea34 ("dma: the passed io_func does not
> > return NULL"). However, there is a chance t
The var is being initialized using the TYPE_PNV_PHB_ROOT_PORT value for
all values of phb->version.
Remove it and call pnv_phb_attach_root_port() using
TYPE_PNV_PHB_ROOT_PORT directly.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 6 +-
1 file changed, 1 insertion(+), 5
The attribute is unused.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4_pec.c | 2 --
include/hw/pci-host/pnv_phb4.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 785b778396..8f11e077c2 100644
--- a/hw/pci-
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
This patch just flips the switch.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c | 2 +-
hw/ppc/pnv.c | 2 ++
2 files changed,
The unified pnv-phb-root-port can be used instead. The phb4-root-port
device isn't exposed to the user in any official QEMU release so there's
no ABI breakage in removing it.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 4 +-
hw/pci-host/pnv_phb4.c | 100
Similar to what we already did for the PnvPHB3 device, let's add a
helper to init the bus when using a PnvPHB4. This helper will be used by
PnvPHb when PnvPHB4 turns into a backend.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 2 ++
hw/pci-host/pnv_phb4.c
It's unused.
Signed-off-by: Daniel Henrique Barboza
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 61a0cb9989..20aa4819d3 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pc
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main difference between the PHB3 and PHB4 root ports is that
pnv-phb4-root-port has the pnv_phb4_root_port_
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb.c | 10 --
hw/pci-host/pnv_phb3.c
Let's reintroduce the powernv8 bits of the code what was removed in
commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices",
allowing us to enable user creatable pnv-phb devices for the powernv8
machine.
The difference is that this time we're adding support for a PnvPHB
device that is
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the
PCI bus is going to be initialized by the PnvPHB parent. Functions that
needs to access the bus via a PnvPHB4 object can do so via the
phb4->phb_base pointer.
pnv_phb4_pec now creates a PnvPHB object.
The powernv9 machine class
To enable user creatable PnvPHB devices for powernv9 we'll revert the
powernv9 related changes made in 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices".
This change alone isn't enough to enable user creatable devices for powernv10
due to how pnv_phb4_get_pec() currently works. For now
We need a handful of changes that needs to be done in a single swoop to
turn PnvPHB3 into a PnvPHB backend.
In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and
will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a
couple of instances in pnv_phb3.c that needs to
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_phb4.c |
The PnvPHB device is going to be the base device for all other powernv
PHBs. It consists of a device that has the same user API as the other
PHB, namely being a PCIHostBridge and having chip-id and index
properties. It also has a 'backend' pointer that will be initialized
with the PHB implementatio
The ics and pic related functions in pnv.c relies in the fact that the
child device of the chip is always a PnvPHB3 object. This will change in
the next patches, and the PHB3 will be a child of another device that
will be attached to the pnv8 chip.
To ease the amount of changes done later, on let'
The PnvPHB3 bus init consists of initializing the pci_io and pci_mmio
regions, registering it via pci_register_root_bus() and then setup the
iommu.
We'll want to init the bus from outside pnv_phb3.c when the bus is
removed from the PnvPHB3 device and put into a new parent PnvPHB device.
The new pn
Hi,
This v2 is considerable different from the first version due to the
review provided by Mark Cave-Ayland.
We're now preserving all PnvPHB3/4/5 implementations already in place.
The PnvPHB device now acts as a base/proxy of the existing PHBs, which
are turned into backends of the base PnvPHB de
On Tue, 31 May 2022 22:03:14 +0100
Stefan Hajnoczi wrote:
> On Tue, 31 May 2022 at 21:11, Alex Williamson
> wrote:
> >
> > On Tue, 31 May 2022 15:01:57 +
> > Jag Raman wrote:
> >
> > > > On May 25, 2022, at 10:53 AM, Stefan Hajnoczi
> > > > wrote:
> > > >
> > > > On Tue, May 24, 2022 at
On 5/31/22 11:05, Laurent Vivier wrote:
Hmm. That will completely hide trapcc -- you should have seen the new test case fail
(and if not, the test case needs fixing).
I ran "make check", thinking the test is run, and saw no failure...
and if I run "make check-tcg", I have:
make: Nothing to
Whether or not VSEIP is pending isn't reflected in env->mip and must
instead be determined from hstatus.vgein and hgeip. As a result a
CPU in WFI won't wake on a VSEIP, which violates the WFI behavior as
specified in the privileged ISA. Just use riscv_cpu_all_pending()
instead, which already accoun
On Tue, 31 May 2022 at 21:11, Alex Williamson
wrote:
>
> On Tue, 31 May 2022 15:01:57 +
> Jag Raman wrote:
>
> > > On May 25, 2022, at 10:53 AM, Stefan Hajnoczi wrote:
> > >
> > > On Tue, May 24, 2022 at 11:30:32AM -0400, Jagannathan Raman wrote:
> > >> Forward remote device's interrupts to
On 31/05/2022 10:22, Damien Hedde wrote:
On 5/31/22 10:00, Mark Cave-Ayland wrote:
On 30/05/2022 15:05, Damien Hedde wrote:
On 5/30/22 12:25, Peter Maydell wrote:
On Mon, 30 May 2022 at 10:50, Damien Hedde wrote:
TYPE_SYS_BUS_DEVICE also comes with reset support.
If a device is on not on a
Dropping this.
New series with suggested changes from reviewers can be found at
https://lists.nongnu.org/archive/html/qemu-devel/2022-05/msg06245.html
On Thu, Apr 28, 2022 at 04:13:01PM -0700, Dongwon Kim wrote:
> This patch series introduces two new gtk optional parameters, monitor
> and detach-a
New integer array parameter, 'monitor' is for specifying the target
displays where individual QEMU windows are placed upon launching.
The array contains a series of numbers representing the monitor where
QEMU windows are placed.
Numbers in the array are mapped to QEMU windows like,
[1st detached
This patch seires is for adding some useful features for the guest os with
multi-displays. First patch is to make all of guest displays visible
when guest os is launched using "detach". Second patch is for providing
a method to assign each guest display to specific physical monitor,
which would be
Detaching any addtional guest displays in case there are multiple
displays assigned to the guest OS (e.g. max_outputs=n) so that
all of them are visible upon lauching.
Cc: Daniel P. Berrangé
Cc: Markus Armbruster
Cc: Philippe Mathieu-Daudé
Cc: Paolo Bonzini
Cc: Gerd Hoffmann
Cc: Vivek Kasired
When a disk is hotplugged, QEMU reports a VIRTIO_SCSI_EVT_RESET_RESCAN
event, but does not send the "REPORTED LUNS CHANGED" sense data. This
does not conform to Section 5.6.6.3 of the VirtIO specification, which
states "Events will also be reported via sense codes..." SCSI layer on
Solaris depends
On Tue, 31 May 2022 15:01:57 +
Jag Raman wrote:
> > On May 25, 2022, at 10:53 AM, Stefan Hajnoczi wrote:
> >
> > On Tue, May 24, 2022 at 11:30:32AM -0400, Jagannathan Raman wrote:
> >> Forward remote device's interrupts to the guest
> >>
> >> Signed-off-by: Elena Ufimtseva
> >> Signed-o
On Thu, May 19, 2022 at 8:41 AM Chao Peng wrote:
>
> Introduce a new memfd_create() flag indicating the content of the
> created memfd is inaccessible from userspace through ordinary MMU
> access (e.g., read/write/mmap). However, the file content can be
> accessed via a different mechanism (e.g. K
On 31/5/22 11:19, Cédric Le Goater wrote:
On 5/30/22 21:37, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Rebase/respin of Cédric RFC:
https://lore.kernel.org/qemu-devel/20220318132824.1134400-1-...@kaod.org/
(sorry it took me so long guys...)
Pushed at https://gitlab.com/philmd/
Add a test to check for overflow conditions in s390x.
This patch is based on the following patches :
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
Signed-off-by: Gautam Agrawal
---
Changes since v1:
- Corrected the
On 31/05/2022 14:27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrangé
Cc: Thomas Huth
Cc: Cédric Le Goater
Cc: Dani
On Mon, May 30, 2022 at 3:33 AM Thomas Huth wrote:
>
> On 26/05/2022 02.09, John Snow wrote:
> > This is needed to be able to add a venv-building step to 'make check';
> > the clang-user job in particular needs this to be able to run
> > check-unit.
> >
> > Signed-off-by: John Snow
> > ---
> >
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h |
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 5 ++
target/riscv/cpu_b
Historically, The mtime/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Reviewed-by: Anup Patel
Reviewed-by: Alistair Francis
This series implements Sstc extension[1] which was ratified recently.
The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
on top of upstream commit (faee5441a038).
The series can also be found at
https://github.
Le 31/05/2022 à 16:59, Richard Henderson a écrit :
On 5/31/22 01:01, Laurent Vivier wrote:
Le 27/05/2022 à 18:48, Richard Henderson a écrit :
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/cpu.h
> On May 30, 2022, at 8:29 AM, Philippe Mathieu-Daudé via
> wrote:
>
> On 4/5/22 00:47, Peter Delevoryas wrote:
>>> On May 3, 2022, at 2:35 PM, Cédric Le Goater wrote:
>>>
>>> On 5/3/22 22:44, Peter Delevoryas wrote:
Hey everyone,
I'm submitting another Facebook (Meta Platforms) ma
On 5/31/22 19:27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrangé
Cc: Thomas Huth
Cc: Cédric Le Goater
Cc: Daniel
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrangé
Cc: Thomas Huth
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Fabiano Rosas
Signed-off-by:
On Tue, May 31, 2022 at 6:18 AM Miaoqian Lin wrote:
> g_strdup_printf() allocated memory for path, we should free it with
> g_free() when no longer needed.
>
> Signed-off-by: Miaoqian Lin
>
Reviewed-by: Hao Wu
> ---
> tests/qtest/npcm7xx_pwm-test.c | 3 +++
> 1 file changed, 3 insertions(+)
>
On 5/31/22 08:14, Peter Maydell wrote:
The FEAT_DoubleFault extension adds the following:
* All external aborts on instruction fetches and translation table
walks for instruction fetches must be synchronous. For QEMU this
is already true.
* SCR_EL3 has a new bit NMEA which disables
On Tue, May 31, 2022 at 04:51:47PM +0200, Julia Suvorova wrote:
> In the ACPI specification [1], the 'unarmed' bit is set when a device
> cannot accept a persistent write. This means that when a memdev is
> read-only, the 'unarmed' flag must be turned on. The logic is correct,
> just changing the e
The FEAT_DoubleFault extension adds the following:
* All external aborts on instruction fetches and translation table
walks for instruction fetches must be synchronous. For QEMU this
is already true.
* SCR_EL3 has a new bit NMEA which disables the masking of SError
interrupts by PSTAT
On Tue, May 31, 2022 at 3:14 PM Ani Sinha wrote:
>
> On Tue, May 31, 2022 at 5:53 PM Julia Suvorova wrote:
> >
> > On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
> > >
> > >
> > >
> > > On Fri, 27 May 2022, Julia Suvorova wrote:
> > >
> > > > The new test is run with a large number of cpus and
> On May 25, 2022, at 10:53 AM, Stefan Hajnoczi wrote:
>
> On Tue, May 24, 2022 at 11:30:32AM -0400, Jagannathan Raman wrote:
>> Forward remote device's interrupts to the guest
>>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
On 5/31/22 01:01, Laurent Vivier wrote:
Le 27/05/2022 à 18:48, Richard Henderson a écrit :
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754
Reviewed-by: Laurent Vivier
Signed-off-by: Richard Henderson
---
target/m68k/cpu.h | 2 ++
linux-user/m68k/cpu_loop.c | 1 +
tar
In the ACPI specification [1], the 'unarmed' bit is set when a device
cannot accept a persistent write. This means that when a memdev is
read-only, the 'unarmed' flag must be turned on. The logic is correct,
just changing the error message.
[1] ACPI NFIT NVDIMM Region Mapping Structure "NVDIMM Sta
On Tue, 31 May 2022 at 15:28, Richard Henderson
wrote:
>
> On 5/31/22 05:15, Peter Maydell wrote:
> > On Fri, 27 May 2022 at 19:07, Richard Henderson
> > wrote:
> >>
> >> We don't need to constrain the value set in zcr_el[1],
> >> because it will be done by sve_zcr_len_for_el.
> >>
> >> Signed-of
Changpeng Liu writes:
> Variable `vdev` in `struct vhost_dev` will not be ready
> until start the device, so let's not use it for the error
> output here.
This seems to be one of the areas where vhost_user_backend_dev_init and
vhost_dev_init do things differently. Is there any particular reaso
On 5/31/22 04:42, Peter Maydell wrote:
The architectural feature RASv1p1 introduces the following new
features:
* new registers ERXPFGCDN_EL1, ERXPFGCTL_EL1 and ERXPFGF_EL1
* new bits in the fine-grained trap registers that control traps
for these new registers
* new trap bits HCR_EL2.F
On 5/31/22 05:07, Peter Maydell wrote:
On Mon, 23 May 2022 at 22:07, Richard Henderson
wrote:
We often have this value already handy in the caller.
Signed-off-by: Richard Henderson
True, but it makes the function clunkier to use. Does it really
make a noticeable difference to performance ?
On 5/31/22 05:04, Peter Maydell wrote:
On Mon, 23 May 2022 at 21:58, Richard Henderson
wrote:
Read this value once in the main function, and pass it
around between the subroutines.
Signed-off-by: Richard Henderson
---
What's the benefit from doing this ?
Just trying to reduce the number
On 5/31/22 05:15, Peter Maydell wrote:
On Fri, 27 May 2022 at 19:07, Richard Henderson
wrote:
We don't need to constrain the value set in zcr_el[1],
because it will be done by sve_zcr_len_for_el.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 +--
1 file changed, 1 insertion(+)
On Tue, May 31, 2022 at 01:47:07PM +0200, Claudio Fontana wrote:
> the code in pcibus_get_fw_dev_path contained the potential for a
> stack buffer overflow of 1 byte, potentially writing to the stack an
> extra NUL byte.
>
> This overflow could happen if the PCI slot is >= 0x1000,
> and the PC
On Tue, May 31, 2022 at 5:53 PM Julia Suvorova wrote:
>
> On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
> >
> >
> >
> > On Fri, 27 May 2022, Julia Suvorova wrote:
> >
> > > The new test is run with a large number of cpus and checks if the
> > > core_count field in smbios_cpu_test (structure ty
Hi Stefan,
On 4/5/22 13:04, Stefan Pejic wrote:
nanoMips ISA support in QEMU is actively used by MediaTek and is
planned to be maintained and potentially extended by MediaTek in
future.
Un-orphan nanoMips ISA support in QEMU by setting a mainainer from
MediaTek and remove deprecation notes from
On Tue, May 31, 2022 at 6:15 PM Claudio Fontana wrote:
>
> On 5/31/22 14:26, Ani Sinha wrote:
> > On Tue, May 31, 2022 at 5:20 PM Claudio Fontana wrote:
> >>
> >> the code in pcibus_get_fw_dev_path contained the potential for a
> >> stack buffer overflow of 1 byte, potentially writing to the stac
On Fri, 27 May 2022 at 19:19, Richard Henderson
wrote:
>
> We will need this over in sme_helper.c.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/vec_internal.h | 2 ++
> target/arm/vec_helper.c | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/vec_
On Fri, 27 May 2022 at 19:11, Richard Henderson
wrote:
>
> Put the inline function near the array declaration.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/vec_internal.h | 8 +++-
> target/arm/sve_helper.c | 9 -
> 2 files changed, 7 insertions(+), 10 deletions(-)
>
> d
Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cx
On Fri, 27 May 2022 at 19:12, Richard Henderson
wrote:
>
> Export all of the support functions for performing bulk
> fault analysis on a set of elements at contiguous addresses
> controlled by a predicate.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On 5/31/22 14:26, Ani Sinha wrote:
> On Tue, May 31, 2022 at 5:20 PM Claudio Fontana wrote:
>>
>> the code in pcibus_get_fw_dev_path contained the potential for a
>> stack buffer overflow of 1 byte, potentially writing to the stack an
>> extra NUL byte.
>>
>> This overflow could happen if the PCI
On Sat, May 28, 2022 at 6:34 AM Ani Sinha wrote:
>
>
>
> On Fri, 27 May 2022, Julia Suvorova wrote:
>
> > In order to use the increased number of cpus, we need to bring smbios
> > tables in line with the SMBIOS 3.0 specification. This allows us to
> > introduce core_count2 which acts as a duplicat
On Fri, 27 May 2022 at 19:17, Richard Henderson
wrote:
>
> Move the data to vec_helper.c and the inline to vec_internal.h.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
Paolo,
can you pick this up if it looks fine, please?
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
> Igor Mammedov (2):
> x86: cpu: make sure number of addressable IDs for processor cores
> meets the spec
> x86: cpu: fixup number of addressable IDs for logical processors
>
On Sat, May 28, 2022 at 7:22 AM Ani Sinha wrote:
>
>
>
> On Fri, 27 May 2022, Julia Suvorova wrote:
>
> > The new test is run with a large number of cpus and checks if the
> > core_count field in smbios_cpu_test (structure type 4) is correct.
> >
> > Choose q35 as it allows to run with -smp > 255.
On Fri, 27 May 2022 at 19:18, Richard Henderson
wrote:
>
> Begin creation of sve_ldst_internal.h by moving the primitives
> that access host and tlb memory.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, May 30, 2022 at 8:11 AM Ani Sinha wrote:
>
> On Fri, May 27, 2022 at 10:27 PM Julia Suvorova wrote:
> >
> > Introduce the 64-bit entry point. Since we no longer have a total
> > number of structures, stop checking for the new ones at the EOF
> > structure (type 127).
> >
> > Signed-off-by
On Tue, May 31, 2022 at 5:20 PM Claudio Fontana wrote:
>
> the code in pcibus_get_fw_dev_path contained the potential for a
> stack buffer overflow of 1 byte, potentially writing to the stack an
> extra NUL byte.
>
> This overflow could happen if the PCI slot is >= 0x1000,
> and the PCI functi
On Fri, 27 May 2022 at 19:11, Richard Henderson
wrote:
>
> This will be used for both Normal and Streaming SVE, and the value
> does not necessarily come from ZCR_ELx. While we're at it, emphasize
> the units in which the value is returned.
>
> Patch produced by
> git grep -l sve_zcr_len_for_
On Fri, 27 May 2022 at 19:13, Richard Henderson
wrote:
>
> The ARM pseudocode function NVL uses this predicate now,
> and I think it's a bit clearer. Simplify the pseudocode
> condition by noting that IsInHost is always false for EL1.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Mayd
On Fri, 27 May 2022 at 19:14, Richard Henderson
wrote:
>
> Use the function instead of the array directly.
>
> Because the function performs its own masking, via the uint8_t
> parameter, we need to nothing extra within the users: the bits
"to do"
> above the first 2 (_uh) or 4 (_uw) will be disc
> -Original Message-
> From: zhenwei pi [mailto:pizhen...@bytedance.com]
> Sent: Tuesday, May 31, 2022 9:48 AM
> To: Gonglei (Arei)
> Cc: qemu-devel@nongnu.org; m...@redhat.com;
> virtualizat...@lists.linux-foundation.org; helei.si...@bytedance.com;
> berra...@redhat.com
> Subject: Re: R
On Fri, 27 May 2022 at 19:18, Richard Henderson
wrote:
>
> This (newish) ARM pseudocode function is easier to work with
> than open-coded tests for HCR_E2H etc. Use of the function
> will be staged into the code base in parts.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
tha
On Fri, 27 May 2022 at 19:07, Richard Henderson
wrote:
>
> We don't need to constrain the value set in zcr_el[1],
> because it will be done by sve_zcr_len_for_el.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --gi
On Mon, 23 May 2022 at 22:07, Richard Henderson
wrote:
>
> We often have this value already handy in the caller.
>
> Signed-off-by: Richard Henderson
True, but it makes the function clunkier to use. Does it really
make a noticeable difference to performance ?
thanks
-- PMM
On Fri, 27 May 2022 at 19:07, Richard Henderson
wrote:
>
> Use the digested vector length rather than the raw zcr_el[1] value.
>
> This fixes an incorrect return from do_prctl_set_vl where we didn't
> take into account the set of vector lengths supported by the cpu.
> It also prepares us for Strea
On Fri, 27 May 2022 at 19:06, Richard Henderson
wrote:
>
> With SME, the vector length does not only come from ZCR_ELx.
> Comment that this is either the SVE VL, or the Streaming SVE VL.
>
> Signed-off-by: Richard Henderson
> --
Reviewed-by: Peter Maydell
thanks
-- PMM
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