On Wed, May 11, 2022 at 10:56:02AM +0800, Jason Wang wrote:
On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
From: Longpeng
Supports vdpa-dev.
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5 +
hw/virtio/meson.build| 1 +
hw/virtio/vdpa-dev.c | 385 ++
On 11/05/2022 01.54, Murilo Opsfelder Araujo wrote:
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
Make devices configuration available in hmp-commands*.hx
Andrea Bolognani writes:
> On Tue, May 03, 2022 at 09:57:27AM +0200, Markus Armbruster wrote:
>> Andrea Bolognani writes:
>> > I still feel that 1) users of a language SDK will ideally not need to
>> > look at the QAPI schema or wire chatter too often
>>
>> I think the most likely point of conta
Hello Jamin,
(Adding a few people that could help with the review)
On 3/21/22 10:14, Jamin Lin wrote:
1. Add GPIO read/write trace event.
Do we really need the "DEVICE(s)->canonical_path" parameter ?
That would be patch 1.
2. Support GPIO index mode for write operation.
It did not support
在 2022/5/11 10:56, Jason Wang 写道:
On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
From: Longpeng
Supports vdpa-dev.
Signed-off-by: Longpeng
---
hw/virtio/Kconfig| 5 +
hw/virtio/meson.build| 1 +
hw/virtio/vdpa-dev.c | 385 ++
>From a previous thread:
On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert
wrote:
>
> Leo:
> Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY
> one I guess is the simpler one; I think Stefanha managed to find the
> liburing fix for the __kernel_timespec case, but that l
On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
>
> From: Longpeng
>
> Supports vdpa-dev.
>
> Signed-off-by: Longpeng
> ---
> hw/virtio/Kconfig| 5 +
> hw/virtio/meson.build| 1 +
> hw/virtio/vdpa-dev.c | 385 +++
> include/h
在 2022/3/17 下午3:47, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +++
target/riscv/vector_helper.c| 35 +
2 files changed, 33 insertions(+), 11 deletions(-)
在 2022/3/17 下午5:32, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 26 +++--
2 files changed, 25 insertions(+), 2 deletions(-)
Rev
在 2022/5/11 上午2:10, ~eopxd 写道:
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to a
在 2022/3/17 下午5:14, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 14 insertions(+)
Reviewed-by: Weiwei Li
Regards
在 2022/3/17 下午5:08, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
target/riscv/vector_helper.c| 26 +
2 files changed, 38 insertions(+)
Reviewed
在 2022/3/17 下午4:52, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
Reviewed-by: Weiwei Li
Regards,
Weiwei Li
diff --git a/targ
在 2022/3/17 下午4:46, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 10 ++
2 files changed, 11 insertions(+)
Reviewed-by: Weiwei Li
Regards,
W
在 2022/3/17 下午4:43, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 7 +++
2 files changed, 8 insertions(+)
Reviewed-by: Weiwei Li
Regards,
Weiwei L
在 2022/3/17 下午4:38, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c| 3 +++
2 files changed, 5 insertions(+)
Reviewed-by: Weiwei Li
Regards,
Weiwei Li
在 2022/3/17 下午3:26, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elem
在 2022/3/17 下午3:47, ~eopxd 写道:
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +++
target/riscv/vector_helper.c| 35 +
2 files changed, 33 insertions(+), 11 deletions(-)
Hi, Thomas.
On 5/10/22 04:24, Thomas Huth wrote:
On 06/05/2022 03.16, Murilo Opsfelder Araujo wrote:
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
Make d
On 5/10/22 10:28, Lucas Mateus Martins Araujo e Castro wrote:
On 08/05/2022 00:41, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 10c6d7ae43..348a898950 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@
On 5/10/22 13:46, Víctor Colombo wrote:
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo
---
v2: Add this patch
---
target/ppc/f
On 5/10/22 13:46, Víctor Colombo wrote:
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exceptio
On 5/10/22 13:46, Víctor Colombo wrote:
The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.
However, the following inconsistency was f
When CONFIG_MOS6522 is not set, building ppc64-softmmu target fails:
/usr/bin/ld: libqemu-ppc64-softmmu.fa.p/monitor_misc.c.o:(.data+0x1158):
undefined reference to `hmp_info_via'
Make devices configuration available in hmp-commands*.hx and check for
CONFIG_MOS6522.
Fixes: 409e9f7131e5 (mos
It is just a big if in the middle of the function, and we need two
functions anways.
Signed-off-by: Juan Quintela
---
migration/ram.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index a2489a2699..b3fa3d5d8f 1006
We are recalculating ram size continously, when we know that it don't
change during migration. Create a field in RAMState to track it.
Signed-off-by: Juan Quintela
---
migration/ram.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
in
Hi
Current migration code recalculates the amount of RAM each time that
is needed. This calculation requires RCU and other operations.
During migration we disable hot/unplug of memory, so we can store it.
Notice the times difference, and specially that ram_bytes_total()
don't appears anymore in
We were calling qemu_target_page_size() left and right.
Signed-off-by: Juan Quintela
---
migration/multifd.h | 4
migration/multifd-zlib.c | 12 +---
migration/multifd-zstd.c | 12 +---
migration/multifd.c | 18 --
4 files changed, 22 insertions(+)
This implements the zero page dection and handling.
Signed-off-by: Juan Quintela
---
Add comment for offset (dave)
Use local variables for offset/block to have shorter lines
---
migration/multifd.h | 5 +
migration/multifd.c | 41 +++--
2 files changed,
Current code asumes that all pages are whole. That is not true for
example for compression already. Fix it for creating a new field
->sent_bytes that includes it.
All ram_counters are used only from the migration thread, so we have
two options:
- put a mutex and fill everything when we sent it (
So we use multifd to transmit zero pages.
Signed-off-by: Juan Quintela
---
- Check zero_page property before using new code (Dave)
---
migration/ram.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/migration/ram.c b/migration/ram.c
index 0a
We are going to create a new function for multifd latest in the series.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
migration/ram.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 738769ba15..14269
In this version:
- document what protects each field in MultiFDRecv/SendParams
- calcule page_size once when we start the migration, and store it in
a field
- Same for page_count.
- rebase to latest
- minor improvements here and there
- test on huge memory machines
Command line for all the tests
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
---
migration/migration.h | 3 +++
hw/core/machine.c | 4 +++-
migration/migration.c | 11 +++
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/migration/migration.h b/migration/migration.h
index a863032
Signed-off-by: Juan Quintela
---
migration/ram.h | 1 +
migration/ram.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/migration/ram.h b/migration/ram.h
index 7b641adc55..aee08de2a5 100644
--- a/migration/ram.h
+++ b/migration/ram.h
@@ -66,6 +66,7 @@ int ram_load_postcopy(Q
Use of flags with respect to locking was incensistant. For the
sending side:
- it was set to 0 with mutex held on the multifd channel.
- MULTIFD_FLAG_SYNC was set with mutex held on the migration thread.
- Everything else was done without the mutex held on the multifd channel.
On the reception si
Reorder the structures so we can know if the fields are:
- Read only
- Their own locking (i.e. sems)
- Protected by 'mutex'
- Only for the multifd channel
Signed-off-by: Juan Quintela
---
migration/multifd.h | 86 +++--
1 file changed, 51 insertions(+), 35
This patch adds counters and similar. Logic will be added on the
following patch.
Signed-off-by: Juan Quintela
---
Added counters for duplicated/non duplicated pages.
Removed reviewed by from David.
Add total_zero_pages
---
migration/multifd.h| 17 -
migration/multifd.c
Signed-off-by: Juan Quintela
---
migration/ram.h | 2 ++
migration/ram.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/migration/ram.h b/migration/ram.h
index ded0a3a086..7b641adc55 100644
--- a/migration/ram.h
+++ b/migration/ram.h
@@ -65,6 +65,8 @@ int ram_load_postcopy(
We do the send_prepare() and the fill of the head packet without the
mutex held. It will help a lot for compression and later in the
series for zero pages.
Notice that we can use p->pages without holding p->mutex because
p->pending_job == 1.
Signed-off-by: Juan Quintela
---
migration/multifd.h
We were recalculating it left and right. We plan to change that
values on next patches.
Signed-off-by: Juan Quintela
---
migration/multifd.h | 4
migration/multifd.c | 7 ---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/migration/multifd.h b/migration/multifd.h
index
On Mon, 9 May 2022 19:36:14 +0200
Laurent Vivier wrote:
> Copied from socket netdev file and modified to use SocketAddress
> to be able to introduce new features like unix socket.
>
> "udp" and "mcast" are squashed into dgram, multicast is detected
> according to the IP address type.
> "listen"
On Mon, 9 May 2022 19:36:16 +0200
Laurent Vivier wrote:
> dgram_dst is a sockaddr_in structure. To be able to use it with
> unix socket, use a pointer to a generic sockaddr structure.
>
> Signed-off-by: Laurent Vivier
> ---
> net/socket-ng.c | 76 ++
On Mon, 9 May 2022 19:36:13 +0200
Laurent Vivier wrote:
> Signed-off-by: Laurent Vivier
> ---
> include/qemu/sockets.h | 2 ++
> net/net.c | 62 ++
> 2 files changed, 34 insertions(+), 30 deletions(-)
>
> diff --git a/include/qemu/sockets.
On Mon, May 9, 2022 at 10:20 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> From: Philippe Mathieu-Daudé
>
> Except hw/core/irq.c which implements the forward-declared opaque
> qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not
> using the typedef. Fix this
The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.
However, the following inconsistency was found when comparing results
from the hardw
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo
---
v2: Add this patch
---
target/ppc/fpu_helper.c | 112
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exception is set
XX <- 1
...
FI is set to 1
...
""
Hello everyone,
The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
One could think this means that, if an instruction is said to modify
the FPSCR register, the bit FI should be cleared. This is what QEMU
does today.
This is not, however, what the real hardware appears to do. It look
On 5/10/22 14:34, Lucas Mateus Martins Araujo e Castro wrote:
On 27/04/2022 17:51, Daniel Henrique Barboza wrote:
On 4/27/22 03:42, Joel Stanley wrote:
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
---
MMA support for TCG is on the list so I think it makes sense
According to our "Supported build platforms" policy, we now do not support
Ubuntu 18.04 anymore. Remove the related files and entries from our CI.
Signed-off-by: Thomas Huth
---
Seems like nobody touched the 18.04-based tests/vm/ubuntu* files in a
very long time, so I assume these are not used
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 26 +++--
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 14 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/in
From: eopXD
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibi
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 10 ++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_
From: Yueh-Ting (eop) Chen
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are m
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/vector_helper.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 9bb259586d..4e48c92617
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c| 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/tra
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
target/riscv/vector_helper.c| 26 +
2 files changed, 38 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c
According to v-spec, mask agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of mask policies, QEMU should be able to simulate the mask
agnostic behavior as "set mask elements' bits to all 1s".
There are multiple possibility for agnos
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c| 7 +++
2 files changed, 8 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/
From: Yueh-Ting (eop) Chen
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 +++
target/riscv/vector_helper.c| 35 +
2 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn_trans
On Tue, May 10, 2022 at 01:37:50PM -0400, Andrea Bolognani wrote:
> On Mon, May 09, 2022 at 12:21:10PM +0200, Victor Toso wrote:
> > On Tue, Apr 19, 2022 at 11:12:28AM -0700, Andrea Bolognani wrote:
> > > Based on the example you have in the README and how commands are
> > > defined, invoking (a si
Thanks Richard! I have fixed it following your advice:
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 528c30c9a2..acd2548e9b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -808,9 +808,13 @@
On Thu, May 5, 2022 at 5:28 AM Paolo Bonzini wrote:
>
> On 5/5/22 10:51, Kevin Wolf wrote:
> > If not, I guess it would be enough if iotests just checks that the venv
> > exists and all of the dependencies are there in the right version and
> > error out if not, telling the user to run 'make check
On Mon, May 09, 2022 at 12:21:10PM +0200, Victor Toso wrote:
> On Tue, Apr 19, 2022 at 11:12:28AM -0700, Andrea Bolognani wrote:
> > Based on the example you have in the README and how commands are
> > defined, invoking (a simplified version of) the trace-event-get-state
> > command would look like
On 27/04/2022 17:51, Daniel Henrique Barboza wrote:
On 4/27/22 03:42, Joel Stanley wrote:
These are new hwcap bits added for power10.
Signed-off-by: Joel Stanley
---
MMA support for TCG is on the list so I think it makes sense for this to
land after those are merged.
I believe you mean this
On 08/05/2022 00:41, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 10c6d7ae43..348a898950 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -238,6 +238,7 @@ typedef union _ppc_vsr_t {
typedef ppc_vsr
On 08/05/2022 01:27, Richard Henderson wrote:
On 5/6/22 07:18, Lucas Mateus Castro(alqotel) wrote:
There's a discrepancy between this implementation and mambo/the
hardware where implementing it with float64_mul then float64r32_muladd
sometimes results in an incorrect result after an underflow,
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 17 +
target/riscv/vector_helper.c| 4
> ~eopxd 於 2022年5月11日 上午12:49 寫道：
>
> According to v-spec, tail agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of tail policies, QEMU should be able to simulate the tail
> agnostic behavior as "set tail elements' bits to al
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 44 +
target/riscv/vector_helper.c| 20 +++
2 files changed, 64 insertions(+)
diff --git a
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 23 ++
target/riscv/vector_helper.c| 40 +
2 files changed, 63 insertions(+)
diff --gi
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
di
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/r
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++
target/riscv/vector_helper.c| 11 +++
2 files changed, 22 insertions(+)
diff --git a/target/riscv/
From: eopXD
Compares write mask registers, and so always operate under a tail-
agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 18 ++
1 file changed, 18 insertions(+)
diff
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5acbe68b
From: eopXD
The tail elements in the destination mask register are updated under
a tail-agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +
target/riscv/vector_helper.c
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 29 +++
target/riscv/internals.h
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail eleme
Hi,
I have sent the fix out at
https://lists.gnu.org/archive/html/qemu-devel/2022-05/msg01980.html.
Would be grateful for your review.
Regards,
Kshitij Suri
On 06/05/22 7:07 pm, Peter Maydell wrote:
On Wed, 27 Apr 2022 at 18:33, Gerd Hoffmann wrote:
From: Kshitij Suri
Currently screendu
> On May 10, 2022, at 9:22 AM, Daniel P. Berrangé wrote:
>
> On Thu, May 05, 2022 at 05:17:01PM +0100, Peter Maydell wrote:
>> On Thu, 5 May 2022 at 16:44, Stefan Hajnoczi wrote:
>>>
>>> On Tue, May 03, 2022 at 10:16:47AM -0400, Jagannathan Raman wrote:
>>> Ubuntu 20.04LTS has CMake 3.16.3:
>
Currently png support is dependent on vnc for linking object file to
libpng. This commit makes the parameter independent of vnc as it breaks
system emulator with --disable-vnc unless --disable-png is added.
Fixes: 9a0a119a382867dc9a5c2ae9348003bf79d84af2
Signed-off-by: Kshitij Suri
---
ui/meson.
On Mon, May 09, 2022 at 12:29:59PM +0200, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> block/blkverify.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/block/blkverify.c b/block/blkverify.c
> index e4a37af3b2..020b1ae7b6 100644
> --- a/block/blkverify.c
>
On 5/9/22 23:42, Dao Lu wrote:
+static bool trans_pause(DisasContext *ctx, arg_pause *a)
+{
+REQUIRE_ZIHINTPAUSE(ctx);
+
+/*
+ * PAUSE is a no-op in QEMU,
+ * however we need to clear the reservation
+ */
+tcg_gen_movi_tl(load_res, -1);
I recommend ending the TB and retu
Let's force on the security issue:
Firstly, this answer (
https://stackoverflow.com/questions/32138524/is-there-a-windows-equivalent-of-openat
) is useless for QEMU.
It uses Windows native API NtCreateFile() and accesses files by Windows handle.
But 9PFS is using Windows POSIX interface, handle
On Mon, May 09, 2022 at 12:29:58PM +0200, Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
Sparse commit message; from the followup email, this sentence would be helpful:
| The only rule is that callers of coroutine_fn must be coroutine_fn themselves,
| or the call must be within "if (qemu_in
On Tue, May 10, 2022 at 10:52:34AM +0100, Daniel P. Berrangé wrote:
> On Mon, May 02, 2022 at 10:01:41AM -0400, Andrea Bolognani wrote:
> > Revised proposal for the annotation:
> >
> > ns:word-WORD-WoRD-123Word
>
> Ugly, but we should only need this in the fairly niche scenarios,
> so not too pai
It's true that these functions currently affect the batch size in which
coroutines are reused (i.e. moved from the global release pool to the
allocation pool of a specific thread), but this is a bug and will be
fixed in a separate patch.
In fact, the comment in the header file already just promise
Kevin Wolf (2):
coroutine: Rename qemu_coroutine_inc/dec_pool_size()
coroutine: Revert to constant batch size
include/qemu/coroutine.h | 6 +++---
hw/block/virtio-blk.c| 6 ++
util/qemu-coroutine.c| 26 --
3 files changed, 21 insertions(+), 17 deletions(-
Commit 4c41c69e changed the way the coroutine pool is sized because for
virtio-blk devices with a large queue size and heavy I/O, it was just
too small and caused coroutines to be deleted and reallocated soon
afterwards. The change made the size dynamic based on the number of
queues and the queue s
On Mon, May 09, 2022 at 12:29:57PM +0200, Paolo Bonzini wrote:
> qemu_coroutine_get_aio_context inspects a coroutine, but it does
> not have to be called from the coroutine itself (or from any
> coroutine).
>
> Signed-off-by: Paolo Bonzini
> ---
> include/qemu/coroutine.h | 2 +-
> util/qemu-cor
On 5/10/22 02:11, yangxiaojuan wrote:
Why does only register 0 affect expire time, and not all 3 registers?
Thanks, the toymatch[1]/[2] should also affect expire time. I fixed it like
this:
+static void rtc_toymatch_write(LS7ARtcState *s, struct tm *tm, uint64_t val)
+{
+ int64_t alarm_off
On Mon, May 09, 2022 at 12:29:56PM +0200, Paolo Bonzini wrote:
> nbd_co_establish_connection_cancel() cancels a coroutine but is not called
> from coroutine context itself, for example in nbd_cancel_in_flight()
> and in timer callbacks reconnect_delay_timer_cb() and open_timer_cb().
>
> Signed-off
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