On Thu, Apr 14, 2022 at 03:46:59AM -0700, Yi Liu wrote:
> Qomify the VFIOContainer object which acts as a base class for a
> container. This base class is derived into the legacy VFIO container
> and later on, into the new iommufd based container.
You certainly need the abstraction, but I'm not su
From: Klaus Jensen
Since version 5.2 commit 6eb7a071292a ("hw/block/nvme: change controller
pci id"), the emulated NVMe controller has defaulted to a non-Intel PCI
identifier.
Deprecate the compatibility parameter so we can get rid of it once and
for all.
Signed-off-by: Klaus Jensen
---
docs/
From: Alistair Francis
Imply the TPM sysbus devices. This allows users to add TPM devices to
the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock
Then launching QEMU w
From: Alistair Francis
Similar to the ARM virt machine add support for adding device tree
entries for dynamically created devices.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Message-Id: <20220427234146.1130752-5-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair F
From: Alistair Francis
The ARM virt machine currently uses sysbus-fdt to create device tree
entries for dynamically created MMIO devices.
The RISC-V virt machine can also benefit from this, so move the code to
the core directory.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
From: Weiwei Li
- add zbk* and zk* strings to isa_edata_arr
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Tested-by: Jiatai He
Reviewed-by: Alistair Francis
Message-Id: <20220426095204.24142-1-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 13 ++
From: Weiwei Li
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-15-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/risc
From: Alistair Francis
Add support for plugging in devices, this was tested with the TPM
device.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Bin Meng
Message-Id: <20220427234146.1130752-6-alistair.fran...@opensource.wdc.com>
Signed-off-by: Alistair Francis
---
From: Alistair Francis
Create a platform bus to allow dynamic devices to be connected. This is
based on the ARM implementation.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Bin Meng
Message-Id: <20220427234146.1130752-4-alistair.fran...@opensource.wdc.com>
Signe
From: Weiwei Li
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-14-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
disas/riscv.c | 173 +
From: Weiwei Li
- add SEED CSR which must be accessed with a read-write instruction:
A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI
with uimm=0 will raise an illegal instruction exception.
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-autho
From: Ralf Ramsauer
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.
Enforce the split up, by tracking the virtual base address.
Let's say we have the mapping:
0x8120 -> 0x89623000 (4K)
0x8120f000 -> 0x89624000 (4K)
Before, wal
From: Weiwei Li
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-
From: Weiwei Li
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-12-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Fr
From: Weiwei Li
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-11-liwei...@iscas.ac.cn>
Signed
From: Weiwei Li
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20220423023510.30794-6-liwei...@iscas.ac.cn>
Signed-off-by: A
From: Weiwei Li
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Message-Id: <20220423023
From: Weiwei Li
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Acked-by: Alistair Francis
Message-Id: <20220423023510.30794-5-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/helper.h
From: Weiwei Li
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-7-liwei...@iscas.ac.cn>
Signed-off-by
From: Weiwei Li
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-Id: <20220423023510.30794-9-liwei...@iscas.ac.cn>
Signed-
From: Weiwei Li
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <20220423023510.30794-4-liwei...@iscas.ac.cn>
Signed-off-by: Alistair
From: Weiwei Li
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Message-Id: <2022042302351
From: Alistair Francis
Move the binary and device tree loading code to the machine done
notifier. This allows us to prepare for editing the device tree as part
of the notifier.
This is based on similar code in the ARM virt machine.
Signed-off-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
From: Bin Meng
Commit 7c28f4da20e5 ("RISC-V: Don't add NULL bootargs to device-tree")
tried to avoid adding *NULL* bootargs to device tree, but unfortunately
the changes were entirely useless, due to MachineState::kernel_cmdline
can't be NULL at all as the default value is given as an empty strin
From: Weiwei Li
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
Message-Id: <20220423023510.30794-2-liwei...@iscas.ac.cn>
Signed-off-by: Alistair Francis
---
target/riscv/cpu.h | 13 +
target/riscv/cpu.c | 23 +++
2 files chang
From: Frank Chang
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Mess
From: Alistair Francis
The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
Merge tag 'pull-target-arm-20220428' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28
08:34:17 -0700)
are available in the Git repositor
From: Bin Meng
At present the adding '/chosen/stdout-path' property in device tree
is determined by whether a kernel command line is provided, which is
wrong. It should be added unconditionally.
Fixes: 8d8897accb1c ("hw/riscv: spike: Allow using binary firmware as bios")
Signed-off-by: Bin Meng
On Fri, Apr 29, 2022 at 4:22 AM Yang Zhong wrote:
>
> On Thu, Apr 28, 2022 at 02:56:50PM +0200, Jinpu Wang wrote:
> > On Thu, Apr 28, 2022 at 2:32 PM Yang Zhong wrote:
> > >
> > > On Thu, Apr 28, 2022 at 02:18:54PM +0200, Jinpu Wang wrote:
> > > > On Thu, Apr 28, 2022 at 2:05 PM Yang Zhong wrote
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Si
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 168 +-
target/riscv/instmap
Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.
In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 533c91e8f22c ("target/riscv: Use RISCVException enum for
CSR access")
Signed-off-by: Anup Patel
---
target/riscv/cs
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V. The first two patches are fixes whereas the second
two patches make nested virtualization performance better on for
QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v1 branch at:
https://github.
On Wed, Apr 27, 2022 at 5:09 PM Si-Wei Liu wrote:
>
>
>
> On 4/27/2022 1:38 AM, Jason Wang wrote:
> > On Wed, Apr 27, 2022 at 4:30 PM Si-Wei Liu wrote:
> >>
> >>
> >> On 4/26/2022 9:28 PM, Jason Wang wrote:
> >>> 在 2022/3/30 14:33, Si-Wei Liu 写道:
> Hi,
>
> This patch series attempt
On Fri, Apr 29, 2022 at 5:14 AM Joao Martins wrote:
>
> IOMMU advertises Access/Dirty bits if the extended capability
> DMAR register reports it (ECAP, mnemonic ECAP.SSADS albeit it used
> to be known as SLADS before). The first stage table, though, has no bit for
> advertising Access/Dirty, unles
On Fri, Apr 29, 2022 at 10:24 AM Jason Wang wrote:
>
>
> 在 2022/4/27 16:30, Si-Wei Liu 写道:
> > With MQ enabled vdpa device and non-MQ supporting guest e.g.
> > booting vdpa with mq=on over OVMF of single vqp, below assert
> > failure is seen:
> >
> > ../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_v
在 2022/4/27 16:30, Si-Wei Liu 写道:
With MQ enabled vdpa device and non-MQ supporting guest e.g.
booting vdpa with mq=on over OVMF of single vqp, below assert
failure is seen:
../hw/virtio/vhost-vdpa.c:560: vhost_vdpa_get_vq_index: Assertion `idx >= dev->vq_index
&& idx < dev->vq_index + dev->n
On Thu, Apr 28, 2022 at 02:56:50PM +0200, Jinpu Wang wrote:
> On Thu, Apr 28, 2022 at 2:32 PM Yang Zhong wrote:
> >
> > On Thu, Apr 28, 2022 at 02:18:54PM +0200, Jinpu Wang wrote:
> > > On Thu, Apr 28, 2022 at 2:05 PM Yang Zhong wrote:
> > > >
> > > > On Thu, Apr 28, 2022 at 01:59:33PM +0200, Jin
在 2022/4/27 16:30, Si-Wei Liu 写道:
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do
On 2022/04/28 20:22, Christian Schoenebeck wrote:
On Mittwoch, 27. April 2022 22:36:25 CEST Greg Kurz wrote:
On Wed, 27 Apr 2022 20:54:17 +0200
Christian Schoenebeck wrote:
mknod() on macOS does not support creating sockets, so divert to
call sequence socket(), bind() and fchmodat() respectiv
> From: Daniel P. Berrangé
> Sent: Friday, April 29, 2022 12:20 AM
>
> On Thu, Apr 28, 2022 at 08:24:48AM -0600, Alex Williamson wrote:
> > On Thu, 28 Apr 2022 03:21:45 +
> > "Tian, Kevin" wrote:
> >
> > > > From: Alex Williamson
> > > > Sent: Wednesday, April 27, 2022 12:22 AM
> > > > > >
On 4/27/22 16:35, Stefan Hajnoczi wrote:
Commit f34e8d8b8d48d73f36a67b6d5e492ef9784b5012 ("virtio-scsi: prepare
virtio_scsi_handle_cmd for dataplane") prepared the virtio-scsi cmd
virtqueue handler function to by used in both the dataplane and
non-datpalane code paths.
It failed to convert the c
On 4/27/22 16:35, Stefan Hajnoczi wrote:
virtio_scsi_handle_cmd_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio-sc
On 4/27/22 16:35, Stefan Hajnoczi wrote:
virtio_scsi_handle_ctrl_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio-s
With "detach-all=on" for display, QEMU starts with all VC windows
detached automatically.
If used with "full-screen=on", it places individual windows (from
top window) starting from monitor 0 or monitor n in case monitor=n.
In case # mon < # VCs, only same number of VCs as # mon will be sent to
t
On 4/27/22 16:35, Stefan Hajnoczi wrote:
There is no longer a need to expose the request and related APIs in
virtio-scsi.h since there are no callers outside virtio-scsi.c.
Note the block comment in VirtIOSCSIReq has been adjusted to meet the
coding style.
Signed-off-by: Stefan Hajnoczi
---
Specify location and size of detached window based on top level
window's location and size info when detachment happens.
Cc: Philippe Mathieu-Daudé
Cc: Paolo Bonzini
Cc: Gerd Hoffmann
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
ui/gtk.c | 13 +
1 file changed, 13 insertion
On 4/27/22 16:35, Stefan Hajnoczi wrote:
virtio_scsi_handle_event_vq() is only called from hw/scsi/virtio-scsi.c
now and its return value is no longer used. Remove the function
prototype from virtio-scsi.h and drop the return value.
Reviewed-by: Paolo Bonzini
On 4/27/22 16:35, Stefan Hajnoczi wrote:
This is typical for rx virtqueues where the device uses buffers when
some event occurs (e.g. a packet is received, an error condition
happens, etc).
Polling non-empty virtqueues wastes CPU cycles. We are not waiting for
new buffers to become available, we
This patch series introduces two new gtk optional parameters, monitor
and detach-all. "monitor" is for specifying a display where QEMU window
will be launched from. "detach-all" is making all VCs detached upon
QEMU's launch. The use-case we originally wanted to deal with is when
multiple displays (
Introducing a new integer parameter to specify the monitor where the
Qemu window is placed upon launching.
Monitor can be any number between 0 and (total number of monitors - 1).
It can be used together with full-screen=on, which will make the QEMU
window full-screened on the targeted monitor.
v
On 4/28/22 15:46, Stefan Hajnoczi wrote:
if have_block
util_ss.add(files('aiocb.c', 'async.c', 'aio-wait.c'))
+ util_ss.add(files('../block/graph-lock.c'))
Why is it in block/ if it needs to be built into libqemuutil?
Maybe register_aiocontext, unregister_aiocontext and
aio_context_li
On 4/28/22 13:21, Stefan Hajnoczi wrote:
It's unclear whether this patch fixes a bug or introduces a new API that
will be used in later patches.
The commit message is a bit misleading: existing functions are not
changed to release the lock when restarting all coroutines.
I think what this commi
On 4/28/22 20:21, Konstantin Kostiuk wrote:
Konstantin Kostiuk (2):
configure: Add cross prefix for widl tool
qga-vss: always build qga-vss.tlb when qga-vss.dll is built
configure | 3 +++
qga/vss-win32/meson.build | 4 ++--
2 files changed, 5 insertions(+), 2 deletions
On 4/21/22 03:42, yue wrote:
Hi, i think it is curios for a process to have so many threads.
my environment: 5.4.160-1.el7.x86_64, qemu-6.1.0
Use "-name debug-threads=yes". Most of them are going to be I/O workers.
Paolo
Am 28/04/2022 um 12:45 schrieb Stefan Hajnoczi:
> On Wed, Apr 27, 2022 at 08:55:35AM +0200, Emanuele Giuseppe Esposito wrote:
>>
>>
>> Am 26/04/2022 um 10:51 schrieb Emanuele Giuseppe Esposito:
>>> Luckly, most of the cases where we recursively go through a graph are
>>> the BlockDriverState cal
On Thu, 28 Apr 2022, Víctor Colombo wrote:
On 28/04/2022 03:46, Cédric Le Goater wrote:
On 4/27/22 19:00, Víctor Colombo wrote:
Hello everyone! Thanks Zoltan and Richard for your kind reviews!
On 26/04/2022 18:29, Richard Henderson wrote:
On 4/22/22 11:54, Víctor Colombo wrote:
Suggested-by:
ioctl(iommufd, IOMMU_HWPT_GET_DIRTY_IOVA, arg) is the UAPI
that fetches the bitmap that tells what was dirty in an IOVA
range.
A single bitmap is allocated and used across all the hw_pagetables
sharing an IOAS which is then used in log_sync() to set Qemu
global bitmaps.
There's no point of even a
Expand dirtyrate measurer that is accessible via HMP calc_dirty_rate
or QMP 'calc-dirty-rate' to receive a @scope argument. The scope
then restricts the dirty tracking to be done at devices only,
while neither enabling or using the KVM (CPU) dirty tracker.
The default stays as is i.e. dirty-ring /
On a successful translation, cache the PASID Table entry
flags set at the context at the time i.e. the first 12bits.
These bits contain read, write, dirty and access for example.
This is a preparatory for SSADS which requires updating A/D
bits on a translation based on the fact that SSADS was enab
ioctl(iommufd, IOMMU_HWPT_SET_DIRTY, arg) is the UAPI
that enables or disables dirty page tracking. We set it
on the whole list of iommu domains we are tracking, and
set ::dirty_pages_supported accordingly, used when we
attempt at reading out the dirty bits from the hw pagetables.
Signed-off-by: J
IOMMU advertises Access/Dirty bits if the extended feature
register reports it. Relevant AMD IOMMU SDM ref[0]
"1.3.8 Enhanced Support for Access and Dirty Bits"
To enable it we set the DTE flag in bits 7 and 8 to enable
access, or access+dirty. With that, the IOMMU starts
marking the D and A flags
The ioctl(iommufd, IOAS_UNMAP_DIRTY) performs an unmap
of an IOVA range and returns whether or not it was dirty.
The kernel atomically clears the IOPTE while telling if
the old IOPTE was dirty or not. This in theory is needed
for the vIOMMU case to handle a potentially erronous guest
PCI device pe
IOMMU advertises Access/Dirty bits if the extended capability
DMAR register reports it (ECAP, mnemonic ECAP.SSADS albeit it used
to be known as SLADS before). The first stage table, though, has no bit for
advertising Access/Dirty, unless referenced via a scalable-mode PASID Entry.
Relevant Intel IO
This series expands IOMMUFD series from Yi and Eric into
supporting IOMMU Dirty Tracking. It adds both the emulated x86
IOMMUs, as well as IOMMUFD support that exercises said
emulation (or H/W).
It is organized into:
* Patches 1 - 4: x86 IOMMU emulation that performs dirty tracking,
useful for a
Print the number of dirty pages after calling
cpu_physical_memory_set_lebitmap() on the vfio_get_dirty_bitmap
tracepoint. Additionally, print the number of dirty pages to
capture the unmap case under a new tracepoint called
vfio_set_dirty_pages.
Signed-off-by: Joao Martins
---
hw/vfio/container.
Generated from `scripts/update-linux-headers`
from github.com:jpemartins/linux:iommufd
Signed-off-by: Joao Martins
---
linux-headers/linux/iommufd.h | 78 +++
1 file changed, 78 insertions(+)
diff --git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommuf
On a successful translation, cache the PTE and DTE
flags set at the time of the translation i.e. the first 12bits
as well as the PTE storage. These bits contain read, write,
dirty and access for example. In theory the DTE lookup takes
precendence in the translation path, but in the interest of
perf
On Apr 21 13:51, Dmitry Tikhov wrote:
> Current implementation have problem in the read part of copy command.
> Because there is no metadata mangling before nvme_dif_check invocation,
> reftag error could be thrown for blocks of namespace that have not been
> previously written to.
>
> Signed-off-
On Thu, 28 Apr 2022 15:49:45 +0200
Eric Auger wrote:
> The CRB command buffer currently is a RAM MemoryRegion and given
> its base address alignment, it causes an error report on
> vfio_listener_region_add(). This region could have been a RAM device
> region, easing the detection of such safe sit
On Mar 18 20:18, Lukasz Maniak wrote:
> Resubmitting v6 as v7 since Patchew got lost with my sophisticated CC of
> all maintainers just for the cover letter.
>
> Changes since v5:
> - Fixed PCI hotplug issue related to deleting VF twice
> - Corrected error messages for SR-IOV parameters
> - Rebase
On Thu, Apr 28, 2022 at 10:18 PM Konstantin Kostiuk
wrote:
> Signed-off-by: Konstantin Kostiuk
>
Reviewed-by: Marc-André Lureau
> ---
> qga/vss-win32/meson.build | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.bui
On Thu, Apr 28, 2022 at 10:17 PM Konstantin Kostiuk
wrote:
> The mingw-w64-tool package in Fedora provides widl tool with a
> cross prefix, so adds it automatically for cross builds.
>
> WIDL env can be used to redefine the path to tool.
> The same behavior as with windres.
>
> Signed-off-by: Kon
* yue (kvml...@163.com) wrote:
> Hi, i think it is curios for a process to have so many threads.
>
> my environment: 5.4.160-1.el7.x86_64, qemu-6.1.0
If you pass:
-name whatever,debug-threads=on
then the qemu will set the kernel thread name to names
like 'CPU 0/Kvm' or 'migration' or whatever
Konstantin Kostiuk (2):
configure: Add cross prefix for widl tool
qga-vss: always build qga-vss.tlb when qga-vss.dll is built
configure | 3 +++
qga/vss-win32/meson.build | 4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
--
2.25.1
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build
index 71c50d0866..26c5dd6e0e 100644
--- a/qga/vss-win32/meson.build
+++ b/qga/vss-win32/meson.build
@@ -23,
Richard Henderson wrote:
>Create and record the two signal trampolines.
>Use them when the guest does not use SA_RESTORER.
This patch caused a regression when running the wasmtime CI under qemu:
https://github.com/bytecodealliance/wasmtime/pull/4076
The problem is that this part:
>diff --git a
The mingw-w64-tool package in Fedora provides widl tool with a
cross prefix, so adds it automatically for cross builds.
WIDL env can be used to redefine the path to tool.
The same behavior as with windres.
Signed-off-by: Konstantin Kostiuk
---
configure | 3 +++
1 file changed, 3 insertions(+)
On Thu, Apr 28, 2022 at 11:08 AM Dr. David Alan Gilbert
wrote:
>
> * Leonardo Bras (leob...@redhat.com) wrote:
> > This patch series intends to enable MSG_ZEROCOPY in QIOChannel, and make
> > use of it for multifd migration performance improvement, by reducing cpu
> > usage.
> >
> > Patch #1 creat
u into
staging (2022-04-27 10:49:28 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220428
for you to fetch changes up to f8e7163d9e6740b5cef02bf73a17a59d0bef8bdb:
hw/arm/smmuv3: Advertise support for SMMUv3.2-BB
On 4/21/22 21:30, Mark Cave-Ayland wrote:
> This patchset started off when I noticed that dino.c was accessing parent_obj
> directly rather than using a QOM cast. After fixing that I noticed quite a few
> other improvements that could be done to bring hppa up to our recommended
> coding standards.
Leo:
Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY
one I guess is the simpler one; I think Stefanha managed to find the
liburing fix for the __kernel_timespec case, but that looks like a bit
more fun!
Dave
Job #2390848140 ( https://gitlab.com/dagrh/qemu/-/jobs/2390848140
On 4/27/22 23:53, Paolo Bonzini wrote:
The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a:
Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into
staging (2022-04-27 10:49:28 -0700)
are available in the Git repository at:
https://gitlab.com/b
On Thu, Apr 28, 2022 at 08:24:48AM -0600, Alex Williamson wrote:
> On Thu, 28 Apr 2022 03:21:45 +
> "Tian, Kevin" wrote:
>
> > > From: Alex Williamson
> > > Sent: Wednesday, April 27, 2022 12:22 AM
> > > > >
> > > > > My expectation would be that libvirt uses:
> > > > >
> > > > > -object
On 4/28/22 05:38, Peter Maydell wrote:
On Tue, 26 Apr 2022 at 17:33, Richard Henderson
wrote:
Split the tcg_constant patches out of my larger v3 cleanups
patch set, and then split the 5 patches into tiny bites.
Since there was only one issue with this patchset (in patch 17),
I'm going to fix
On 4/28/22 05:56, Peter Maydell wrote:
On Wed, 27 Apr 2022 at 05:23, Richard Henderson
wrote:
This controls whether the PACI{A,B}SP instructions trap with BTYPE=3
(indirect branch from register other than x16/x17). The linux kernel
sets this in bti_enable().
Resolves: https://gitlab.com/qemu
On Fri, 25 Mar 2022 at 08:04, Juan Quintela wrote:
>
> Laurent Vivier wrote:
> > Perhaps Juan or Thomas can help too (added to cc)
> >
> > Is this a regression?
> > It looks like a bug in QEMU as it doesn't move from cancelling to cancelled.
I had a repeat of this hang (same machine), so here's
From: Leonardo Bras
A lot of places check parameters.tls_creds in order to evaluate if TLS is
in use, and sometimes call migrate_get_current() just for that test.
Add new helper function migrate_use_tls() in order to simplify testing
for TLS usage.
Signed-off-by: Leonardo Bras
Reviewed-by: Jua
From: Leonardo Bras
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_socket_flush() was imple
From: Daniel P. Berrangé
Most of the multifd migration test logic is common with the rest of the
precopy tests, so it can use the helper without difficulty. The only
exception of the multifd cancellation test which tries to run multiple
migrations in a row.
Reviewed-by: Peter Xu
Signed-off-by:
From: Daniel P. Berrangé
We need to encode just the address bytes, not the whole struct sockaddr
data. Add a test case to validate that we're matching on SAN IP
addresses correctly.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-2-berra...@redhat.com>
Reviewed-by: Dr. Davi
From: Daniel P. Berrangé
Most of the XBZRLE migration test logic is common with the rest of the
precopy tests, so it can use the helper with just one small tweak.
Reviewed-by: Peter Xu
Signed-off-by: Daniel P. Berrangé
Message-Id: <20220426160048.812266-6-berra...@redhat.com>
Signed-off-by: Dr
From: "Dr. David Alan Gilbert"
The following changes since commit cf6f26d6f9b2015ee12b4604b79359e76784163a:
Merge tag 'kraxel-20220427-pull-request' of git://git.kraxel.org/qemu into
staging (2022-04-27 10:49:28 -0700)
are available in the Git repository at:
https://gitlab.com/dagrh/qemu.
On Tue, Apr 26, 2022 at 04:51:13AM -0400, Emanuele Giuseppe Esposito wrote:
> Similar to the implementation in lockable.h, implement macros to
> automatically take and release the rdlock.
> Create the empty GraphLockable struct only to use it as a type for
> G_DEFINE_AUTOPTR_CLEANUP_FUNC.
>
> Sign
From: Frank Chang
Add Xilinx AXI CDMA model, which follows
AXI Central Direct Memory Access v4.1 spec:
https://docs.xilinx.com/v/u/en-US/pg034-axi-cdma
Supports both Simple DMA and Scatter Gather modes.
Signed-off-by: Frank Chang
Reviewed-by: Jim Shu
---
hw/dma/meson.build | 2
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
Message-id: 20220426163043.100432-48-richard.hender...@linaro.org
Signed-off-by: Peter Maydell
---
target/arm/translate-sve.c | 54 ++
1 file changed, 14 insertions(+), 40 d
From: Damien Hedde
As of now, cryptographic instructions ISAR fields are never cleared so
we can end up with a cpu with cryptographic instructions but no
floating-point/neon instructions which is not a possible configuration
according to Arm specifications.
In QEMU, we have 3 kinds of cpus regar
On Tue, Apr 26, 2022 at 04:51:12AM -0400, Emanuele Giuseppe Esposito wrote:
> diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h
> index f171ba0527..2211d41286 100644
> --- a/include/block/graph-lock.h
> +++ b/include/block/graph-lock.h
> @@ -52,5 +52,20 @@ void coroutine_fn bdrv_
On 4/28/22 07:56, Víctor Colombo wrote:
A solution I could think that might be easy is: rename PPC_BIT to
PPC_BIT_ULL (behaves like BIT_ULL but 'inverted'), and create a new
PPC_BIT macro that just inverts the bit value
#define PPC_BIT_ULL(bit) (0x8000ULL >> (bit))
#define PPC_BIT(bi
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