On 05/04/2022 08:36, Eugenio Pérez wrote:
These functions were not traced properly.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 2 ++
hw/virtio/trace-events | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 8adf7c0b92.
These functions were not traced properly.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 2 ++
hw/virtio/trace-events | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 8adf7c0b92..9e5fe15d03 100644
--- a/hw/virtio/vhost-vdpa.c
Changing the affected package from "linux (Ubuntu)" (kernel) to "qemu
(Ubuntu)" as affected package, since the attached patch set is for qemu.
** Package changed: linux (Ubuntu) => qemu (Ubuntu)
** Also affects: qemu
Importance: Undecided
Status: New
** No longer affects: qemu
** Also
On 01/04/22 4:50 pm, Markus Armbruster wrote:
Dave, please have a look at the HMP compatibility issue in
hmp-command.hx below.
Kshitij Suri writes:
Currently screendump only supports PPM format, which is un-compressed and not
standard.
If "standard" means "have to pay a standards organizat
Daniel P. Berrangé writes:
> On Wed, Mar 16, 2022 at 10:54:55AM +0100, Damien Hedde wrote:
>> It takes an input file containing raw qmp commands (concatenated json
>> dicts) and send all commands one by one to a qmp server. When one
>> command fails, it exits.
>>
>> As a convenience, it can also
ping
https://lore.kernel.org/qemu-devel/39400817-3dc9-516d-9096-bc1f68862...@zapateado.de/
https://patchew.org/QEMU/39400817-3dc9-516d-9096-bc1f68862...@zapateado.de/
Am 16.03.22 um 14:54 schrieb Helge Konetzka:
This fixes:
qga/vss-win32/install.cpp:49:24: error: cannot initialize a variable o
From: Pedro Tôrres
When running on a Mac, QEMU is able to get the host OSK and use it as
the default value for the AppleSMC device. The OSK query operation
doesn't require administrator privileges and can be executed by any user
on the system. This patch is based on Phil Dennis-Jordan's descript
Hi Marc-Andre,
>
> Hi
>
> On Mon, Mar 7, 2022 at 10:00 PM Kasireddy, Vivek
> wrote:
> >
> > Hi Marc-Andre,
> >
> > >
> > > Hi Vivek
> > >
> > > On Mon, Mar 7, 2022 at 8:39 AM Vivek Kasireddy
> > > wrote:
> > > >
> > > > Since not all listeners (i.e VirtualConsoles) of GL events have
> > > > a
On Mon, Apr 4, 2022, at 10:06 AM, Sean Christopherson wrote:
> On Mon, Apr 04, 2022, Quentin Perret wrote:
>> On Friday 01 Apr 2022 at 12:56:50 (-0700), Andy Lutomirski wrote:
>> FWIW, there are a couple of reasons why I'd like to have in-place
>> conversions:
>>
>> - one goal of pKVM is to mi
> On Apr 4, 2022, at 8:14 AM, Jonathan Cameron via
> wrote:
>
> From: Ben Widawsky
>
> A device's volatile and persistent memory are known Host Defined Memory
> (HDM) regions. The mechanism by which the device is programmed to claim
> the addresses associated with those regions is through d
On Wed, Mar 16, 2022 at 5:55 AM Damien Hedde wrote:
>
> It takes an input file containing raw qmp commands (concatenated json
> dicts) and send all commands one by one to a qmp server. When one
> command fails, it exits.
>
> As a convenience, it can also wrap the qemu process to avoid having
> to
ilable in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-ppc-20220404
>
> for you to fetch changes up to 0798da8df9fd917515c957ae918d6d979cf5f3fb:
>
> linux-user/ppc: Narrow type of cc
On Mon, Apr 4, 2022 at 2:54 PM John Snow wrote:
>
> On Fri, Apr 1, 2022 at 1:05 PM Kashyap Chamarthy wrote:
> >
> > On Wed, Mar 30, 2022 at 02:24:13PM -0400, John Snow wrote:
> > > Split python/ from qemu.git, using these commands:
> > >
> > > > git subtree split -P python/ -b python-split-v3
> >
On Fri, Apr 1, 2022 at 1:05 PM Kashyap Chamarthy wrote:
>
> On Wed, Mar 30, 2022 at 02:24:13PM -0400, John Snow wrote:
> > Split python/ from qemu.git, using these commands:
> >
> > > git subtree split -P python/ -b python-split-v3
> > > mkdir ~/src/tmp
> > > cd ~/src/tmp
> > > git clone --no-loca
Let's use the reserved pool of simulated PCI groups to allow intercept
devices to have separate groups from interpreted devices as some group
values may be different. If we run out of simulated PCI groups, subsequent
intercept devices just get the default group.
Furthermore, if we encounter any PCI
Use the associated kvm ioctl operation to enable adapter event notification
and forwarding for devices when requested. This feature will be set up
with or without firmware assist based upon the 'forwarding_assist' setting.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-bus.c | 20 +
Lack of MSI-X support is not an issue for interpreted passthrough
devices, so let's let these in. This will allow, for example, ISM
devices to be passed through -- but only when interpretation is
available and being used.
Reviewed-by: Thomas Huth
Reviewed-by: Pierre Morel
Signed-off-by: Matthew
The maximum supported store block length might be different depending
on whether the instruction is interpretively executed (firmware-reported
maximum) or handled via userspace intercept (host kernel API maximum).
Choose the best available value during group creation.
Signed-off-by: Matthew Rosato
The zpci-interp feature is used to specify whether zPCI interpretation is
to be used for this guest.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-virtio-ccw.c | 1 +
target/s390x/cpu_features_def.h.inc | 1 +
target/s390x/gen-features.c | 2 ++
target/s390x/kvm/kvm.c
The v1 uapi is deprecated and will be replaced by v2 at some point;
this patch just tolerates the renaming of uapi fields to reflect
v1 / deprecated status.
Signed-off-by: Matthew Rosato
---
hw/vfio/common.c| 2 +-
hw/vfio/migration.c | 19 +++
2 files changed, 12 insertions
In order to interface with the underlying host zPCI device, we need
to know it's function handle. Add a routine to grab this from the
vfio CLP capabilities chain.
Signed-off-by: Matthew Rosato
---
hw/s390x/s390-pci-vfio.c | 83 ++--
include/hw/s390x/s390-pci-
This is a placeholder that pulls in 5.18-rc1 + unmerged kernel changes
required by this item. A proper header sync can be done once the
associated kernel code merges.
Signed-off-by: Matthew Rosato
---
.../linux/input-event-codes.h | 4 +-
.../standard-headers/linux/virtio_conf
If the appropriate CPU facilty is available as well as the necessary
ZPCI_OP ioctl, then the underlying KVM host will enable load/store
intepretation for any guest device without a SHM bit in the guest
function handle. For a device that will be using interpretation
support, ensure the guest functi
For QEMU, the majority of the work in enabling instruction interpretation
is handled via SHM bit settings (to indicate to firmware whether or not
interpretive execution facilities are to be used) + a new KVM ioctl is
used to setup firmware-interpreted forwarding of Adapter Event
Notification
* Alex Bennée (alex.ben...@linaro.org) wrote:
>
> (expanding the CC list for help, anyone have a better idea about how
> vhost-user qtests should work/see obvious issues with this patch?)
How exactly does it fail?
DAve
> Alex Bennée writes:
>
> > We don't have a virtio-gpio implementation in
* Laurent Vivier (lviv...@redhat.com) wrote:
> If the migration is over before we cancel it, we are
> waiting in a loop a state that never comes because the state
> is already "completed".
>
> To avoid an infinite loop, skip the test if the migration
> is "completed" before we were able to cancel
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.
Enforce the split up, by tracking the virtual base address.
Let's say we have the mapping:
0x8120 -> 0x89623000 (4K)
0x8120f000 -> 0x89624000 (4K)
Before, walk_pte would have shown
On 01/04/2022 14:22, Ralf Ramsauer wrote:
Two non-subsequent PTEs can be mapped to subsequent paddrs. In this
case, walk_pte will erroneously merge them.
Enforce the split up, by tracking the virtual base address.
Let's say we have the mapping:
0x8120 -> 0x89623000 (4K)
0x8120f000 -> 0x8
* Ilya Leoshkevich (i...@linux.ibm.com) wrote:
> On Mon, 2022-04-04 at 12:20 +0100, Dr. David Alan Gilbert wrote:
> > * Ilya Leoshkevich (i...@linux.ibm.com) wrote:
> > > zlib_send_prepare() compresses pages of a running VM. zlib does not
> > > make any thread-safety guarantees with respect to chan
On 4/4/22 10:53, Peter Maydell wrote:
It's not possible to provide the guest with the Security extensions
(TrustZone) when using KVM or HVF, because the hardware
virtualization extensions don't permit running EL3 guest code.
However, we weren't checking for this combination, with the result
that
On Mon, Apr 04, 2022, Quentin Perret wrote:
> On Friday 01 Apr 2022 at 12:56:50 (-0700), Andy Lutomirski wrote:
> FWIW, there are a couple of reasons why I'd like to have in-place
> conversions:
>
> - one goal of pKVM is to migrate some things away from the Arm
>Trustzone environment (e.g. DR
On 3/31/22 14:55, Igor Mammedov wrote:
On Tue, 29 Mar 2022 00:15:38 +0300
Maxim Davydov wrote:
The command "query-init-properties" is needed to get values of properties
after initialization (not only default value). It makes sense, for example,
when working with x86_64-cpu.
All machine types
Switch the creation of the external GIC to the new-style "embedded in
state struct" approach, so we can easily refer to the object
elsewhere during realize.
Signed-off-by: Peter Maydell
---
include/hw/arm/exynos4210.h | 2 ++
include/hw/intc/exynos4210_gic.h | 43 ++
Switch the creation of the combiner devices to the new-style
"embedded in state struct" approach, so we can easily refer
to the object elsewhere during realize.
Signed-off-by: Peter Maydell
---
include/hw/arm/exynos4210.h | 3 ++
include/hw/intc/exynos4210_combiner.h | 57
Fix a missing set of spaces around '-' in the definition of
combiner_grp_to_gic_id[]. We're about to move this code, so
fix the style issue first to keep checkpatch happy with the
code-motion patch.
Signed-off-by: Peter Maydell
---
hw/intc/exynos4210_gic.c | 2 +-
1 file changed, 1 insertion(+),
The only time we use the int_combiner_irq[] and ext_combiner_irq[]
arrays in the Exynos4210Irq struct is during realize of the SoC -- we
initialize them with the input IRQs of the combiner devices, and then
connect those to outputs of other devices in
exynos4210_init_board_irqs(). Now that the com
The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0
and EXT_GIC_ID_MCT_G1 multiple times. This means that we will
connect multiple IRQs up to the same external GIC input, which
is not permitted. We do the same thing in the code in
exynos4210_init_board_irqs() because the conditionals
The only time we use the ext_gic_irq[] array in the Exynos4210Irq
struct is during realize of the SoC -- we initialize it with the
input IRQs of the external GIC device, and then connect those to
outputs of other devices further on in realize (including in the
exynos4210_init_board_irqs() function)
Add a single complex case for aarch64 virt machine.
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 48 +
tests/qtest/meson.build | 1 +
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl
The function exynos4210_combiner_get_gpioin() currently lives in
exynos4210_combiner.c, but it isn't really part of the combiner
device itself -- it is a function that implements the wiring up of
some interrupt sources to multiple combiner inputs. Move it to live
with the other SoC-level code in e
It's not possible to provide the guest with the Security extensions
(TrustZone) when using KVM or HVF, because the hardware
virtualization extensions don't permit running EL3 guest code.
However, we weren't checking for this combination, with the result
that QEMU would assert if you tried it:
$ qe
Currently for the interrupts MCT_G0 and MCT_G1 which are
the only ones in the input range of the external combiner
and which are also wired to the external GIC, we connect
them only to the internal combiner and the external GIC.
This seems likely to be a bug, as all other interrupts
which are in th
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron
---
tests/qtest/bios-tab
In exynos4210_init_board_irqs(), the loop that handles IRQ lines that
are in a range that applies to the internal combiner only creates a
splitter for those interrupts which go to both the internal combiner
and to the external GIC, but it does nothing at all for the
interrupts which don't go to the
The exynos4210 code currently has two very similar arrays of IRQs:
* board_irqs is a field of the Exynos4210Irq struct which is filled
in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
for each IRQ the board/SoC can assert
* irq_table is a set of qemu_irqs pointed to from t
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| 0
tests/data/acpi/q35/DSDT.cxl| 0
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
3 files
At this point, the function exynos4210_init_board_irqs() splits input
IRQ lines to connect them to the input combiner, output combiner and
external GIC. The function exynos4210_combiner_get_gpioin() splits
some of the combiner input lines further to connect them to multiple
different inputs on the
The only time we use the int_gic_irq[] array in the Exynos4210Irq
struct is in the exynos4210_realize() function: we initialize it with
the GPIO inputs of the a9mpcore device, and then a bit later on we
connect those to the outputs of the internal combiner. Now that the
a9mpcore object is easily a
Delete a couple of #defines which are never used.
Signed-off-by: Peter Maydell
---
include/hw/arm/exynos4210.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index b564e3582bb..f0769a4045b 100644
--- a/include/hw/arm/exynos4210.h
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device
instead of qemu_irq_split().
Signed-off-by: Peter Maydell
---
include/hw/arm/exynos4210.h | 9
hw/arm/exynos4210.c | 41 +
2 files changed, 42 insertions(+), 8 deletions(-)
diff
The exynos4210 SoC mostly creates its child devices as if it were
board code. This includes the a9mpcore object. Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize()
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
Reviewed-by: Alex Bennée
---
hw/arm/Kconfig | 1 +
The primary aim of this patchset is to make the exynos4210 code use
the TYPE_SPLIT_IRQ device instead of the old qemu_split_irq() function
(which we are trying to get rid of). However, the current code is
quite complicated and so we have to do a fair amount of refactoring
in order to be able to use
From: Jonathan Cameron
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable b
The function exynos4210_init_board_irqs() currently lives in
exynos4210_gic.c, but it isn't really part of the exynos4210.gic
device -- it is a function that implements (some of) the wiring up of
interrupts between the SoC's GIC and combiner components. This means
it fits better in exynos4210.c, w
The Exynos4210 SoC device currently uses a custom device
"exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ
line. We have a standard TYPE_OR_IRQ device for this now, so use
that instead.
(This is a migration compatibility break, but that is OK for this
machine type.)
Signed-off
On Mon, 4 Apr 2022 at 15:51, Sakshi Kaushik wrote:
> I am not able to find vhost-user-scsi inside build/contrib/vhost-user-scsi
> despite running the 'make' command.
It is probably not being built because the dependencies are not
installed on your machine. Here are the contents of the
contrib/vh
From: Ben Widawsky
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
iasl -d decodes the result of this patch as:
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SU
Emulation of a simple CXL Switch downstream port.
The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-host.c | 43 +-
hw/pci-bridge/cxl_downstream.c | 244 +
hw/pci-bridge/meson.build | 2 +-
3 fil
Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
delete the device entirely.
Signed-off-by: Peter Maydell
---
hw/intc/exynos4210_gic.c | 107 ---
1 file changed, 107 deletions(-)
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gi
Switches were already introduced, but now we support them update
the documentation to provide an example in diagram and
qemu command line parameter forms.
Signed-off-by: Jonathan Cameron
---
docs/system/devices/cxl.rst | 88 -
1 file changed, 86 insertions(+),
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mai
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which is relevant to either
user
From: Ben Widawsky
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
---
tests/qtest/cxl-test.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/test
Code based on i386/pc enablement.
The memory layout places space for 16 host bridge register regions after
the GIC_REDIST2 in the extended memmap.
The CFMWs are placed above the extended memmap.
Only create the CEDT table if cxl=on set for the machine.
Signed-off-by: Jonathan Cameron
Signed-off-
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron
---
tests/data/acpi/q35/CEDT.cxl| Bin 0 -> 184 bytes
tests/data/acpi/q35/DSDT.cxl| Bin 0 -> 9615 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 2 --
3 fi
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device specific address space to access the
hostmem->mr to
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 3 +++
hw/mem/cxl_type3.c | 9 +
include/hw/cxl/cxl_device.h | 11 ++
On 3/30/22 18:17, Vladimir Sementsov-Ogievskiy wrote:
29.03.2022 00:15, Maxim Davydov wrote:
The command "query-init-properties" is needed to get values of
properties
after initialization (not only default value). It makes sense, for
example,
when working with x86_64-cpu.
All machine types (
From: Jonathan Cameron
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 7 +++
include/hw/cxl/cxl_component.h | 2 ++
2
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a no
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
---
hw/i386/pc.c | 31 ++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/h
An initial simple upstream port emulation to allow the creation
of CXL switches. The Device ID has been allocated for this use.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_upstream.c | 211 +++
hw/pci-bridge/meson.build| 2 +-
include/hw/cxl/cxl.h
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci/pci
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
---
tests/qtest/cxl-test.c | 23 +++
tests/qtest/meson.build | 4
2 files changed, 27 insertions(+)
di
From: Ben Widawsky
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-component-utils.c | 31 +++
1 file changed, 31 insertions(+)
diff
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicat
From: Ben Widawsky
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield
Signed-of
From: Jonathan Cameron
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/core/machine.c
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
tests/qtest/cxl-test.c | 126 +
1 file changed, 126 insertions(+)
dif
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
From: Ben Widawsky
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to
From: Ben Widawsky
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware
The main problem that if we call object_new_with_class() and then
object_unref(), it fails. First of all, this is due to the fact that
finalize expects that net/colo-compare.c:colo_compare_complete() has
been called before.
On 3/30/22 17:54, Vladimir Sementsov-Ogievskiy wrote:
29.03.2022 00:1
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
---
hw/cxl/cxl-mailbox-utils.c | 69 +
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
From: Ben Widawsky
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly
From: Ben Widawsky
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/pci-bridge/pci_expander_bridge.c | 11 +++
1 f
From: Ben Widawsky
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/cxl/cxl-mailbox-utils.c | 27 +++
From: Ben Widawsky
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the
From: Ben Widawsky
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
command
From: Ben Widawsky
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically c
From: Ben Widawsky
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
hw/cxl/cxl-mail
From: Ben Widawsky
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulate
From: Ben Widawsky
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignme
From: Jonathan Cameron
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
From: Ben Widawsky
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit comm
From: Ben Widawsky
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of
On Fri, Apr 01, 2022 at 02:30:34PM +0100, Jonathan Cameron wrote:
> On Thu, 31 Mar 2022 22:13:20 +
> Adam Manzanares wrote:
>
> > On Wed, Mar 30, 2022 at 06:48:48PM +0100, Jonathan Cameron wrote:
> > > On Tue, 29 Mar 2022 18:13:59 +
> > > Adam Manzanares wrote:
> > >
> > > > On Fri, M
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