On Fri, Oct 15, 2021 at 6:43 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
>
> --
> ---
> target/riscv/cpu.h | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
> target/riscv/vector_helper.c| 2
On Fri, Oct 15, 2021 at 6:44 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
Hey Frank,
You will need to rebase this on the latest master branch.
Alistair
> ---
> target/riscv/csr.c | 9 ++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv
22.10.2021 12:52, Fabrice Fontaine пишет:
Include linux/falloc.h if CONFIG_FALLOCATE_ZERO_RANGE is defined to fix
https://gitlab.com/qemu-project/qemu/-/commit/50482fda98bd62e072c30b7ea73c985c4e9d9bbb
and avoid the following build failure on musl:
../block/export/fuse.c: In function 'fuse_falloc
On Fri, Oct 15, 2021 at 6:43 PM wrote:
>
> From: Frank Chang
>
> Add the following instructions:
>
> * vfcvt.rtz.xu.f.v
> * vfcvt.rtz.x.f.v
>
> Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
> modes.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistai
On Fri, Oct 15, 2021 at 6:38 PM wrote:
>
> From: Frank Chang
>
> Add the following instructions:
>
> * vfslide1up.vf
> * vfslide1down.vf
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 7 ++
> target/riscv/insn32.deco
On Fri, Oct 15, 2021 at 6:26 PM wrote:
>
> From: Frank Chang
>
> * Only do carry-in or borrow-in if is masked (vm=0).
> * Remove clear function from helper functions as the tail elements
> are unchanged in RVV 1.0.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
Alistair
> ---
On Sat, Oct 23, 2021 at 4:34 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
> Reviewed-by: Alistair Francis
> ---
> target/riscv/cpu.c | 2 +
> target/riscv/cpu.h | 11 ++
> target/riscv/csr.c | 285 +
> 3 files changed, 298 insertions(+)
Option -compat lets you configure what to do when deprecated
interfaces get used. This series extends this to unstable interfaces.
Works the same way. Intended for testing users of the management
interfaces. It is experimental.
To make it possible, I replace the "x-" naming convention by specia
The code to check policy for handling deprecated input is triplicated.
Factor it out into compat_policy_input_ok() before I mess with it in
the next commit.
Signed-off-by: Markus Armbruster
---
include/qapi/compat-policy.h | 7 +
qapi/qapi-visit-core.c | 18 +
qapi/qmp-dis
By convention, names starting with "x-" are experimental. The parts
of external interfaces so named may be withdrawn or changed
incompatibly in future releases.
Drawback: promoting something from experimental to stable involves a
name change. Client code needs to be updated.
Moreover, the conve
The code to check enumeration value policy can see special feature
flag 'deprecated' in QEnumLookup member flags[value]. I want to make
feature flag 'unstable' visible there as well, so I can add policy for
it.
Instead of extending flags[], replace it by @special_features (a
bitset of QapiSpecial
New option parameters unstable-input and unstable-output set policy
for unstable interfaces just like deprecated-input and
deprecated-output set policy for deprecated interfaces (see commit
6dd75472d5 "qemu-options: New -compat to set policy for deprecated
interfaces"). This is intended for testin
The generated visitor functions call visit_deprecated_accept() and
visit_deprecated() when visiting a struct member with special feature
flag 'deprecated'. This makes the feature flag visible to the actual
visitors. I want to make feature flag 'unstable' visible there as
well, so I can add policy
Add special feature 'unstable' everywhere the name starts with 'x-',
except for InputBarrierProperties member x-origin and
MemoryBackendProperties member x-use-canonical-path-for-ramblock-id,
because these two are actually stable.
Signed-off-by: Markus Armbruster
---
qapi/block-core.json | 123 +
The code to check command policy can see special feature flag
'deprecated' as command flag QCO_DEPRECATED. I want to make feature
flag 'unstable' visible there as well, so I can add policy for it.
To let me make it visible, add member @special_features (a bitset of
QapiSpecialFeature) to QmpComma
New enum QapiSpecialFeature enumerates the special feature flags.
New helper gen_special_features() returns code to represent a
collection of special feature flags as a bitset.
The next few commits will put them to use.
Signed-off-by: Markus Armbruster
---
include/qapi/util.h| 4
scr
Signed-off-by: Markus Armbruster
---
include/qapi/qmp/dispatch.h | 1 -
monitor/misc.c | 3 +--
scripts/qapi/commands.py| 5 +
3 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/include/qapi/qmp/dispatch.h b/include/qapi/qmp/dispatch.h
index 075203dc67..0ce88200b9
I neglected to put RFC in the subject.
Markus Armbruster writes:
> The next commit will add feature flags to enum members. There's a
> problem, though: query-qmp-schema shows an enum type's members as an
> array of member names (SchemaInfoEnum member @values). If it showed
> an array of objects with a name member, we could simply ad
[Expired for OpenStack Compute (nova) because there has been no activity
for 60 days.]
** Changed in: nova
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1761798
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1761798
Title:
live migrat
The next commit will add feature flags to enum members. There's a
problem, though: query-qmp-schema shows an enum type's members as an
array of member names (SchemaInfoEnum member @values). If it showed
an array of objects with a name member, we could simply add more
members to these objects. Si
This copies the code implementing the policy from qapi/qmp-dispatch.c
to qapi/qobject-input-visitor.c. Tolerable, but if we acquire more
copies, we should look into factoring them out.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
Tested-by: Peter Krempa
Acked-by: Peter Krempa
---
This is quite similar to commit 84ab008687 "qapi: Add feature flags to
struct members", only for enums instead of structs.
Special feature flag 'deprecated' is silently ignored there. This is
okay only because it will be implemented shortly.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Bl
PATCH 1+2 add feature flags to enum members. Awkward due to an
introspection design mistake; see PATCH 1 for details.
PATCH 3+4 implement policy deprecated-input={reject,crash} for enum
values.
Policy deprecated-output=hide is not implemented, because we can't
hide a value without hiding the ent
The next commit needs to access compat policy from the generic visitor
core. Move it there from qobject input and output visitor.
Signed-off-by: Markus Armbruster
Reviewed-by: Eric Blake
---
include/qapi/qobject-input-visitor.h | 4
include/qapi/qobject-output-visitor.h | 4
inclu
Several moons ago, Vladimir posted
Subject: [PATCH v2 3/3] qapi: deprecate drive-backup
Date: Wed, 5 May 2021 16:58:03 +0300
Message-Id: <20210505135803.67896-4-vsement...@virtuozzo.com>
https://lists.gnu.org/archive/html/qemu-devel/2021-05/msg01394.html
with this
TODO: We a
On Sat, Oct 23, 2021 at 4:23 AM Alexey Baturo wrote:
>
> v15:
> Renamed pm into pointer_masking in machine state.
>
> v14:
> Addressed Richard's comments from previous series.
>
> v13:
> Rebased QEMU and addressed Richard's comment.
>
> v12:
> Updated function for adjusting address with pointer ma
On Mon, Oct 25, 2021 at 12:07 PM Alistair Francis
wrote:
>
> From: Alistair Francis
>
> Fixup the PLIC context address to correctly support the threshold and
> claim register.
>
> Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
> Signed-off-by: Alistair Francis
> ---
> hw/
From: Alistair Francis
Fixup the PLIC context address to correctly support the threshold and
claim register.
Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build")
Signed-off-by: Alistair Francis
---
hw/riscv/opentitan.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
On Sat, Oct 23, 2021 at 4:27 AM Alexey Baturo wrote:
>
> Signed-off-by: Alexey Baturo
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6b767a4a0b..16fac64806 10064
On 10/24/21 12:42 AM, Paolo Bonzini wrote:
On 22/10/21 20:31, Richard Henderson wrote:
Hi Daniel, you win the cookie because you committed cirrus.yml.
I should have reported this before the weekend, but at some point this week the auth
tokens expired(?). All of the cirrus-run tests are now fa
On Sun, Oct 24, 2021 at 06:16:19PM +0200, Philippe Mathieu-Daudé wrote:
> Avoid using a TCG temporary by moving the MemOp index
> to the constant pool.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> target/ppc/translate.c | 29 +
> 1 file
On Sun, Oct 24, 2021 at 06:16:18PM +0200, Philippe Mathieu-Daudé wrote:
> Avoid using a TCG temporary by moving the compared values
> to the constant pool.
>
> Signed-off-by: Philippe Mathieu-Daudé
Acked-by: David Gibson
> ---
> target/ppc/translate.c | 11 ---
> 1 file changed, 4 ins
I have a question about the emulation of streams and UASP with the two xhci
controller options QEMU supports: qemu-xhci and nec-usb-xhci
It is my understanding that the UASP code checks to see if streams are
supported by simply checking if the device is a Super Speed Device?
https://gitlab.com/
Le 20/10/2021 à 21:06, Richard Henderson a écrit :
> On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
>
> Hmm. 3 * (and + shift + cmp + cmov) + 2 * (sub + or) = 16 ops.
> Not horrible...
>
> Let's see.
>
> ls = sh & 63; 1
> rs = -sh & 63; 3
> hs = sh & 64; 4
>
>
On 10/24/21 9:16 AM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary by moving the MemOp index
to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
Reviewed-by:
On 10/24/21 9:16 AM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary by moving the compared values
to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderso
On 10/24/21 9:16 AM, Philippe Mathieu-Daudé wrote:
The immediate value used for comparison is constant and
read-only. Move it to the constant pool. This frees a
TCG temporary for unsigned saturation opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate-sve.c | 17
On 10/24/21 9:16 AM, Philippe Mathieu-Daudé wrote:
Avoid using a TCG temporary by moving the flag and
exception address to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
Reviewed-by: Richar
On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
While the first 'off' variable assignment is unused, it helps
to better understand the code logic. Move the assignation where
it would have been used so it is easier to compare the MSA
registers based on FPU ones versus the MSA specific registers
On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
Only the MSA generic opcode was overlapping with the other
instructions. Since the previous commit removed it, we can
now remove the overlap group. The decodetree script forces
us to re-indent the opcodes.
Diff trivial to review using `git-diff
On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 --
target/mips/tcg/msa_translate.c | 7 ---
2 files change
On 10/23/21 2:48 PM, Philippe Mathieu-Daudé wrote:
Convert the CFCMSA (Copy From Control MSA register) and
CTCMSA (Copy To Control MSA register) opcodes to decodetree.
Since they respectively overlap with the SLDI and SPLATI
opcodes, use decodetree overlap groups.
Signed-off-by: Philippe Mathie
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+tsr = tcg_const_i32(a->ws);
+tdt = tcg_const_i32(a->wd);
tcg_constant_i32. Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 +
target/mips/tcg/msa_translate.c | 92 --
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+#define TRANS_DF_W64(NAME, trans_func, gen_func) \
+TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+DF_HALF, DF_WORD, \
+gen_func##_b, gen_func##_h, gen_func##_w, NULL)
Again with the tab
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_elm_df(DisasContext *ctx, arg_msa_elm *a,
+ void (*gen_msa_elm_df)(TCGv_ptr, TCGv_i32,
+TCGv_i32, TCGv_i32,
+
On 10/24/21 11:57 AM, Philippe Mathieu-Daudé wrote:
On 10/24/21 19:52, Richard Henderson wrote:
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32,
TCGv_i32,
+
On 10/24/21 20:26, Jiaxun Yang wrote:
> Thanks that's really helpful!
>
> For the whole series:
>
> Reviewed-by: Jiaxun Yang
>
> Double checked decode tree opcode with manual.
Thank you!
I'll respin addressing Richard comments but won't change the
msa.decode file, so I'll include your R-b ta
On 10/24/21 19:52, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
>> + void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32,
>> TCGv_i32,
>> +
在 2021/10/23 22:47, Philippe Mathieu-Daudé 写道:
Hi,
This series converts 2000+ lines of switch() code to decodetree
description, so this hard-to-review/modify switch is auto generated
by the decodetree script. This is a big win for maintenance (and
indeed the convertion revealed 2 bugs).
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert 3-register operations to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 53 ++
target/mips/tcg/msa_translate.c | 916 ++--
2 files changed, 106 insertions(+), 863
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 3 +++
target/mips/tcg/msa_translate.c | 37 +++
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
+ void (*gen_msa_3r_b)(TCGv_ptr, TCGv_i32,
+ TCGv_i32, TCGv_i32),
+ void (*gen_msa_3r_h)(TCGv_
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
+void (*gen_msa_3r_df)(TCGv_ptr, TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_i32))
+{
+TCGv_i32 tdf = tcg_cons
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+TCGv_i32 twd = tcg_const_i32(a->wd);
+TCGv_i32 tws = tcg_const_i32(a->ws);
+TCGv_i32 twt = tcg_const_i32(a->wt);
tcg_constant_i32, otherwise,
Reviewed-by: Richard Henderson
r~
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert 3-register floating-point or fixed-point operations
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 37 ++
target/mips/tcg/msa_translate.c | 213 ++--
2 file
On 10/24/21 10:37 AM, Richard Henderson wrote:
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+ enum CPUMIPSMSADataFormat df_base,
+ void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+ enum CPUMIPSMSADataFormat df_base,
+ void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
+
On 10/24/21 9:44 AM, Philippe Mathieu-Daudé wrote:
On 10/24/21 07:04, Richard Henderson wrote:
On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
Convert the FILL opcode (Vector Fill from GPR) to decodetree.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/msa.decode | 2 ++
On 10/24/21 07:04, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> Convert the FILL opcode (Vector Fill from GPR) to decodetree.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/mips/tcg/msa.decode | 2 ++
>> target/mips/tcg/msa_translate.c | 4
Avoid using a TCG temporary by moving the MemOp index
to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 29 +
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5
Avoid using a TCG temporary by moving the flag and
exception address to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/alpha/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index a4c
The immediate value used for comparison is constant and
read-only. Move it to the constant pool. This frees a
TCG temporary for unsigned saturation opcodes.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/translate-sve.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-
Avoid using a TCG temporary by moving the compared values
to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 518337bcb7f..507f
Few more cases where we can use tcg_constant().
Philippe Mathieu-Daudé (4):
target/alpha: Use tcg_constant_i64() in gen_call_pal()
target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
target/ppc: Use tcg_constant_tl() in gen_op_cmp()
target/ppc: Use tcg_constant_i32() in gen_ld/st()
This is a bugfix that stretches all the way back to January 2020,
where I initially introduced this problem and potential solutions.
A quick recap of the issue: QEMU did not sync up with the monitors
refresh rate causing the VM to render frames that were NOT displayed
to the user. That "fix" allow
On 10/24/21 02:40, BALATON Zoltan wrote:
> This fixes coding style of files belonging to SH4 system emulation
> which were not following current QEMU coding style requirements.
>
> BALATON Zoltan (5):
> hw/sh4: Coding style: Remove tabs
> hw/sh4: Coding style: Fix multi-line comments
> hw/sh
On 10/24/21 03:02, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> Have check_msa_access() return a boolean value so we can
>> return early if MSA is not enabled.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> target/mips/tcg/msa_translate.c | 20 +
On 10/24/21 06:53, Richard Henderson wrote:
> On 10/23/21 2:47 PM, Philippe Mathieu-Daudé wrote:
>> +#define TRANS_DF_E(NAME, trans_func, gen_func) \
>> + TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
>> + gen_func##_b, gen_func##_h, gen_func##_w,
>> gen_func##_d)
On 22/10/21 20:31, Richard Henderson wrote:
Hi Daniel, you win the cookie because you committed cirrus.yml.
I should have reported this before the weekend, but at some point this
week the auth tokens expired(?). All of the cirrus-run tests are now
failing:
cirrus_run.api.CirrusAPIError: API
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