Re: [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs

[Alistair Francis]

On Fri, Oct 15, 2021 at 6:44 PM <frank.ch...@sifive.com> wrote:
>
> From: Frank Chang <frank.ch...@sifive.com>
>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>

Hey Frank,

You will need to rebase this on the latest master branch.

Alistair

> ---
>  target/riscv/csr.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9f51626a3d8..3929abb112a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -224,7 +224,8 @@ static RISCVException write_fflags(CPURISCVState *env, 
> int csrno,
>                                     target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
> +    env->mstatus |= MSTATUS_FS | sd;
>  #endif
>      riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>      return RISCV_EXCP_NONE;
> @@ -241,7 +242,8 @@ static RISCVException write_frm(CPURISCVState *env, int 
> csrno,
>                                  target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
> +    env->mstatus |= MSTATUS_FS | sd;
>  #endif
>      env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
>      return RISCV_EXCP_NONE;
> @@ -259,7 +261,8 @@ static RISCVException write_fcsr(CPURISCVState *env, int 
> csrno,
>                                   target_ulong val)
>  {
>  #if !defined(CONFIG_USER_ONLY)
> -    env->mstatus |= MSTATUS_FS;
> +    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
> +    env->mstatus |= MSTATUS_FS | sd;
>  #endif
>      env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>      riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> --
> 2.25.1
>
>