From: Cai Huoqing
Fix typo:
*informations ==> information
*enougth ==> enough
*enouth ==> enough
*registy ==> registry
*releated ==> related
*Ouptut ==> Output
*manualy ==> manually
*Attemping ==> Attempting
*contine ==> continue
*tranceiver ==> transceiver
*Tranceiver ==> Transceiver
The following changes since commit ad22d0583300df420819e6c89b1c022b998fac8a:
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827'
into staging (2021-08-27 11:34:12 +0100)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/usb-20210901-pull-request
The device uses the guest-supplied stream number unchecked, which can
lead to guest-triggered out-of-band access to the UASDevice->data3 and
UASDevice->status3 fields. Add the missing checks.
Fixes: CVE-2021-3713
Signed-off-by: Gerd Hoffmann
Reported-by: Chen Zhe
Reported-by: Tan Jingguo
Revie
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:37 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATCH v5 4/4] hw/arm/virt:
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:02 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATCH v5 2/4] hw/arm/smmuv
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:13 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATCH v5 3/4] hw/arm/virt:
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:02 PM
> To: chunming; peter.mayd...@linaro.org
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Wen, Jianxian; Liu,
> Renwei; Li, Chunming
> Subject: Re: [PATCH v5 1/4] hw/arm/smmuv3
On 9/1/21 1:31 AM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> This is a follow-up to a discussion in a previous series I sent:
>
> https://lore.kernel.org/qemu-devel/20210827210417.4022054-1-p...@fb.com/
>
> I tried to add a new machine type called Fuji that required the ability
> to speci
在 2021/8/31 上午1:07, Yuri Benditovich 写道:
On Fri, Aug 20, 2021 at 6:41 AM Jason Wang wrote:
在 2021/7/13 下午11:37, Andrew Melnychenko 写道:
Helper program. Loads eBPF RSS program and maps and passes them through unix
socket.
Libvirt may launch this helper and pass eBPF fds to qemu virtio-net.
在 2021/8/26 上午2:24, Andrew Melnichenko 写道:
Hi,
I wonder if this can be done as helper for TAP/bridge.
Well, it does already, libvirt may create TAP device and pass it in
command line or using getfd qmp command.
E.g it's the qemu to launch those helper with set-uid.
Then libvir
Adding Peter Maydell and Joel.
On 9/1/21 1:31 AM, p...@fb.com wrote:
> From: Peter Delevoryas
>
> When you run QEMU with an Aspeed machine and a single serial device
> using stdio like this:
>
> qemu -machine ast2600-evb -drive ... -serial stdio
>
> The guest OS can read and write to the U
> -Original Message-
> From: Eric Auger [mailto:eric.au...@redhat.com]
> Sent: Tuesday, August 31, 2021 10:46 PM
> To: Liu, Renwei; Peter Maydell
> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org; Li, Chunming; Wen,
> Jianxian
> Subject: Re: [PATCH v2] hw/arm/smmuv3: Simplify range invalidat
> I already gave my r-b on the last posting, but here it is again
>
> Reviewed-by: Andrew Jones
Sorry, We overlooked that.
Thank you:)
Best regards,
> -Original Message-
> From: Andrew Jones
> Sent: Tuesday, August 31, 2021 7:20 PM
> To: Ishii, Shuuichirou/石井 周一郎
> Cc: peter.mayd...@
Hi folks,
I have a bunch of unreviewed patches for cocoa sitting in my patch
mailbox. If you are Cc'ed you are one of the patch authors.
I simply don't have the macos expertise to do a proper review for most
patches, specifically the macos interface parts. So, if you want help
improve cocoa s
From: Philippe Mathieu-Daudé
Split the Audio backends into multiple sections (OS / framework /
library), allowing developers with different interests to add their
contact to the relevant entries.
Suggested-by: Gerd Hoffmann
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Christian Schoenebe
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Christian Schoenebeck
Message-Id: <20210816191014.2020783-2-phi...@redhat.com>
Signed-off-by: Gerd Hoffmann
---
MAINTAINERS | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/MAIN
From: Philippe Mathieu-Daudé
SPICE audio is already covered in the SPICE section,
so remove it from the Audio backends one.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Christian Schoenebeck
Message-Id: <20210816191014.2020783-3-phi...@redhat.com>
Signed-off-by: Gerd Hoffmann
---
MAINT
The following changes since commit ad22d0583300df420819e6c89b1c022b998fac8a:
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827'
into staging (2021-08-27 11:34:12 +0100)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/audio-20210901-pull-request
From: Helge Deller
The CDE desktop on HP-UX 10 shows wrongly rendered pixels when the local screen
menu is closed. This bug was introduced by commit c7050f3f167b
("hw/display/artist: Refactor x/y coordination extraction") which converted the
coordinate extraction in artist_vram_read() and artist_
From: "Jose R. Ziviani"
If users try to add an isa-vga device that was already registered,
still in command line, qemu will crash:
$ qemu-system-mips64el -M pica61 -device isa-vga
RAMBlock "vga.vram" already registered, abort!
Aborted (core dumped)
That particular board registers the device aut
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20210823100454.615816-3-phi...@redhat.com>
Signed-off-by: Gerd Hoffmann
---
include/ui/console.h | 2 ++
ui/udmabuf.c | 11 ---
ui/meson.build | 6 --
3 files changed, 6 insertions(+), 1
From: Qiang Liu
xlnx_dp_read allows an out-of-bounds read at its default branch because
of an improper index.
According to
https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
(DP Module), registers 0x3A4/0x3A4/0x3AC are allowed.
DP_INT_MASK 0x03A4
From: Philippe Mathieu-Daudé
When using qemu configured with --enabled-modules, the
generic stubs are used instead of the module symbols:
qemu-system-x86_64: -device virtio-vga,blob=on: cannot enable blob resources
without udmabuf
Restrict the stubs to Linux and only link them when
CONFIG_VI
From: Dongwon Kim
The code should check the opposite condition of res->iov because it will be null
if virtio_gpu_create_mapping_iov fails and actually this checking is not even
required because checking on ret covers all failing cases.
Signed-off-by: Dongwon Kim
Message-Id: <20210830175033.2923
The following changes since commit ad22d0583300df420819e6c89b1c022b998fac8a:
Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827'
into staging (2021-08-27 11:34:12 +0100)
are available in the Git repository at:
git://git.kraxel.org/qemu tags/vga-20210901-pull-request
At present when input clock is disabled, any character transmitted
to tx fifo can still show on the serial line, which is wrong.
Fixes: b636db306e06 ("hw/char/cadence_uart: add clock support")
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
hw/char/cadence_uart
This converts uart_read() and uart_write() to memop_with_attrs() ops.
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: hw/char: cadence_uart: Convert to memop_with_attrs() ops
hw/char/cadence_uart.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
dif
Read or write to uart registers when unclocked or in reset should be
ignored. Add the check there, and as a result of this, the check in
uart_write_tx_fifo() is now unnecessary.
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: hw/char: cadence_uart: Ignore access when unclocked or in res
As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as
per the logic in uart_receive().
>From zynq_slcr_reset_exit() comment, it intends to compute
Currently the clock/reset check is done in uart_receive(), but we
can move the check to uart_can_receive() which is earlier.
Signed-off-by: Bin Meng
---
Changes in v2:
- avoid declaring variables mid-scope
hw/char/cadence_uart.c | 17 ++---
1 file changed, 10 insertions(+), 7 dele
As of today, when booting upstream U-Boot for Xilinx Zynq, the UART
does not receive anything. Debugging shows that the UART input clock
frequency is zero which prevents the UART from receiving anything as.
per the logic in uart_receive().
Note the U-Boot can still output data to the UART tx fifo,
On Tue, Aug 31, 2021 at 02:15:36PM +0200, Gerd Hoffmann wrote:
> Signed-off-by: Gerd Hoffmann
ppc part
Acked-by: David Gibson
> ---
> include/exec/exec-all.h | 2 +-
> include/tcg/tcg-module.h| 1 +
> accel/tcg/cpu-exec-common.c | 2 +-
> accel/tcg/tcg-module.c
On Tue, Aug 31, 2021 at 09:42:05AM +0200, Cédric Le Goater wrote:
> On 8/30/21 6:04 PM, Michal Suchánek wrote:
> > On Mon, Aug 30, 2021 at 04:57:21PM +1000, David Gibson wrote:
> >> On Sun, Aug 29, 2021 at 04:09:54AM +, Joseph wrote:
> >>> Hi Mark, Cédric, Greg at the openbsd-ppc ML,
> >
> >>
From: Richard Henderson
Exit early if check_access fails.
Split out do_hlv, do_hsv, do_hlvx subroutines.
Use dest_gpr, get_gpr in the new subroutines.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-24-richar
From: Richard Henderson
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-23-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvd.c.inc | 125
1 file ch
From: Richard Henderson
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-22-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvf.c.inc | 146
1 file ch
On Tue, Aug 31, 2021 at 04:31:40PM -0700, p...@fb.com wrote:
> From: Peter Delevoryas
>
> When you run QEMU with an Aspeed machine and a single serial device
> using stdio like this:
>
> qemu -machine ast2600-evb -drive ... -serial stdio
>
> The guest OS can read and write to the UART5 regi
From: Richard Henderson
Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-21-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_t
On Tue, 31 Aug 2021, Mark Cave-Ayland wrote:
> You mentioned that the OS may compensate for the fact that the 6522
> doesn't have an overflow flag: can you explain more as to how this works
> in Linux?
When running on real hardware, Linux/mac68k does so by
- Elevating the interrupt priority o
From: Richard Henderson
We failed to write into *val for these read functions;
replace them with read_zero. Only warn about unsupported
non-zero value when writing a non-zero value.
Signed-off-by: Richard Henderson
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 2021082319552
From: Richard Henderson
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-16-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc | 38 +
1 file ch
From: Richard Henderson
These operations can be done in one instruction on some hosts.
Signed-off-by: Richard Henderson
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-14-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn
From: Richard Henderson
Use ctx->w for ctpopw, which is the only one that can
re-use the generic algorithm for the narrow operation.
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-12-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
From: Richard Henderson
Remove gen_get_gpr, as the function becomes unused.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-25-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/translate.c| 13 ++---
From: Richard Henderson
Narrow the scope of t0 in trans_jalr.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-15-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvi.c.inc |
From: Richard Henderson
These operations are greatly simplified by ctx->w, which allows
us to fold gen_shiftw into gen_shift. Split gen_shifti into
gen_shift_imm_{fn,tl} like we do for gen_arith_imm_{fn,tl}.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
From: Richard Henderson
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvb.c.inc.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-11-richard.hender..
From: Richard Henderson
Move these helpers near their use by the trans_*
functions within insn_trans/trans_rvm.c.inc.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-10-richard.hender..
From: Richard Henderson
Reviewed-by: Bin Meng
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-20-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 47 ++---
1 file ch
From: Richard Henderson
Split out gen_mulh and gen_mulhu and use the common helper.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-9-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/insn_tra
From: Richard Henderson
Introduce csrr and csrw helpers, for read-only and write-only insns.
Note that we do not properly implement this in riscv_csrrw, in that
we cannot distinguish true read-only (rs1 == 0) from any other zero
write_mask another source register -- this should still raise an
ex
From: Richard Henderson
We will require the context to handle RV64 word operations.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-5-richard.hender...@linaro.org
Signed-off-by: Alistai
From: Richard Henderson
Introduce get_gpr, dest_gpr, temp_new -- new helpers that do not force
tcg globals into temps, returning a constant 0 for $zero as source and
a new temp for $zero as destination.
Introduce ctx->w for simplifying word operations, such as addw.
Reviewed-by: Bin Meng
Revie
From: Richard Henderson
Use ctx->w and the enhanced gen_arith function.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-8-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/translate.c
From: Richard Henderson
Most arithmetic does not require extending the inputs.
Exceptions include division, comparison and minmax.
Begin using ctx->w, which allows elimination of gen_addw,
gen_subw, gen_mulw.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
From: Richard Henderson
We distinguish write-only by passing ret_value as NULL.
Signed-off-by: Richard Henderson
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210823195529.560295-17-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 23
From: Richard Henderson
Replace uses of tcg_const_* with the allocate and free close together.
Reviewed-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-2-richard.hender...@linaro.org
Signed-off-
From: Richard Henderson
Utilize the condition in the movcond more; this allows some of
the setcond that were feeding into movcond to be removed.
Do not write into source1 and source2. Re-name "condN" to "tempN"
and use the temporaries for more than holding conditions.
Tested-by: Bin Meng
Revie
From: Richard Henderson
Tested-by: Bin Meng
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
Message-id: 20210823195529.560295-3-richard.hender...@linaro.org
Signed-off-by: Alistair Francis
---
tests/tcg/riscv64/test-div.c | 58 ++
From: Bin Meng
When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned,
not -1 (RISCV_EXCP_NONE).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Message-id: 20210807141025.31808-1-bmeng...@gmail.com
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 2 +-
1 file changed,
From: David Hoppenbrouwers
`muldiv64` would overflow in cases where the final 96-bit value does not
fit in a `uint64_t`. This would result in small values that cause an
interrupt to be triggered much sooner than intended.
The overflow can be detected in most cases by checking if the new value is
From: LIU Zhiwei
For U-mode CSRs, read-only check is also needed.
Signed-off-by: LIU Zhiwei
Reviewed-by: Bin Meng
Message-id: 20210810014552.4884-1-zhiwei_...@c-sky.com
Signed-off-by: Alistair Francis
---
target/riscv/csr.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff
From: Bin Meng
The flash is not inside the SoC, so it's inappropriate to put it
under the /soc node. Move it to root instead.
Signed-off-by: Bin Meng
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 20210807035641.22449-1-bmeng...@gmail.com
Signed-off-by: Alistair
From: Joe Komlodi
If we have a field that's wider than 32-bits, we need a data type wide enough to
be able to create the bitfield used to deposit the value.
Signed-off-by: Joe Komlodi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-id: 1626805903-162860-3-git-send-em
From: Joe Komlodi
We already have some utilities to handle 64-bit wide registers, so this just
adds some more for:
- Initializing 64-bit registers
- Extracting and depositing to an array of 64-bit registers
Signed-off-by: Joe Komlodi
Reviewed-by: Alistair Francis
Message-id: 1626805903-162860-
From: Peter Maydell
In the riscv virt machine init function, We assemble a string
plic_hart_config which is a comma-separated list of N copies of the
VIRT_PLIC_HART_CONFIG string. The code that does this has a
misunderstanding of the strncat() length argument. If the source
string is too large
From: LIU Zhiwei
For some cpu, the isa version has already been set in cpu init function.
Thus only override the isa version when isa version is not set, or
users set different isa version explicitly by cpu parameters.
Signed-off-by: LIU Zhiwei
Reviewed-by: Bin Meng
Message-id: 20210811144612.
From: Vijai Kumar K
Use a dedicated UART config(CONFIG_SHAKTI_UART) to select
shakti uart.
Signed-off-by: Vijai Kumar K
Reviewed-by: Alistair Francis
Message-id: 20210731190229.137483-1-vi...@behindbytes.com
Signed-off-by: Alistair Francis
---
hw/char/Kconfig | 3 +++
hw/char/meson.build
From: Alistair Francis
The following changes since commit d52dff5d8048d4982437db9606c27bb4127cf9d0:
Merge remote-tracking branch 'remotes/marcandre/tags/clip-pull-request' into
staging (2021-08-31 14:38:15 +0100)
are available in the Git repository at:
g...@github.com:alistair23/qemu.git
From: Peter Delevoryas
This is a follow-up to a discussion in a previous series I sent:
https://lore.kernel.org/qemu-devel/20210827210417.4022054-1-p...@fb.com/
I tried to add a new machine type called Fuji that required the ability
to specify the UART connected to the first serial device on th
From: Peter Delevoryas
When you run QEMU with an Aspeed machine and a single serial device
using stdio like this:
qemu -machine ast2600-evb -drive ... -serial stdio
The guest OS can read and write to the UART5 registers at 0x1E784000 and
it will receive from stdin and write to stdout. The A
On Tue, 31 Aug 2021, Mark Cave-Ayland wrote:
> On 28/08/2021 02:22, Finn Thain wrote:
>
> > > On 8/24/21 12:09 PM, Finn Thain wrote:
> > >
> > > > On a real Quadra, accesses to the SY6522 chips are slow because they are
> > > > synchronous with the 783360 Hz "phase 2" clock. In QEMU, they are sl
On 8/31/21 10:27 PM, Peter Maydell wrote:
> On Mon, 23 Aug 2021 at 09:54, Philippe Mathieu-Daudé
> wrote:
>>
>> Per Peter Maydell [*]:
>>
>> 'info mtree' monitor command was designed on the assumption that
>> there's really only one or two interesting address spaces, and
>> with more recent
> On Aug 31, 2021, at 5:08 PM, BALATON Zoltan wrote:
>
> On Tue, 31 Aug 2021, Programmingkid wrote:
>>> On Aug 30, 2021, at 5:47 PM, BALATON Zoltan wrote:
>
>>> On Mon, 30 Aug 2021, Peter Maydell wrote:
On Mon, 30 Aug 2021 at 21:29, Programmingkid
wrote:
> I found out that th
On Tue, Aug 31, 2021 at 08:02:36AM -0300, Leonardo Bras wrote:
> Results:
> So far, the resource usage of __sys_sendmsg() reduced 15 times, and the
> overall migration took 13-18% less time, based in synthetic workload.
Leo,
Could you share some of the details of your tests? E.g., what's the
con
On 8/24/2021 5:36 AM, Zheng Chuan wrote:
> Hi, Steve.
>
> I think I have found the problem, it is because the rom_reset() during the
> cpr_exec will write dtb into the mach-virt.ram which cause the memory
> corruption.
> Also I found in x86 the memoryregion of acpi also changed during rom_rest.
On 28/08/2021 02:22, Finn Thain wrote:
On 8/24/21 12:09 PM, Finn Thain wrote:
On a real Quadra, accesses to the SY6522 chips are slow because they are
synchronous with the 783360 Hz "phase 2" clock. In QEMU, they are slow
only because of the division operation in the timer count calculation.
On Tue, 31 Aug 2021, Programmingkid wrote:
On Aug 30, 2021, at 5:47 PM, BALATON Zoltan wrote:
On Mon, 30 Aug 2021, Peter Maydell wrote:
On Mon, 30 Aug 2021 at 21:29, Programmingkid wrote:
I found out that there are two pc-bios folders. One in the root directory
and one in the build directo
> On Aug 31, 2021, at 4:33 PM, Mark Cave-Ayland
> wrote:
>
> On 31/08/2021 17:50, John Arbuckle wrote:
>
>> Currently the file qemu_vga.ndrv is not copied into the /build/pc-bios
>> folder. This makes all video resolution choices disappear from a PowerPC Mac
>> OS guest. This patch has the
On 31/08/2021 17:50, John Arbuckle wrote:
Currently the file qemu_vga.ndrv is not copied into the /build/pc-bios folder.
This makes all video resolution choices disappear from a PowerPC Mac OS guest.
This patch has the qemu_vga.ndrv file copied into the build/pc-bios folder
giving users back
On Thu, 26 Aug 2021 at 19:07, Philippe Mathieu-Daudé wrote:
>
> Minor cleanups on the GICv3 distributor common accessors to
> have the overall codebase better use the MEMTX_* constants.
>
> No logical code change intended.
>
> Philippe Mathieu-Daudé (2):
> hw/intc/arm_gicv3_dist: Rename 64-bit a
On Tue, Aug 31, 2021 at 02:16:42PM +0100, Daniel P. Berrangé wrote:
> On Tue, Aug 31, 2021 at 08:02:39AM -0300, Leonardo Bras wrote:
> > Call qio_channel_set_zerocopy(true) in the start of every multifd thread.
> >
> > Change the send_write() interface of multifd, allowing it to pass down
> > flag
On Mon, 23 Aug 2021 at 09:54, Philippe Mathieu-Daudé wrote:
>
> Per Peter Maydell [*]:
>
> 'info mtree' monitor command was designed on the assumption that
> there's really only one or two interesting address spaces, and
> with more recent developments that's just not the case any more.
>
>
On Tue, Aug 31, 2021 at 01:57:33PM +0100, Daniel P. Berrangé wrote:
> On Tue, Aug 31, 2021 at 08:02:38AM -0300, Leonardo Bras wrote:
> > MSG_ZEROCOPY is a feature that enables copy avoidance in TCP/UDP socket
> > send calls. It does so by avoiding copying user data into kernel buffers.
> >
> > To
On Fri, 27 Aug 2021 at 07:08, Philippe Mathieu-Daudé wrote:
>
> Since v2:
> - updated "Since 6.1" -> "Since 6.2"
>
> Peter reported CI failure [*] but I can't reproduce:
> https://gitlab.com/philmd/qemu/-/pipelines/360227279
'make check' seems to work for me too this time...
Applied to target-ar
On Tue, 31 Aug 2021 at 14:31, wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit ad22d0583300df420819e6c89b1c022b998fac8a:
>
> Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827'
> into staging (2021-08-27 11:34:12 +0100)
>
> are available in the G
On Tue, 31 Aug 2021 at 19:34, Michael Tokarev wrote:
>
> We test whenever the path of unix-domain socket
> address is non-empty and strictly-less than
> the length of the path buffer. Both these
> conditions are wrong: the socket can be unnamed,
> with empty path, or socket can have pathname
> nul
Hi,
> Got something I could git-pull?
>
I can share some links for tests:
https://github.com/daynix/qemu/tree/HelperEBPFv3 - qemu with helper
https://github.com/daynix/libvirt/tree/RSS_RFC_v1 - libvirt with RSS
On Tue, Aug 31, 2021 at 6:00 PM Markus Armbruster wrote:
> Yuri Benditovich writes:
Signed-off-by: Vladislav Yaroshchuk
---
qemu-options.hx | 17 +
1 file changed, 17 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 83aa59a920..b5d1cbd49a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2655,6 +2655,17 @@ DEF("netdev", HAS_ARG, QEMU_OPTIO
Still not implemented:
- port forwarding
- ipv6 prefix setting
Signed-off-by: Vladislav Yaroshchuk
---
net/meson.build| 2 +-
net/vmnet-common.c | 20 ---
net/vmnet-common.m | 294 +
net/vmnet-shared.c | 73 ++-
net/vmnet_int.h| 23
Still not implemented:
- port forwarding
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-host.c | 75 ++--
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/net/vmnet-host.c b/net/vmnet-host.c
index 1d3484b51e..77a2c20b48 100644
--- a/ne
Signed-off-by: Vladislav Yaroshchuk
---
net/meson.build | 8 +++-
net/vmnet-bridged.c | 25 +
net/vmnet-common.c | 20
net/vmnet-host.c| 24
net/vmnet-shared.c | 25 +
net/vmnet.c
Signed-off-by: Vladislav Yaroshchuk
---
net/meson.build | 2 +-
net/vmnet-bridged.c | 25 -
net/vmnet-bridged.m | 123
3 files changed, 124 insertions(+), 26 deletions(-)
delete mode 100644 net/vmnet-bridged.c
create mode 100644 net/vm
Add 'vmnet' customizable option and 'vmnet.framework' probe into
configure;
Create separate netdev per each vmnet operating mode
because they use quite different settings. Especially since
macOS 11.0 (vmnet.framework API gets lots of updates)
Create source files for network client driver, update m
macOS provides networking API for VMs called vmnet.framework.
I tried to add it as a network backend. All three modes are supported:
-shared:
allows the guest to comminicate with other guests in shared mode and
also with external network (Internet) via NAT
-host:
allows the guest to communi
31.08.2021 22:21, Marc-André Lureau wrote:
...
Seems right to me, however there are some notes in libc bits/socket.h
/* Structure large enough to hold any socket address (with the historical
exception of AF_UNIX). */
And also this
https://idea.popcount.org/2019-12-06-addressing/#fn:sockadd
Hi
On Tue, Aug 31, 2021 at 10:26 PM Michael Tokarev wrote:
> We test whenever the path of unix-domain socket
> address is non-empty and strictly-less than
> the length of the path buffer. Both these
> conditions are wrong: the socket can be unnamed,
> with empty path, or socket can have pathname
We test whenever the path of unix-domain socket
address is non-empty and strictly-less than
the length of the path buffer. Both these
conditions are wrong: the socket can be unnamed,
with empty path, or socket can have pathname
null-terminated _after_ the sun_path buffer,
since we provided more roo
On Tue, Aug 31, 2021 at 01:39:50PM -0300, Luis Pires wrote:
> Move abs64 to host-utils as uabs64, so it can be used elsewhere.
> The function was renamed to uabs64 and modified to return an
> unsigned value. This avoids the undefined behavior for common
> abs implementations, where abs of the most
On 8/31/21 9:39 AM, Luis Pires wrote:
+DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
Shouldn't be upcase. None of the others are.
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5489b4b6e0..c3739f7370 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7422
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