On 05.08.21 21:34, Eduardo Habkost wrote:
We have a SCLPEventsBus struct defined, but the struct is not
used at the TypeInfo definition. This works today but will break
silently if anybody adds a new field to SCLPEventsBus.
Set instance_size properly to avoid problems in the future.
Signed-off
On 06.08.21 06:15, Thomas Huth wrote:
On 05/08/2021 21.34, Eduardo Habkost wrote:
Use the SCLP_EVENT_BUS macro instead of manually calling
OBJECT_CHECK.
Signed-off-by: Eduardo Habkost
---
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Halil Pasic
Cc: Christian Borntraeger
Cc: Richard Henderson
Cc:
On 06.08.21 04:46, Eduardo Habkost wrote:
We have a SCLPEventsBus struct type defined, but no QOM type
checkers are declared for the type.
Use OBJECT_DECLARE_SIMPLE_TYPE to declare the struct type and
have a SCLP_EVENT_BUS typecast wrapper defined.
Signed-off-by: Eduardo Habkost
---
Changes v1
marcandre.lur...@redhat.com writes:
> From: Marc-André Lureau
>
> For the sake of completeness, introduce the 'not' condition.
>
> Signed-off-by: Marc-André Lureau
> ---
[...]
> diff --git a/tests/qapi-schema/enum-if-invalid.err
> b/tests/qapi-schema/enum-if-invalid.err
> index b96d94c48a..3b
According to the PoP:
"When the enhanced-DAT facility 1 is not installed, or
when the facility is installed but the multiple-block
control is zero, general register R 2 contains a real
address. When the enhanced-DAT facility 1 is
installed and the multiple-block control is one, gen-
On 05/08/2021 17.27, David Hildenbrand wrote:
For RRBE, SSKE, and ISKE, we're dealing with real addresses, so we have to
convert to an absolute address first.
Signed-off-by: David Hildenbrand
---
target/s390x/tcg/mem_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/s390
Marc-André Lureau writes:
> Hi
>
> On Thu, Aug 5, 2021 at 5:57 PM Markus Armbruster wrote:
>
>> marcandre.lur...@redhat.com writes:
>>
>> > From: Marc-André Lureau
>> >
>> > Signed-off-by: Marc-André Lureau
>> > Reviewed-by: Stefan Hajnoczi
>> > Tested-by: John Snow
>> > Reviewed-by: Markus
On 06.08.21 08:25, Thomas Huth wrote:
On 06/08/2021 08.19, Thomas Huth wrote:
On 05/08/2021 17.27, David Hildenbrand wrote:
The last bit has to be ignored.
Signed-off-by: David Hildenbrand
---
target/s390x/tcg/mem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
在 2021/8/2 下午4:42, Laurent Vivier 写道:
On 02/08/2021 06:50, Jason Wang wrote:
在 2021/7/30 上午3:19, Laurent Vivier 写道:
Add virtio_queue_disable()/virtio_queue_enable() to disable/enable a queue
by setting vring.num to 0 (or num_default).
This is needed to be able to disable a guest driver from t
On 06/08/2021 08.19, Thomas Huth wrote:
On 05/08/2021 17.27, David Hildenbrand wrote:
The last bit has to be ignored.
Signed-off-by: David Hildenbrand
---
target/s390x/tcg/mem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target
I am simulating a device. When an interrupt occurs, another interrupt
comes, and the second interrupt will not be triggered because the
first interrupt has not yet finished.
I want to know whether qemu can detect whether the interrupt has been
executed, will there be a callback here?
Or how can I
On 05/08/2021 17.27, David Hildenbrand wrote:
The last bit has to be ignored.
Signed-off-by: David Hildenbrand
---
target/s390x/tcg/mem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index e0befd0f03.
On Fri, Aug 6, 2021 at 2:08 PM Ruinland Chuan-Tzu Tsa(蔡傳資)
wrote:
>
>
> Hi Bin and Alistair,
>
>
> >> +#if defined(CONFIG_RISCV_CUSTOM)
> >> +static void setup_custom_csr(CPURISCVState *env,
> >> + riscv_custom_csr_operations csr_map_struct[]
> >> +
On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinalnd ChuanTzu Tsai
>
> In this patch we enabled custom CSR logic for Andes AX25 and A25 logic.
> Hence csr_andes.inc.c and andes_cpu_bits.h is added.
>
> Signed-off-by: Dylan Jhong
> ---
> target/riscv/andes_cpu_bits.h
Hi Bin and Alistair,
>> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
> The latest RISC-V core from Andes is AX45 and A45. Should we just
> support the latest one?
Maybe we can have them all ?
AX25 and A25 is still in production, and we still have new clients using these
CPU
When COLO use only one vnet_hdr_support parameter between
COLO network filter(filter-mirror, filter-redirector or
filter-rewriter and colo-compare, packet will not be parsed
correctly. Acquire network driver related to COLO, if it is
nirtio-net, check vnet_hdr_support flag of COLO network filter
an
Hi Bin and Alistair,
>> +#if defined(CONFIG_RISCV_CUSTOM)
>> +static void setup_custom_csr(CPURISCVState *env,
>> + riscv_custom_csr_operations csr_map_struct[]
>> + ) {
>{ should be put to the next line, per QEMU coding convention. Please
On 05/08/2021 17.27, David Hildenbrand wrote:
Let's wrap the address just like for SSKE and ISKE.
Signed-off-by: David Hildenbrand
---
target/s390x/tcg/mem_helper.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem
On 05/08/2021 16.37, David Hildenbrand wrote:
schib->pmcw.chars is 32bit, not 16bit. This fixes the kvm-unit-tests
"css" test, which fails with:
FAIL: Channel Subsystem: measurement block format1: Unaligned MB origin:
Program interrupt: expected(21) == received(0)
Because we end up not in
On 05/08/2021 00.51, Ilya Leoshkevich wrote:
Verify that s390x-specific uc_mcontext.psw.addr is reported correctly
and that signal handling interacts properly with debugging.
Signed-off-by: Ilya Leoshkevich
---
v7: https://lists.nongnu.org/archive/html/qemu-devel/2021-08/msg00463.html
v7 -> v8
On 05/08/2021 14.59, David Hildenbrand wrote:
We not only invalidate the translation of the range 0x0-0x2000, we also
invalidate the translation of the new prefix range and the translation
of the old prefix range -- because real2abs would return different
results for all of these ranges when chan
> When adding RAM_NORESERVE, we forgot to remove the old assertion when
> adding the updated one, most probably when reworking the patches or
> rebasing. We can easily crash QEMU by adding
> -object memory-backend-ram,id=mem0,size=500G,reserve=off
> to the QEMU cmdline:
> qemu-system-x86_64: ..
> We are currently using maxcpus to calculate the omitted sockets
> but using cpus to calculate the omitted cores/threads. This makes
> cmdlines like:
> -smp cpus=8,maxcpus=16
> -smp cpus=8,cores=4,maxcpus=16
> -smp cpus=8,threads=2,maxcpus=16
> work fine but the ones like:
> -smp cpus=8,so
> We have two requirements for a valid SMP configuration:
> the product of "sockets * cores * threads" must represent all the
> possible cpus, i.e., max_cpus, and then must include the initially
> present cpus, i.e., smp_cpus.
>
> So we only need to ensure 1) "sockets * cores * threads == maxcpus"
> Put both sanity-check of the input SMP configuration and sanity-check
> of the output SMP configuration uniformly in the generic parser. Then
> machine_set_smp() will become cleaner, also all the invalid scenarios
> can be tested only by calling the parser.
>
> Signed-off-by: Yanan Wang
> ---
>
> In the real SMP hardware topology world, it's much more likely that
> we have high cores-per-socket counts and few sockets totally. While
> the current preference of sockets over cores in smp parsing results
> in a virtual cpu topology with low cores-per-sockets counts and a
> large number of soc
On 05/08/2021 21.34, Eduardo Habkost wrote:
We have a SCLPEventsBus struct defined, but the struct is not
used at the TypeInfo definition. This works today but will break
silently if anybody adds a new field to SCLPEventsBus.
Set instance_size properly to avoid problems in the future.
Signed-o
On 05/08/2021 21.34, Eduardo Habkost wrote:
Use the SCLP_EVENT_BUS macro instead of manually calling
OBJECT_CHECK.
Signed-off-by: Eduardo Habkost
---
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Halil Pasic
Cc: Christian Borntraeger
Cc: Richard Henderson
Cc: David Hildenbrand
Cc: qemu-s3...@nong
On 06/08/2021 04.46, Eduardo Habkost wrote:
We have a SCLPEventsBus struct type defined, but no QOM type
checkers are declared for the type.
Use OBJECT_DECLARE_SIMPLE_TYPE to declare the struct type and
have a SCLP_EVENT_BUS typecast wrapper defined.
Signed-off-by: Eduardo Habkost
---
Changes
On Fri, Aug 6, 2021 at 2:00 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinalnd ChuanTzu Tsai
>
> Adding Andes AX25 and A25 CPU model into cpu.h and cpu.c without
The latest RISC-V core from Andes is AX45 and A45. Should we just
support the latest one?
> enhanced features (yet).
>
> Signed-off
+Alistair
On Fri, Aug 6, 2021 at 1:58 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinalnd ChuanTzu Tsai
>
> For now we add a custom CSR handling mechanism to handle non-standard CSR read
> or write.
>
> The write_stub() and read_zero() are provided for quick placeholder usage if
> such CSRs' be
We can get NUMA information completely from MachineState::numa_state.
Remove PCMachineState::numa_nodes and PCMachineState::node_mem,
since they are just copied from MachineState::numa_state.
Signed-off-by: Jingqi Liu
---
hw/i386/acpi-build.c | 12 +++-
hw/i386/pc.c | 9
On 8/5/2021 5:26 PM, Igor Mammedov wrote:
On Tue, 3 Aug 2021 14:30:05 +0800
Jingqi Liu wrote:
The NUMA information in PCMachineState is copied from MachineState.
We get this information uniformly from struct NumaState in MachineState.
Is there a another reason behind this patch?
As clean
Hello,
I'm looking for help dealing with a naming conflict when building
QEMU for Windows hosts.
The summary is: I'm trying to replace the ACCEL() macro in
include/qemu/accel.h with an inline function, but the ACCEL name
conflicts with a symbol provided by winuser.h:
In file included from /bui
On 2021/8/6 上午3:01, Richard Henderson wrote:
On 8/4/21 4:53 PM, LIU Zhiwei wrote:
For 32-bit applications run on 64-bit cpu, it may share some code
with other 64-bit applictions. Thus we should distinguish the translated
cache of the share code with a tb flag.
Signed-off-by: LIU Zhiwei
---
We have a SCLPEventsBus struct type defined, but no QOM type
checkers are declared for the type.
Use OBJECT_DECLARE_SIMPLE_TYPE to declare the struct type and
have a SCLP_EVENT_BUS typecast wrapper defined.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* v1 was previously submitted as par
On Thu, Aug 05, 2021 at 03:34:29PM -0400, Eduardo Habkost wrote:
> We have a SCLPEventsBus struct type defined, but no QOM type
> checkers are declared for the type.
>
> Use OBJECT_DECLARE_SIMPLE_TYPE to declare the struct type and
> have a SCLP_EVENT_BUS typecast wrapper defined.
>
> Signed-off-
On Fri, Aug 6, 2021 at 10:39 AM Bin Meng wrote:
>
> On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
> wrote:
> >
> > From: Ruinland ChuanTzu Tsai
> >
> > Adding option `riscv_custom` to configure script, meson.build and
> > meson_options.txt so as to toggle custom CSR and will-be-upstream
On Fri, Aug 6, 2021 at 1:57 AM Ruinland Chuan-Tzu Tsai
wrote:
>
> From: Ruinland ChuanTzu Tsai
>
> Adding option `riscv_custom` to configure script, meson.build and
> meson_options.txt so as to toggle custom CSR and will-be-upstreamed custom
> instructions handling logic.
>
> Signed-off-by: Dylan
The SBSA_GWDT enum value conflicts with the SBSA_GWDT() QOM type
checking helper, preventing us from using a OBJECT_DEFINE* or
DEFINE_INSTANCE_CHECKER macro for the SBSA_GWDT() wrapper.
If I understand the SBSA 6.0 specification correctly, the signal
being connected to IRQ 16 is the WS0 output sig
On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote:
>
> We extend virt machine to emulate ACLINT devices only when "aclint=on"
> parameter is passed along with machine name in QEMU command-line.
>
> Signed-off-by: Anup Patel
> ---
> hw/riscv/virt.c | 113 +++
On Sat, Jul 24, 2021 at 8:24 PM Anup Patel wrote:
>
> We re-factor and break the FDT generation into smaller functions
> so that it is easier to modify FDT generation for different
> configurations of virt machine.
>
> Signed-off-by: Anup Patel
> ---
> hw/riscv/virt.c | 521 +
On Sat, Jul 24, 2021 at 8:27 PM Anup Patel wrote:
>
> The RISC-V ACLINT is more modular and backward compatible with
> original SiFive CLINT so instead of duplicating the original
> SiFive CLINT implementation we upgrade the current SiFive CLINT
> implementation to RISC-V ACLINT implementation.
>
On Sat, Jul 24, 2021 at 8:24 PM Anup Patel wrote:
>
> We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
> implementation so let's first rename the sources.
>
> Signed-off-by: Anup Patel
> ---
> hw/intc/Kconfig| 2 +-
> hw/intc/meson.build
This implements a PCI device for ACPI ERST. This implements the
non-NVRAM "mode" of operation for ERST as it is supported by
Linux and Windows.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 750 +++
hw/acpi/meson.build | 1 +
hw/acpi/t
This change implements the test suite checks for the ERST table.
Signed-off-by: Eric DeVolder
---
tests/qtest/bios-tables-test.c | 43 ++
1 file changed, 43 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 5
This change provides a qtest that locates and then does a simple
interrogation of the ERST feature within the guest.
Signed-off-by: Eric DeVolder
---
tests/qtest/erst-test.c | 167
tests/qtest/meson.build | 2 +
2 files changed, 169 insertions(+
This builds the ACPI ERST table to inform OSPM how to communicate
with the acpi-erst device.
Signed-off-by: Eric DeVolder
---
hw/acpi/erst.c | 239 +
1 file changed, 239 insertions(+)
diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c
index eb4a
This patchset introduces support for the ACPI Error Record
Serialization Table, ERST.
For background and implementation information, please see
docs/specs/acpi_erst.txt, which is patch 2/10.
Suggested-by: Konrad Wilk
Signed-off-by: Eric DeVolder
---
v6: 5aug2021
- Fixed compile warning/error,
Following the guidelines in tests/qtest/bios-tables-test.c, this
is step 6, the re-generated ACPI tables binary blobs.
Signed-off-by: Eric DeVolder
---
tests/data/acpi/microvm/ERST.pcie | Bin 0 -> 912 bytes
tests/data/acpi/pc/DSDT | Bin 6002 -> 6009 bytes
tests/da
Information on the implementation of the ACPI ERST support.
Signed-off-by: Eric DeVolder
---
docs/specs/acpi_erst.txt | 147 +++
1 file changed, 147 insertions(+)
create mode 100644 docs/specs/acpi_erst.txt
diff --git a/docs/specs/acpi_erst.txt b/doc
This change reserves the PCI device_id for the new ACPI ERST
device.
Signed-off-by: Eric DeVolder
---
include/hw/pci/pci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index d0f4266..58101d8 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci
This change introduces the public defintions for ACPI ERST.
Signed-off-by: Eric DeVolder
---
include/hw/acpi/erst.h | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 include/hw/acpi/erst.h
diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h
new file mode 10
Included creation of ITS as part of virt platform GIC
initialization. This Emulated ITS model now co-exists with kvm
ITS and is enabled in absence of kvm irq kernel support in a
platform.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/arm/virt.c | 28 +++
This change exposes ACPI ERST support for x86 guests.
Signed-off-by: Eric DeVolder
---
hw/i386/acpi-build.c | 9 +
hw/i386/acpi-microvm.c | 9 +
include/hw/acpi/erst.h | 5 +
3 files changed, 23 insertions(+)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index a
Updated expected IORT files applicable with latest GICv3
ITS changes.
Full diff of new file disassembly:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180629 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
* Disassembly of tests/data/acpi/virt/IORT
Implemented lpi processing at redistributor to get lpi config info
from lpi configuration table,determine priority,set pending state in
lpi pending table and forward the lpi to cpuif.Added logic to invoke
redistributor lpi processing with translated LPI which set/clear LPI
from ITS device as part o
Added ITS command queue handling for MAPTI,MAPI commands,handled ITS
translation which triggers an LPI via INT command as well as write
to GITS_TRANSLATER register,defined enum to differentiate between ITS
command interrupt trigger and GITS_TRANSLATER based interrupt trigger.
Each of these commands
Following the guidelines in tests/qtest/bios-tables-test.c, this
change adds empty placeholder files per step 1 for the new ERST
table, and excludes resulting changed files in bios-tables-test-allowed-diff.h
per step 2.
Signed-off-by: Eric DeVolder
---
tests/data/acpi/microvm/ERST
Added expected IORT files applicable with latest GICv3
ITS changes.Temporarily differences in these files are
okay.
Signed-off-by: Shashi Mallela
---
tests/data/acpi/virt/IORT | 0
tests/data/acpi/virt/IORT.memhp | 0
tests/data/acpi/virt/IORT.numamem | 0
Defined descriptors for ITS device table,collection table and ITS
command queue entities.Implemented register read/write functions,
extract ITS table parameters and command queue parameters,extended
gicv3 common to capture qemu address space(which host the ITS table
platform memories required for s
Added functionality to trigger ITS command queue processing on
write to CWRITE register and process each command queue entry to
identify the command type and handle commands like MAPD,MAPC,SYNC.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Reviewed-by: Eric Auger
---
hw/intc/arm_gi
Added properties to enable ITS feature and define qemu system
address space memory in gicv3 common,setup distributor and
redistributor registers to indicate LPI support.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
---
hw/intc/arm_gicv3_common.c | 12
hw/intc/ar
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 79 ---
1 file changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index c1629df603..f
Added register definitions relevant to ITS,implemented overall
ITS device framework with stubs for ITS control and translater
regions read/write,extended ITS common to handle mmio init between
existing kvm device and newer qemu device.
Signed-off-by: Shashi Mallela
Reviewed-by: Peter Maydell
Rev
This patchset implements qemu device model for enabling physical
LPI support and ITS functionality in GIC as per GICv3 specification.
Both flat table and 2 level tables are implemented.The ITS commands
for adding/deleting ITS table entries,trigerring LPI interrupts are
implemented.Translated LPI in
This patch enables running generic EGL devices such as Nvidia's in headless
mode. It assumes single device. More work is needed to support multiple devices.
Signed-off-by: Eugene Huang mailto:euge...@nvidia.com>>
---
ui/egl-helpers.c | 41 +
1 file chan
On 8/4/21 4:53 PM, LIU Zhiwei wrote:
Don't overwrite global source register after
https://lists.gnu.org/archive/html/qemu-riscv/2021-07/msg00058.html.
Signed-off-by: LIU Zhiwei
---
target/riscv/translate.c | 46 +++-
1 file changed, 26 insertions(+), 20 del
On 8/4/21 4:53 PM, LIU Zhiwei wrote:
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
+if (ctx->uxl32) {
+return trans_srliw(ctx, a);
+}
return gen_shifti(ctx, a, tcg_gen_shr_tl);
}
First, trans_srliw begins with REQUIRE_64BIT, which *should* fail when RV32 i
On Thu, Aug 05, 2021 at 07:42:35PM +0530, Ani Sinha wrote:
> Also to be noted that there is a stub for acpi_get_i386_pci_host() which
> simply returns NULL. This activates when CONFIG_PC is disabled. It is this
> stub that gets called for mips and hence the check for non-null host is
> needed in ac
commit 58b350280e97 ("hw/arm/bcm2836: Restrict BCM283XInfo
declaration to C source") didn't just move the struct
BCM283XClass definition to bcm2836.c. It also introduced a
typedef (BCM283XClass) and two type checking macros
(BCM283X_CLASS, BCM283X_GET_CLASS).
The typedef and macros duplicate what
On Thu, Aug 5, 2021 at 5:02 PM Eric Blake wrote:
> On Tue, Aug 03, 2021 at 02:29:22PM -0400, John Snow wrote:
> > This serves a few purposes:
> >
> > 1. Protect interfaces when it's not safe to call them (via @require)
> >
> > 2. Add an interface by which an async client can determine if the stat
On Thu, 2021-07-08 at 19:27 +0200, Eric Auger wrote:
> Hi Shashi,
>
> On 7/6/21 11:29 AM, Eric Auger wrote:
> > Hi,
> >
> > On 6/30/21 5:31 PM, Shashi Mallela wrote:
> > > Defined descriptors for ITS device table,collection table and ITS
> > > command queue entities.Implemented register read/writ
On Tue, Aug 03, 2021 at 02:29:22PM -0400, John Snow wrote:
> This serves a few purposes:
>
> 1. Protect interfaces when it's not safe to call them (via @require)
>
> 2. Add an interface by which an async client can determine if the state
> has changed, for the purposes of connection management.
>
translate_insn() implementations fetch instruction bytes piecemeal,
which can cause qemu-user to generate inconsistent translations if
another thread modifies them concurrently [1].
Fix by making pages containing translated instruction non-writable
right before loading instruction bytes from them.
On Thu, 2021-08-05 at 06:59 -1000, Richard Henderson wrote:
> On 8/5/21 12:56 AM, Ilya Leoshkevich wrote:
> > On Wed, 2021-08-04 at 14:30 -1000, Richard Henderson wrote:
> > > I think that the translator_ld*_swap functions should be moved
> > > out of
> > > include/exec/translator.h into accel/tcg/
Dear all,
in my opinion the `type` argument in the kvm ioctl wrappers should be of
type unsigned. Please correct me if I am wrong.
-
Due to the same reason as explained in the comment on the
`irq_set_ioctl` field in `struct KVMState` (accel/kvm/kvm-all.c),
the kvm ioctl wrapper should take `type
On Wed, Aug 04, 2021 at 11:54:43AM +, Ashish Kalra wrote:
> From: Brijesh Singh
>
> AMD SEV migration flow requires that target machine's public Diffie-Hellman
> key (PDH) and certificate chain must be passed before initiating the guest
> migration. User can use QMP 'migrate-set-parameters' t
On Thu, 2021-07-08 at 23:05 +0100, Leif Lindholm wrote:
> On Thu, Jul 08, 2021 at 21:05:02 +0100, Peter Maydell wrote:
> > On Thu, 8 Jul 2021 at 20:40, Leif Lindholm
> > wrote:
> > > I think my summary-summary would be:
> > > - I think we will need to introduce a compatiblity-breaking
> > > change
On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
wrote:
> This patch adds type annotations for aqmp-tui using
> the mypy library.
>
>
Awesome, thanks for taking a swing at this. Looks like it wasn't as bad as
I was fearing.
> Signed-off-by: G S Niteesh Babu
> ---
> python/qemu/aqmp/aqmp_tui.p
On Wed, Jun 23, 2021 at 08:00:14PM +0200, Philippe Mathieu-Daudé wrote:
> Multiple commands have to check the address requested is valid.
check that the
> Extract this code pattern as a new address_in_range() helper, and
> log invalid accesses as guest errors.
>
> Signed-off-by: Philippe Mathieu
Sean, understood with many thanks!
Good luck,
Harry
On Wed, Jul 28, 2021 at 3:01 PM Sean Christopherson wrote:
>
> On Wed, Jul 28, 2021, harry harry wrote:
> > Sean, sorry for the late reply. Thanks for your careful explanations.
> >
> > > For emulation of any instruction/flow that starts with a
On Wed, Jun 23, 2021 at 08:00:13PM +0200, Philippe Mathieu-Daudé wrote:
> We report the card is in an inconsistent state, but don't precise
s/don't/aren't/
> in which state it is. Add this information, as it is useful when
> debugging problems.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
>
We have a SCLPEventsBus struct type defined, but no QOM type
checkers are declared for the type.
Use OBJECT_DECLARE_SIMPLE_TYPE to declare the struct type and
have a SCLP_EVENT_BUS typecast wrapper defined.
Signed-off-by: Eduardo Habkost
---
Cc: Richard Henderson
Cc: David Hildenbrand
Cc: Corn
OBJECT_CHECK(PciHostState, ..., TYPE_PCI_HOST_BRIDGE) is exactly
what the PCI_HOST_BRIDGE macro does. We can just use the macro
instead of using OBJECT_CHECK manually.
Signed-off-by: Eduardo Habkost
---
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: Paolo Bonzini
Cc: Richard Henderson
Cc: Ed
On Thu, 5 Aug 2021 at 15:09, Markus Armbruster wrote:
>
> The following changes since commit cb2f4b8750b7e1c954570d19b104d4fdbeb8739a:
>
> Merge remote-tracking branch
> 'remotes/thuth-gitlab/tags/pull-request-2021-08-03' into staging (2021-08-03
> 19:50:43 +0100)
>
> are available in the Git
On Thu, Aug 05, 2021 at 04:36:03PM +0200, Max Reitz wrote:
> gluster's block-status implementation is basically a copy of that in
> block/file-posix.c, there is only one thing missing, and that is
> aligning trailing data extents to the request alignment (as added by
> commit 9c3db310ff0).
>
> Not
We have a SCLPEventsBus struct defined, but the struct is not
used at the TypeInfo definition. This works today but will break
silently if anybody adds a new field to SCLPEventsBus.
Set instance_size properly to avoid problems in the future.
Signed-off-by: Eduardo Habkost
---
Cc: Cornelia Huck
Use the SCLP_EVENT_BUS macro instead of manually calling
OBJECT_CHECK.
Signed-off-by: Eduardo Habkost
---
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Halil Pasic
Cc: Christian Borntraeger
Cc: Richard Henderson
Cc: David Hildenbrand
Cc: qemu-s3...@nongnu.org
Cc: qemu-devel@nongnu.org
---
hw/s390x
Those macros never worked and never will, because the
SBSA_GWDTClass type never existed.
Signed-off-by: Eduardo Habkost
---
Cc: qemu-devel@nongnu.org
Cc: Peter Maydell
Cc: Shashi Mallela
---
include/hw/watchdog/sbsa_gwdt.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/hw/watch
The macro never worked and never will, because the
AcpiGedX86State type never existed.
Signed-off-by: Eduardo Habkost
---
Cc: "Michael S. Tsirkin"
Cc: Igor Mammedov
Cc: qemu-devel@nongnu.org
---
include/hw/acpi/generic_event_device.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include
This series removes some broken OBJECT_CHECK macros and fix cases
where OBJECT_CHECK is being used directly in the code.
Eduardo Habkost (6):
acpi: Delete broken ACPI_GED_X86 macro
sbsa_gwdt: Delete broken SBSA_*CLASS macros
s390-sclp-events-bus: Set instance_size
s390-sclp-events-bus: Use
This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
This commit was misguided and broke using --disable-pie on any distro
that enables PIE by default in their compiler driver, including Debian
and its derivatives. Whilst -no-pie is not a linker flag, it is a
compiler driver fla
On Wed, Aug 04, 2021 at 12:31:05PM +0400, marcandre.lur...@redhat.com wrote:
> From: Marc-André Lureau
>
> Change the 'if' condition strings to be C-agnostic. It will accept
> '[A-Z][A-Z0-9_]*' identifiers. This allows to express configuration
This allows the expression of configuration
> condi
On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
wrote:
> Add an entry point for aqmp-tui. This will allow it to be run from
> the command line using "aqmp-tui localhost:1234"
> More options available in the TUI can be found using "aqmp-tui -h"
>
> Signed-off-by: G S Niteesh Babu
>
Reviewed-by:
This partially reverts commit bbd2d5a8120771ec59b86a80a1f51884e0a26e53.
This commit was misguided and broke using --disable-pie on any distro
that enables PIE by default in their compiler driver, including Debian
and its derivatives. Whilst -no-pie is not a linker flag, it is a
compiler driver fla
On Fri, Jul 30, 2021 at 4:19 PM G S Niteesh Babu
wrote:
> Added a draft of AQMP TUI.
>
> Implements the follwing basic features:
> 1) Command transmission/reception.
> 2) Shows events asynchronously.
> 3) Shows server status in the bottom status bar.
>
> Also added necessary pylint, mypy configur
On 8/4/21 4:53 PM, LIU Zhiwei wrote:
+static bool gen_arith_simm_tl(DisasContext *ctx, arg_i *a,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+TCGv dest = gpr_dst(ctx, a->rd);
+TCGv src1 = gpr_src_s(ctx, a->rs1);
+TCGv src2 = tcg_constant_tl(a->imm);
+
+(*func
On 8/4/21 4:53 PM, LIU Zhiwei wrote:
Get the LSB 32 bits and zero-extend as the base address.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/
On Thu, Aug 05, 2021 at 12:36:11PM -0400, Eduardo Habkost wrote:
> On Wed, Aug 04, 2021 at 08:26:10PM -0400, John Snow wrote:
> > On Wed, Aug 4, 2021 at 5:00 PM Eduardo Habkost wrote:
> >
> > > On Wed, Aug 04, 2021 at 09:42:24PM +0100, Peter Maydell wrote:
> > > > Is there a sensible default-role
1 - 100 of 272 matches
Mail list logo
