[PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling

TCG_TARGET_HAS_MEMORY_BSWAP is already unset for this backend, which means that MO_BSWAP be handled by the middle-end and will never be seen by the backend. Thus the indexes used with qemu_{ld,st}_helpers will always be zero. Tidy the comments and asserts in tcg_out_qemu_{ld,st}_direct. It is not

[PATCH v3 28/29] tcg/aarch64: Unset TCG_TARGET_HAS_MEMORY_BSWAP

The memory bswap support in the aarch64 backend merely dates from a time when it was required. There is nothing special about the backend support that could not have been provided by the middle-end even prior to the introduction of the bswap flags. Reviewed-by: Peter Maydell Signed-off-by: Richa

Re: [RFC PATCH] tcg/plugins: enable by default for TCG builds

On 25/06/2021 13.27, Alex Bennée wrote: Aside from a minor bloat to file size the ability to have TCG plugins has no real impact on performance unless a plugin is actively loaded. Even then the libempty.so plugin shows only a minor degradation in performance caused by the extra book keeping the T

[PATCH v3 23/29] target/arm: Improve REVSH

The new bswap flags can implement the semantics exactly. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/translate.c b/target/arm/transla

[PATCH v3 27/29] tcg/arm: Unset TCG_TARGET_HAS_MEMORY_BSWAP

Now that the middle-end can replicate the same tricks as tcg/arm used for optimizing bswap for signed loads and for stores, do not pretend to have these memory ops in the backend. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-targ

[PATCH v3 25/29] target/sh4: Improve swap.b translation

Remove TCG_BSWAP_IZ and the preceding zero-extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/sh4/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 147219759b..4dcfff81f6 100644

[PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_*

We can perform any required sign-extension via TCG_BSWAP_OS. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 24 ++-- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op

[PATCH v3 22/29] target/arm: Improve vector REV

We can eliminate the requirement for a zero-extended output, because the following store will ignore any garbage high bits. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 ++ 1 file changed, 2 insertions(+)

[PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_*

By removing TCG_BSWAP_IZ we indicate that the input is not zero-extended, and thus can remove an explicit extend. By removing TCG_BSWAP_OZ, we allow the implementation to leave high bits set, which will be ignored by the store. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg

[PATCH v3 21/29] target/arm: Improve REV32

For the sf version, we are performing two 32-bit bswaps in either half of the register. This is equivalent to performing one 64-bit bswap followed by a rotate. For the non-sf version, we can remove TCG_BSWAP_IZ and the preceding zero-extension. Reviewed-by: Peter Maydell Reviewed-by: Philippe M

[PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64

Implement the new semantics in the fallback expansion. Change all callers to supply the flags that keep the semantics unchanged locally. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h| 8 +-- target/arm/tra

[PATCH v3 24/29] target/i386: Improve bswap translation

Use a break instead of an ifdefed else. There's no need to move the values through s->T0. Remove TCG_BSWAP_IZ and the preceding zero-extension. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 14 -- 1 file changed, 4 insertions(+), 10 de

[PATCH v3 26/29] target/mips: Fix gen_mxu_s32ldd_s32lddr

There were two bugs here: (1) the required endianness was not present in the MemOp, and (2) we were not providing a zero-extended input to the bswap as semantics required. The best fix is to fold the bswap into the memory operation, producing the desired result directly. Acked-by: Philippe Mathie

[PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32

Merge tcg_out_bswap32 and tcg_out_bswap32s. Use the flags in the internal uses for loads and stores. For mips32r2 bswap32 with zero-extension, standardize on WSBH+ROTR+DEXT. This is the same number of insns as the previous DSBH+DSHD+DSRL but fits in better with the flags check. Reviewed-by: Phil

[PATCH v3 04/29] tcg/aarch64: Support bswap flags

Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 12 1 file changed, 12 insertions(+) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 8619e54fca..72aa7e0e74 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/

[PATCH v3 17/29] tcg: Handle new bswap flags during optimize

Notice when the input is known to be zero-extended and force the TCG_BSWAP_IZ flag on. Honor the TCG_BSWAP_OS bit during constant folding. Propagate the input to the output mask. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/optimize.c | 56 ++

[PATCH v3 09/29] tcg/ppc: Split out tcg_out_bswap32

Cc: qemu-...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 38 ++ 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index ad46ce32ca..28b8

[PATCH v3 13/29] tcg/s390: Support bswap flags

For INDEX_op_bswap16_i64, use 64-bit instructions so that we can easily provide the extension to 64-bits. Drop the special case, previously used, where the input is already zero-extended -- the minor code size savings is not worth the complication. Cc: qemu-s3...@nongnu.org Signed-off-by: Richard

[PATCH v3 16/29] tcg/tci: Support bswap flags

The existing interpreter zero-extends, ignoring high bits. Simply add a separate sign-extension opcode if required. Ensure that the interpreter supports ext16s when bswap16 is enabled. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c| 3 ++- tc

[PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16

Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags in the internal uses for loads and stores. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 63 +++ 1 file changed, 30 insertions(+), 33 deletions(-

[PATCH v3 11/29] tcg/ppc: Support bswap flags

For INDEX_op_bswap32_i32, pass 0 for flags: input not zero-extended, output does not need extension within the host 64-bit register. Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 22 -- 1 file changed, 16 insertions(+), 6 deletions(-)

[PATCH v3 07/29] tcg/ppc: Split out tcg_out_sari{32,64}

We will shortly require sari in other context; split out both for cleanliness sake. Cc: qemu-...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/tcg/ppc/tcg

[PATCH v3 08/29] tcg/ppc: Split out tcg_out_bswap16

With the use of a suitable temporary, we can use the same algorithm when src overlaps dst. The result is the same number of instructions either way. Cc: qemu-...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 34 +++

[PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions

Cc: qemu-...@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 34 ++ 1 file changed, 34 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 33f0139519..e0f4665213 100644 --- a/tcg/ppc/tcg-target.c.inc +++

[PATCH v3 02/29] tcg/i386: Support bswap flags

Retain the current rorw bswap16 expansion for the zero-in/zero-out case. Otherwise, perform a wider bswap plus a right-shift or extend. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 20 +++- 1 file changed, 19 insertions(+), 1 deleti

[PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64

Cc: qemu-...@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 64 +--- 1 file changed, 34 insertions(+), 30 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 28b8671cba..da

[PATCH v3 05/29] tcg/arm: Support bswap flags

Combine the three bswap16 routines, and differentiate via the flags. Use the correct flags combination from the load/store routines, and pass along the constant parameter from tcg_out_op. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 101

[PATCH v3 00/29] tcg: bswap improvements

Changes for v3: * Comment improvments for mips (phil). * Patch 3 is new, rearranging some tcg/aarch64 helpers. Changes for v2: * Merge tcg_out_rev{16,32,64}, which perhaps solves the issue of mnemonics vs actual opcodes, and also preps for Phil suggestion of adding additional tcg opc

[PATCH v3 06/29] tcg/ppc: Split out tcg_out_ext{8,16,32}s

We will shortly require these in other context; make the expansion as clear as possible. Cc: qemu-...@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 31 +-- 1 file changed, 21

[PATCH v3 01/29] tcg: Add flags argument to bswap opcodes

This will eventually simplify front-end usage, and will allow backends to unset TCG_TARGET_HAS_MEMORY_BSWAP without loss of optimization. The argument is added during expansion, not currently exposed to the front end translators. The backends currently only support a flags value of either TCG_BSW

[PATCH v3 03/29] tcg/aarch64: Merge tcg_out_rev{16,32,64}

Pass in the input and output size. We currently use 3 of the 5 possible combinations; the others may be used by new tcg opcodes. Cc: Peter Maydell Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 42 ++-- 1 file changed, 16 insertions(+), 26 d

Re: [PATCH 0/5] tcg: Issue memory barriers for guest memory model

Ping. A local rebase seems to apply clean. r~ On 3/16/21 3:07 PM, Richard Henderson wrote: This is intending to fix the current aarch64 host failure for s390x guest cdrom-test. This is caused by the io thread issuing memory barriers that are supposed to be matched by the vcpu, but are elided

Re: [PATCH v3 2/3] target/ppc: change ppc_hash32_xlate to use mmu_idx

On 6/24/21 1:21 PM, Bruno Larsen (billionai) wrote: -static int ppc_hash32_pte_prot(PowerPCCPU *cpu, +static int ppc_hash32_pte_prot(PowerPCCPU *cpu, int mmu_idx, target_ulong sr, ppc_hash_pte32_t pte) { -CPUPPCState *env = &cpu->env; unsigned pp, key;

Re: [PATCH v3 3/3] target/ppc: changed ppc_hash64_xlate to use mmu_idx

On 6/24/21 1:21 PM, Bruno Larsen (billionai) wrote: /* Check Basic Storage Protection */ -static int ppc_hash64_pte_prot(PowerPCCPU *cpu, +static int ppc_hash64_pte_prot(PowerPCCPU *cpu, int mmu_idx, ppc_slb_t *slb, ppc_hash_pte64_t pte) { -CPUPPCState *en

Re: [PATCH v2 1/1] tcg: Use correct trap number for page faults on *BSD systems

On 6/24/21 9:57 PM, Warner Losh wrote: The trap number for a page fault on BSD systems is T_PAGEFLT not 0xe. 0xe is used by Linux and represents the intel hardware trap vector. The BSD kernels, however, translate this to T_PAGEFLT in their Xpage, Xtrap0e, Xtrap14, etc fault handlers. This is true

Re: [PATCH v4 00/16] tcg/s390x: host vector support

Patchew URL: https://patchew.org/QEMU/20210626050307.2408505-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20210626050307.2408505-1-richard.hender...@linaro.org Subject: [PATCH v4 00/16

[PATCH v4 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-se

[PATCH v4 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec

This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4a8d9f2f

[PATCH v4 08/16] tcg/s390x: Implement minimal vector operations

Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 - 1 file changed, 150 insertions(+), 4 deletions(-) diff --git a

[PATCH v4 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 8dce6af5af..275f980cee 100644 --- a/tcg/s390x/tc

[PATCH v4 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +- tcg/s390x/tcg-target.c.inc | 34 +- 3 files changed, 39 insertions(+),

[PATCH v4 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index a3d4b5111f..cb14a011c7 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/

[PATCH v4 13/16] tcg: Expand usadd/ussub with umin/umax

For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37

[PATCH v4 04/16] tcg/s390x: Add host vector framework

Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h |

[PATCH v4 11/16] tcg/s390x: Implement vector shift operations

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +- 3 files changed, 99 insertions(+), 7 deletions(-) diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x

[PATCH v4 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 + 1 file changed, 110 insertions(+), 12 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 18233c628d..b6ea129e14 100644 --- a/tcg/s390x/tcg-target.c.in

[PATCH v4 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec

The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson --- tcg/s390x/

[PATCH v4 07/16] tcg/s390x: Implement tcg_out_dup*_vec

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 - 1 file changed, 119 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index c4e12a57f3..76216eb5bc 100644 --- a/tcg/s390x/tcg-target.c.inc

[PATCH v4 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg

They are rightly values in the same enumeration. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e12

[PATCH v4 06/16] tcg/s390x: Implement tcg_out_mov for vector types

Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++--- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b6ea129e14..c4e12a57f3 100644 --- a/tcg/s390x/tcg-target.c.inc

[PATCH v4 01/16] tcg/s390x: Rename from tcg/s390

This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 => s390x}/tcg-target-con-set.h | 0 tcg/{s390 => s390x}/tcg-target-con-str.h | 0 tcg/{s390 => s390

[PATCH v4 00/16] tcg/s390x: host vector support

Changes for v4: * Fix bug in RXB (david). r~ Richard Henderson (16): tcg/s390x: Rename from tcg/s390 tcg/s390x: Change FACILITY representation tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg tcg/s390x: Add host vector framework tcg/s390x: Implement tcg_out_ld/st for vect

[PATCH v4 02/16] tcg/s390x: Change FACILITY representation

We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Change name to HAVE_FACILITY (david) --- t

[Bug 1437970] Re: qemu-system-x86_64 - two mouse pointers & fast scrolling problem

[Expired for QEMU because there has been no activity for 60 days.] ** Changed in: qemu Status: Incomplete => Expired -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1437970 Title: qemu-system

Re: [RFC PATCH 0/9] hw/sd: Allow card size not power of 2 again

On 210624 1012, Philippe Mathieu-Daudé wrote: > On 6/24/21 4:50 AM, Alexander Bulekov wrote: > > On 210623 2000, Philippe Mathieu-Daudé wrote: > >> Hi Ubi-Wan Kenubi and Tom, > >> > >> In commit a9bcedd (SD card size has to be power of 2) we decided > >> to restrict SD card size to avoid security p

Re: [PATCH 0/5] tcg: Add 32-bit vector operations

On 6/24/21 3:50 AM, LIU Zhiwei wrote: This patch set is split from RISC-V Packed extension where needs some i32 vector operations, accorind to Richard Henderson's suggestion. The original implementation is on https://www.mail-archive.com/qemu-devel@nongnu.org/msg814538.html. LIU Zhiwei (5):

Re: [RFC PATCH 06/10] hw/sd: Add sd_cmd_unimplemented() handler

On Sat, Jun 26, 2021 at 1:17 AM Philippe Mathieu-Daudé wrote: > > On 6/25/21 3:49 PM, Bin Meng wrote: > > On Thu, Jun 24, 2021 at 10:28 PM Philippe Mathieu-Daudé > > wrote: > >> > >> Signed-off-by: Philippe Mathieu-Daudé > >> --- > >> hw/sd/sd.c | 21 - > >> 1 file changed,

Re: Qemu on Haiku

On Fri, Jun 25, 2021 at 8:45 PM Richard Zak wrote: > Hello and thanks for the detailed response! I wasn't aware that a Linux > host could compile for Haiku as a target, that's interesting. > > Seems like the big tasks are: > 1) Haiku VM for continuous integration. Is this hosted in Amazon or othe

Re: Qemu on Haiku

Hello and thanks for the detailed response! I wasn't aware that a Linux host could compile for Haiku as a target, that's interesting. Seems like the big tasks are: 1) Haiku VM for continuous integration. Is this hosted in Amazon or other cloud infrastructure? 2) Supporting aspects of the qemu code

Re: [PATCH 1/1] target/arm: Check NaN mode before silencing NaN

On 6/25/21 4:02 PM, Joe Komlodi wrote: If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will assert due to fpst->default_nan_mode being set. To avoid this, we check to see what NaN mode we're running

Re: Guidance on emulating "sparse" address spaces

On 6/23/21 5:53 PM, Jason Thorpe wrote: Thanks for the pointer! Yes, it seems like that might be similar to what I need... create new address spaces (rather than using the "system" address space) for the PCI memory and I/O regions (I need to do this for PCI configuration space, too, FWIW...),

Re: [PATCH] target/s390x: Fix CC set by CONVERT TO FIXED/LOGICAL

On 6/23/21 7:50 AM, Ulrich Weigand wrote: @@ -506,6 +534,7 @@ uint64_t HELPER(cgeb)(CPUS390XState *env, uint64_t v2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); int64_t ret = float32_to_int64(v2, &env->fpu_status); +env->cc_op = set_cc_

[PATCH v1 QEMU CXL modifications for openspdm 1/1] pcie/spdm: PCIe CMA implementation

From: hchkuo The Data Object Exchange implementation of Component Measurement and Authentication (CMA). This patch is basically based on Openspdm: https://github.com/jyao1/openspdm.git. Openspdm is an emulator composed of an SPDM requester and an SPDM responder. The requester and responder commu

[PATCH v1 QEMU CXL modifications for openspdm 0/1] Testing PCIe DOE in QEMU CXL/PCIe Device using openspdm

This patch series provides an implementation of the the Data Object Exchange (DOE) for Component Measurement and Authentication (CMA) of the Security Protocol and Data Model (SPDM). This patch is based on [1] [PATCH v1 openspdm on QEMU CXL/PCIe Device 0/2] Testing PCIe DOE in QEMU CXL/PCIe Devi

[PATCH v1 openspdm on QEMU CXL/PCIe Device 2/2] requester: Modified for QEMU emulation

From: hchkuo The requester should be used as a PCIe app to access the SPDM object in the PCEe device. Signed-off-by: Chris Browy --- Include/IndustryStandard/PciDoeBinding.h| 27 +++ SpdmEmu/SpdmEmuCommon/SpdmEmu.c | 85 ++ SpdmEmu/SpdmEmuCommon/SpdmEm

[PATCH v1 openspdm on QEMU CXL/PCIe Device 1/2] build: gcc to CC in GNUMakefile

From: hchkuo Modified gcc to CC in GNUMakefile, so that we can specify the gcc version Signed-off-by: Chris Browy --- GNUmakefile.Flags | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GNUmakefile.Flags b/GNUmakefile.Flags index 3586284..33baceb 100644 --- a/GNUmakefile.

Re: [PATCH v5 13/14] target/hexagon: import additional tests

On Sat, Jun 19, 2021 at 4:49 AM Alessandro Di Federico via < qemu-devel@nongnu.org> wrote: > From: Niccolò Izzo > > Signed-off-by: Alessandro Di Federico > Signed-off-by: Niccolò Izzo > --- > > diff --git a/tests/tcg/hexagon/crt.S b/tests/tcg/hexagon/crt.S > new file mode 100644 > index 0

[PATCH v1 openspdm on QEMU CXL/PCIe Device 0/2] Testing PCIe DOE in QEMU CXL/PCIe Device using openspdm

This patch series provides an implementation of the the Data Object Exchange (DOE) for Component Measurement and Authentication (CMA) of the Security Protocol and Data Model (SPDM). This patch is based on [1] Openspdm: https://github.com/jyao1/openspdm.git Openspdm is an emulator composed of an

[PATCH 1/1] target/arm: Check NaN mode before silencing NaN

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will assert due to fpst->default_nan_mode being set. To avoid this, we check to see what NaN mode we're running in before we call floatxx_silence_nan().

[PATCH 0/1] target/arm: Check NaN mode before silencing NaN

Hi all, This fixes an assertion that occurs when executing FRSQRTE, FRECPE, or FRECPX on a signaling NaN when the CPU has default NaN mode enabled. When attempting to silence the NaN, we hit an assertion that ensures that the CPU FPU status does not have default_nan_mode set. To avoid this, we c

Re: [PATCH v5 12/14] target/hexagon: remove unused macros and functions

Don't do this. Keeping these around makes it easy to fall back to the helper implementations for debugging. Also, some of them are needed for future HVX support. Thanks, Taylor On Sat, Jun 19, 2021 at 4:48 AM Alessandro Di Federico via < qemu-devel@nongnu.org> wrote: > From: Paolo Montesel >

RE: [PATCH v5 11/14] target/hexagon: call idef-parser functions

> -Original Message- > From: Alessandro Di Federico > Sent: Saturday, June 19, 2021 3:37 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; bab...@rev.ng; ni...@rev.ng; phi...@redhat.com; > richard.hender...@linaro.org; Alessandro Di Federico > Subject: [PATCH v5 11/1

[PATCH v3] Add basic power management to raspi.

This is just enough to make reboot and poweroff work. Works for linux, u-boot, and the arm trusted firmware. Not tested, but should work for plan9, and bare-metal/hobby OSes, since they seem to generally do what linux does for reset. The watchdog timer functionality is not yet implemented. Resolv

Re: [PATCH v4 05/22] tests/docker: remove FEATURES env var from templates

On Wed, Jun 23, 2021 at 11:23 AM Daniel P. Berrangé wrote: > > In preparation for switching to auto-generated dockerfiles, remove the > FEATURES env variable. The equivalent functionality can be achieved in > most cases by just looking for existance of a binary. s/existance/existence/ > > The ca

Re: [PATCH v4 03/22] tests/docker: use project specific container registries

On Wed, Jun 23, 2021 at 11:23 AM Daniel P. Berrangé wrote: > > Since Docker Hub has started to enforce pull rate limits on clients, it > is preferrable to use project specific container registries where they s/preferrable/preferable/ > are available. Fedora and OpenSUSE projects provide registri

Re: [PATCH v4 02/22] tests/docker: don't use BUILDKIT in GitLab either

On Wed, Jun 23, 2021 at 11:23 AM Daniel P. Berrangé wrote: > > Using BUILDKIT breaks with certain container registries such as CentOS, > with docker build reporting an error such as > > failed to solve with frontend dockerfile.v0: > failed to build LLB: failed to load cache key: > unexpected

Re: [PATCH 08/11] python: add 'make check-venv' invocation

On 6/25/21 3:01 PM, Willian Rampazzo wrote: On Fri, Jun 25, 2021 at 3:38 PM John Snow wrote: On 6/25/21 2:36 PM, Willian Rampazzo wrote: Maybe, it may confuse people using `make check-venv` under `tests`. Anyway, I'm not opposed to it. Reviewed-by: Willian Rampazzo I have to admit there's

Re: [PATCH 08/11] python: add 'make check-venv' invocation

On Fri, Jun 25, 2021 at 3:38 PM John Snow wrote: > > On 6/25/21 2:36 PM, Willian Rampazzo wrote: > > Maybe, it may confuse people using `make check-venv` under `tests`. > > Anyway, I'm not opposed to it. > > > > Reviewed-by: Willian Rampazzo > > I have to admit there's much about Python packaging

Re: [PATCH v2 00/11] hw/nvme: reimplement all multi-aio commands with custom aiocbs

On Thu, Jun 17, 2021 at 09:06:46PM +0200, Klaus Jensen wrote: > From: Klaus Jensen > > This series reimplements flush, dsm, copy, zone reset and format nvm to > allow cancellation. I posted an RFC back in March ("hw/block/nvme: > convert ad-hoc aio tracking to aiocb") and I've applied some feedba

Re: [PATCH 11/11] python: remove auto-generated pyproject.toml file

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > For reasons that at-present escape me, pipenv insists on creating a stub > pyproject.toml file. This file is a nuisance, because its mere presence > changes the behavior of various tools. > > For instance, this stub file will cause "pip install

Re: [PATCH 08/11] python: add 'make check-venv' invocation

On 6/25/21 2:36 PM, Willian Rampazzo wrote: Maybe, it may confuse people using `make check-venv` under `tests`. Anyway, I'm not opposed to it. Reviewed-by: Willian Rampazzo I have to admit there's much about Python packaging that is confusing :) Can you elaborate on your point for me, though?

Re: [PULL 0/7] misc fixes (docs, plugins, tests)

On Fri, 25 Jun 2021 at 10:14, Alex Bennée wrote: > > A few miscellaneous fixes > > - tweak tcg/kvm based GIC tests > - add header to MTTCG docs > - cleanup checkpatch handling > - GitLab feature and bug request templates >

Re: [PATCH 10/11] python: Update help text on 'make clean', 'make distclean'

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > Just for visual parity with everything else. > > Signed-off-by: John Snow > --- > python/Makefile | 11 +++ > 1 file changed, 7 insertions(+), 4 deletions(-) > Reviewed-by: Willian Rampazzo

Re: [PATCH 09/11] python: Update help text on 'make check', 'make develop'

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > Update for visual parity with the other targets. > > Signed-off-by: John Snow > --- > python/Makefile | 10 +++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > Reviewed-by: Willian Rampazzo

Re: [PATCH 08/11] python: add 'make check-venv' invocation

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > This is a *third* way to run the Python tests. Unlike the first two > (check-pipenv, check-tox), this version does not require any specific > interpreter version -- making it a lot easier to tell people to run it > as a quick smoketest prior to

Re: [PATCH 05/11] python: Add no-install usage instructions

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > It's not encouraged, but it's legitimate to want to know how to do. > > Signed-off-by: John Snow > --- > python/README.rst | 28 > 1 file changed, 28 insertions(+) > Reviewed-by: Willian Rampazzo

Re: [PATCH 07/11] python: update help text for check-tox

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > Move it up near the check-pipenv help text, and update it to suggest parity. > > (At the time I first added it, I wasn't sure if I would be keeping it, > but I've come to appreciate it as it has actually helped uncover bugs I > would not have n

Re: [PATCH 04/11] python: README.rst touchups

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > Clarifying a few points; removing the reference to 'setuptools' because > it referenced anywhere else in this document and doesn't really provide > any useful information to a Python newcomer. > > Adjusting the language elsewhere to be less amb

Re: [PATCH 06/11] python: rename 'venv-check' target to 'check-pipenv'

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > Well, Cleber was right, this is a better name. > > In preparation for adding a different kind of virtual environment check > (One that simply uses whichever version of Python you happen to have), > rename this test 'check-pipenv' so that it mat

Re: [PATCH 03/11] python: Re-lock pipenv at *oldest* supported versions

On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: > > tox is already testing the most recent versions. Let's use pipenv to > test the oldest versions we claim to support. This matches the stylistic > choice to have pipenv always test our oldest supported Python version, 3.6. > > The effect of this

[PATCH 10/10] python: Add iotest linters to test suite

As a convenience, since iotests is an extremely prominent user of the qemu.qmp and qemu.machine packages and already implements a linting regime, run those tests as well so that it's very hard to miss regressions caused by changes to the python library. Signed-off-by: John Snow --- python/tests/

Re: [PATCH 04/11] python: README.rst touchups

On 6/25/21 2:23 PM, Willian Rampazzo wrote: On Fri, Jun 25, 2021 at 12:46 PM John Snow wrote: Clarifying a few points; removing the reference to 'setuptools' because it referenced anywhere else in this document and doesn't really provide ^ isn't Noticed the typo when adding your RB. a

[PATCH 02/10] iotests/297: Add get_files() function

Split out file discovery into its own method to begin separating out the "environment setup" and "test execution" phases. Signed-off-by: John Snow --- tests/qemu-iotests/297 | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tests/qemu-iotests/297 b/tests/qemu-iotest

[PATCH 09/10] iotests/linters: Add entry point for Python CI linters

Add a main() function to linters.py so that the Python CI infrastructure has something it can run. Now, linters.py represents an invocation of the linting scripts that more resembles a "normal" execution of pylint/mypy, like you'd expect to use if 'qemu' was a bona-fide package you obtained from P

[PATCH 07/10] iotests/297: return error code from run_linters()

This turns run_linters() into a bit of a hybrid test; returning non-zero on failed execution while also printing diffable information. This is done for the benefit of the avocado simple test runner, which will soon be attempting to execute this test from a different environment. (Note: universal_n

[PATCH 08/10] iotests/297: split linters.py off from 297

Split the linter execution itself out from 297, leaving just environment setup in 297. This is done so that non-iotest code can invoke the linters without needing to worry about imports of unpackaged iotest code. Eventually, it should be possible to replace linters.py with mypy.ini and pylintrc fi

[PATCH 05/10] iotests/297: Separate environment setup from test execution

Move environment setup into main(), leaving pure test execution behind in run_linters(). Signed-off-by: John Snow --- tests/qemu-iotests/297 | 36 +--- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/tests/qemu-iotests/297 b/tests/qemu-iotests/297

[PATCH 01/10] iotests/297: modify is_python_file to work from any CWD

Add a directory argument to is_python_file to allow it to work correctly no matter what CWD we happen to run it from. This is done in anticipation of running the iotests from another directory (./python/). Signed-off-by: John Snow --- tests/qemu-iotests/297 | 8 +--- 1 file changed, 5 insert

[PATCH 00/10] python/iotests: Run iotest linters during Python CI

Based-on: <20210625154540.783306-1-js...@redhat.com> GitLab: https://gitlab.com/jsnow/qemu/-/commits/python-package-iotest CI: https://gitlab.com/jsnow/qemu/-/pipelines/327413868 Since iotests are such a heavy and prominent user of the Python qemu.qmp and qemu.machine packages, it would be conveni

[PATCH 03/10] iotests/297: Don't rely on distro-specific linter binaries

'pylint-3' is another Fedora-ism. Use "python3 -m pylint" or "python3 -m mypy" to access these scripts instead. This style of invocation will prefer the "correct" tool when run in a virtual environment. Note that we still check for "pylint-3" before the test begins -- this check is now "overly str

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