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Title:
Solaris on
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Windows 10
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attach-inte
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Title:
USB keyboar
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input-linux
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SBSA ACS te
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qemu-system
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Title:
qemu someti
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aarch64/tcg
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NVME pass t
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QEMU e500 k
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CALL FWORD
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suspend/res
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go build fa
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qemu-user i
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Title:
No ACPI-tab
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Title:
qemu-system
This fixes the build with --enable-tcg-interpreter:
clang -Ilibqemu-arm-softmmu.fa.p -I. -I.. -Itarget/arm -I../target/arm
-I../dtc/libfdt -I../capstone/include/capstone -Iqapi -Itrace -Iui -Iui/shader
-I/usr/include/pixman-1 -I/usr/include/glib-2.0
-I/usr/lib/x86_64-linux-gnu/glib-2.0/includ
On Sun, Jan 10, 2021 at 02:13:48AM +0100, BALATON Zoltan wrote:
> On Sun, 10 Jan 2021, Roman Bolshakov wrote:
> > On Sat, Jan 09, 2021 at 12:13:36AM +0100, BALATON Zoltan wrote:
> > > On Sat, 9 Jan 2021, Roman Bolshakov wrote:
> > > > On Fri, Jan 08, 2021 at 03:00:07PM +, Peter Maydell wrote:
>
On Sat, Jan 09, 2021 at 11:42:18AM +, Peter Maydell wrote:
> On Sat, 9 Jan 2021 at 05:49, Roman Bolshakov wrote:
> >
> > On Fri, Dec 18, 2020 at 06:13:47PM -0800, Hill Ma wrote:
> > > This prevents illegal instruction on cpus do not support xgetbv.
> > >
> > > Buglink: https://bugs.launchpad.n
Hi Philippe,
On Sun, Jan 10, 2021 at 7:53 AM Philippe Mathieu-Daudé wrote:
>
> On 1/9/21 1:35 PM, Bin Meng wrote:
> > From: Bin Meng
> >
> > Usually the approach is that the device on the other end of the line
> > is going to reset its state anyway, so there's no need to actively
> > signal an i
On Sun, 10 Jan 2021, Roman Bolshakov wrote:
On Sat, Jan 09, 2021 at 12:13:36AM +0100, BALATON Zoltan wrote:
On Sat, 9 Jan 2021, Roman Bolshakov wrote:
On Fri, Jan 08, 2021 at 03:00:07PM +, Peter Maydell wrote:
On Fri, 8 Jan 2021 at 13:50, Peter Maydell wrote:
On Sat, 2 Jan 2021 at 15:14
On Sun, 10 Jan 2021, Philippe Mathieu-Daudé wrote:
Hi Zoltan,
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
Currently the ISA devices that are part of the VIA south bridge,
superio chip are wired up by board code. Move creation of these ISA
devices to the VIA ISA bridge model so that board code does
On Sat, Jan 09, 2021 at 01:25:44PM +0100, Christian Schoenebeck via wrote:
> On Samstag, 9. Januar 2021 00:13:36 CET BALATON Zoltan wrote:
> > On Sat, 9 Jan 2021, Roman Bolshakov wrote:
> > > On Fri, Jan 08, 2021 at 03:00:07PM +, Peter Maydell wrote:
> > >> On Fri, 8 Jan 2021 at 13:50, Peter Ma
Hi Zoltan,
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> Currently the ISA devices that are part of the VIA south bridge,
> superio chip are wired up by board code. Move creation of these ISA
> devices to the VIA ISA bridge model so that board code does not need
> to access ISA bus. This also allows
On Sat, Jan 09, 2021 at 12:13:36AM +0100, BALATON Zoltan wrote:
> On Sat, 9 Jan 2021, Roman Bolshakov wrote:
> > On Fri, Jan 08, 2021 at 03:00:07PM +, Peter Maydell wrote:
> > > On Fri, 8 Jan 2021 at 13:50, Peter Maydell
> > > wrote:
> > > >
> > > > On Sat, 2 Jan 2021 at 15:14, Roman Bolshak
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> The superio memory region holds the io space index/data registers used
> to access the superio config registers that are implemented in struct
> SuperIOConfig. To keep these related things together move the memory
> region to SuperIOConfig and rename it ac
When decodetree.py was added in commit 568ae7efae7, QEMU was
using Python 2 which happily reads UTF-8 files in text mode.
Python 3 requires either UTF-8 locale or an explicit encoding
passed to open(). Now that Python 3 is required, explicit
UTF-8 encoding for decodetree source files.
To avoid fur
On 1/9/21 1:35 PM, Bin Meng wrote:
> From: Bin Meng
>
> Current implementation of the imx spi controller expects the burst
> length to be multiple of 8, which is the most normal use case.
s/normal/common/?
>
> In case the burst length is not what we expect, log it to give user
> a chance to no
On 1/9/21 1:35 PM, Bin Meng wrote:
> From: Bin Meng
>
> Usually the approach is that the device on the other end of the line
> is going to reset its state anyway, so there's no need to actively
> signal an irq line change during the reset hook.
>
> Move imx_spi_update_irq() out of imx_spi_reset(
Hi,
On 1/9/21 1:35 PM, Bin Meng wrote:
> From: Xuzhou Cheng
>
> When a write to ECSPI_CONREG register to disable the SPI controller,
> imx_spi_reset() is called to reset the controller, but chip select
> lines should have been disabled, otherwise the state machine of any
> devices (e.g.: SPI fla
On 1/9/21 1:35 PM, Bin Meng wrote:
> From: Bin Meng
>
> Avoid using a magic number (4) everywhere for the number of chip
> selects supported.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
> ---
>
> (no changes since v1)
>
> include/hw/ssi/imx_spi.h | 5 -
> hw/ssi/imx_spi.
On 1/9/21 3:36 PM, Bin Meng wrote:
> From: Bin Meng
>
> SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
> there is no need to use #idef to set the mc->default_cpu_type.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/sifive_u.c | 6 +-
> 1 file changed, 1 insertion(+),
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> The vt82c686b-pm model can be shared between VT82C686B and VT8231. The
> only difference between the two is the device id in what we emulate so
> make an abstract via-pm model by renaming appropriately and add types
> for vt82c686b-pm and vt8231-pm based o
On 1/9/21 9:16 PM, BALATON Zoltan wrote:
> This device is part of the multifunction VIA superio/south bridge chip
> so not useful in itself.
>
> Signed-off-by: BALATON Zoltan
> ---
> hw/isa/vt82c686.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
Use the dedicated X86Seg enum type for segment registers.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h| 4 ++--
target/i386/gdbstub.c| 2 +-
target/i386/tcg/seg_helper.c | 8
target/i386/tcg/translate.c | 6 +++---
4 files changed, 10 insertions(+), 1
On Thu, 7 Jan 2021, Philippe Mathieu-Daudé wrote:
On 1/7/21 2:15 AM, BALATON Zoltan wrote:
On Wed, 6 Jan 2021, BALATON Zoltan wrote:
Hello,
This is adding a new PPC board called pegasos2 currently posted as RFC
because it depends on not yet merged VT8231 emulation currently on the
list:
https
Hi Taylor,
On 1/8/21 5:28 AM, Taylor Simpson wrote:
> Signed-off-by: Taylor Simpson
> ---
> target/hexagon/printinsn.h | 28
> target/hexagon/printinsn.c | 158
> +
> 2 files changed, 186 insertions(+)
> create mode 100644 target/hexagon/pr
On 1/8/21 5:28 AM, Taylor Simpson wrote:
> GDB register read and write routines
>
> Signed-off-by: Taylor Simpson
> Reviewed-by: Richard Henderson
> ---
> target/hexagon/internal.h | 3 +++
> target/hexagon/cpu.c | 2 ++
> target/hexagon/gdbstub.c | 47
> +++
On Fri, Dec 18, 2020 at 10:26:53AM +0800, Yifei Jiang wrote:
> Add the support needed for creating prstatus elf notes. Now elf notes
> only contains user_regs. This allows us to use QMP dump-guest-memory.
>
> Signed-off-by: Yifei Jiang
> Signed-off-by: Mingwang Li
> ---
> target/riscv/arch_dump
Hi Taylor,
On 1/8/21 5:28 AM, Taylor Simpson wrote:
> Add hexagon to disas/meson.build
> Add disas/hexagon.c
> Add hexagon to include/disas/dis-asm.h
>
> Signed-off-by: Taylor Simpson
> ---
> include/disas/dis-asm.h | 1 +
> disas/hexagon.c | 68
> +
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II,
a PowerPC board based on the Marvell MV64361 system controller and the
VIA VT8231 integrated south bridge/superio chips. It can run Linux,
AmigaOS and a wide range of MorphOS versions. Currently a firmware ROM
image is needed to
The Marvell Discovery II aka. MV64361 is a PowerPC system controller
chip that is used on the pegasos2 PPC board. This adds emulation of it
that models the device enough to boot guests on this board. The
mv643xx.h header with register definitions is taken from Linux 4.15.10
only fixing end of line
Hello,
v2 adds missing file that's omitted from original series, still based
on "[PATCH v2 0/3] Fix up sam460ex fixes"
Based-on:
This is adding a new PPC board called pegasos2 currently posted as RFC
because it depends on not yet merged VT8231 emulation currently under
review. A working version
The sizeof(struct ifreq) is 40 for 64 bit and 32 for 32 bit architectures.
This structure contains a union of other structures, of which struct ifmap
is the biggest for 64 bit architectures. Calling ioclt(…, SIOCGIFCONF, …)
fills a struct sockaddr of that union, and do_ioctl_ifconf() only considere
Collect superio functionality and its controlling config registers
handling in an abstract VIA_SUPERIO class that is a subclass of
ISA_SUPERIO and put vt82c686b specific parts in a subclass of this
abstract class.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 240
Add emulation of VT8231 south bridge ISA part based on the similar
VT82C686B but implemented in a separate subclass that holds the
differences while reusing parts that can be shared.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 154 ++
include
These functions are memory region callbacks so we have to check
against relative address not the mapped address. Also reduce
indentation by returning early and log unimplemented accesses.
Additionally we remove separate index value from SuperIOConfig and
store the index at reg 0 which is reserved a
In VIA super south bridge the io ranges of superio components
(parallel and serial ports and FDC) can be controlled by superio
config registers to set their base address and enable/disable them.
This is not easy to implement in QEMU because ISA emulation is only
designed to set io base address once
Move lines around so that object definitions become consecutive and
not scattered around. This brings functions belonging to an object
together so it's clearer what is defined and what parts belong to
which object.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt8
Currently the ISA devices that are part of the VIA south bridge,
superio chip are wired up by board code. Move creation of these ISA
devices to the VIA ISA bridge model so that board code does not need
to access ISA bus. This also allows vt82c686b-superio to be made
internal to vt82c686 which allow
The VT8231 south bridge is very similar to VT82C686B but there are
some differences in register addresses and functionality, e.g. the
VT8231 only has one serial port. This commit adds VT8231_SUPERIO
subclass based on the abstract VIA_SUPERIO class to emulate the
superio part of VT8231.
Signed-off-
Remove unneeded variables and setting value to 0 on zero initialised
data and replace check for error with error_fatal. Rationalise loop
that sets PCI config header fields read only.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/isa/vt82c686.c | 20 ++-
The base address of the SMBus io ports and its enabled status is set
by registers in the PCI config space but this was not correctly
emulated. Instead the SMBus registers were mapped on realize to the
base address set by a property to the address expected by fuloong2e
firmware.
Fix the base and co
The vt82c686b-pm model can be shared between VT82C686B and VT8231. The
only difference between the two is the device id in what we emulate so
make an abstract via-pm model by renaming appropriately and add types
for vt82c686b-pm and vt8231-pm based on it.
Signed-off-by: BALATON Zoltan
---
hw/isa
Version 2 of remaining patches for VT8231 emulation addressing review
comments:
- Split off making vt82c686b-pm an abstract class to separate patch
- Use constants for PCI IDs
Regards,
BALATON Zoltan
BALATON Zoltan (13):
vt82c686: Move superio memory region to SuperIOConfig struct
vt82c686:
The superio memory region holds the io space index/data registers used
to access the superio config registers that are implemented in struct
SuperIOConfig. To keep these related things together move the memory
region to SuperIOConfig and rename it accordingly.
Also remove the unused "data" member o
This device is part of the multifunction VIA superio/south bridge chip
so not useful in itself.
Signed-off-by: BALATON Zoltan
---
hw/isa/vt82c686.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index fc2a1f4430..9b16660e9d 100644
---
Similar to the SMBus io registers there is a power management io range
that is set via similar base address reg and enable bit. Some handling
of this was already there but with several problems: using the wrong
registers and bits, wrong size range, not acually updating mapping and
handling reset co
On Sat, Jan 9, 2021 at 10:03 AM Kyle Evans wrote:
> On Fri, 8 Jan 2021 at 19:43, Warner Losh wrote:
> >
> > The FreeBSD project has rewritten bsd-user. We've been working on this
> for quite some time (the earliest commits date from 2013). Maybe a dozen
> people have worked on this over time, an
On Fri, 8 Jan 2021 at 19:43, Warner Losh wrote:
>
> The FreeBSD project has rewritten bsd-user. We've been working on this for
> quite some time (the earliest commits date from 2013). Maybe a dozen people
> have worked on this over time, and there's 3 or 4 active developers focused
> on FreeBSD
From: Bin Meng
SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence
there is no need to use #idef to set the mc->default_cpu_type.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/
Keep setting ret close to setting errp and don't merge different error
paths into one. This way it's more obvious that we don't return
error without setting errp.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block/qcow2.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff
It's better to return status together with setting errp. It makes
possible to avoid error propagation.
While being here, put ERRP_GUARD() to fix error_prepend(errp, ...)
usage inside qcow2_store_persistent_dirty_bitmaps() (see the comment
above ERRP_GUARD() definition in include/qapi/error.h)
Sig
qcow2_do_open correctly sets errp on each failure path. So, we can
simplify code in qcow2_co_invalidate_cache() and drop explicit error
propagation.
Add ERRP_GUARD() as mandated by the documentation in
include/qapi/error.h so that error_prepend() is actually called even if
errp is &error_fatal.
S
Don't use error propagation in qcow2_get_specific_info(). For this
refactor qcow2_get_bitmap_info_list, its current interface is rather
weird.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
block/qcow2.h| 4 ++--
block/qcow2-bitmap.c
It's better to return status together with setting errp. It allows to
reduce error propagation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
block/qcow2.c | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --gi
We leak local_err and don't report failure to the caller. It's
definitely wrong, let's fix.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
blockdev.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/blockdev.c b/blockdev
Better to return status together with setting errp. It allows to avoid
error propagation in the caller.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
include/block/blockjob.h | 2 +-
blockjob.c | 18 --
2 files
Set errp always on failure. Generic bdrv_open_driver supports driver
functions which can return negative value and forget to set errp.
That's a strange thing.. Let's improve bdrv_qed_do_open to not behave
this way. This allows to simplify code in
bdrv_qed_co_invalidate_cache().
Signed-off-by: Vlad
Now bdrv_append returns status and we can drop all the local_err things
around it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 6 ++
block/backup-top.c | 23 +++
block/commit.c | 6 ++
block/mirror.c
This patch is generated by cocci script:
@@
symbol bdrv_open_child, errp, local_err;
expression file;
@@
file = bdrv_open_child(...,
-&local_err
+errp
);
- if (local_err)
+ if (!file)
{
...
- error_propagate(err
Let's check return value of mirror_start_job to check for failure
instead of local_err.
Rename ret to job, as ret is usually integer variable.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
block/mirror.c | 12 +---
1 file changed, 5
bdrv_set_backing_hd now returns status, let's use it.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Greg Kurz
Reviewed-by: Alberto Garcia
---
block.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/block.c b/block.c
index 2a13fbfc73..0d7a62476f 100644
--- a
It's recommended for bool functions with errp to return true on success
and false on failure. Non-standard interfaces don't help to understand
the code. The change is also needed to reduce error propagation.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Alberto Garcia
Reviewed-by: Gre
v5: rebase on master
Vladimir Sementsov-Ogievskiy (14):
block: return status from bdrv_append and friends
block: use return status of bdrv_append()
block: check return value of bdrv_open_child and drop error
propagation
blockdev: fix drive_backup_prepare() missed error
block: drop ex
The recommended use of qemu error api assumes returning status together
with setting errp and avoid void functions with errp parameter. Let's
improve bdrv_append and some friends to reduce error-propagation
overhead in further patches.
Choose int return status, because bdrv_replace_node_common() h
From: Bin Meng
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second
word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second
word.
Current logic uses either s->burst_length or
From: Bin Meng
Avoid using a magic number (4) everywhere for the number of chip
selects supported.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
(no changes since v1)
include/hw/ssi/imx_spi.h | 5 -
hw/ssi/imx_spi.c | 4 ++--
2 files changed, 6 insertions(+), 3 delet
From: Bin Meng
The endianness of data exchange between tx and rx fifo is incorrect.
Earlier bytes are supposed to show up on MSB and later bytes on LSB,
ie: in big endian. The manual does not explicitly say this, but the
U-Boot and Linux driver codes have a swap on the data transferred
to tx fifo
From: Bin Meng
Current implementation of the imx spi controller expects the burst
length to be multiple of 8, which is the most normal use case.
In case the burst length is not what we expect, log it to give user
a chance to notice it.
Signed-off-by: Bin Meng
---
Changes in v3:
- new patch:
We are going to drop group file. Define group in tests as a preparatory
step.
The patch is generated by
cd tests/qemu-iotests
grep '^[0-9]\{3\} ' group | while read line; do
file=$(awk '{print $1}' <<< "$line");
groups=$(sed -e 's/^... //' <<< "$line");
awk "NR==2
From: Bin Meng
Usually the approach is that the device on the other end of the line
is going to reset its state anyway, so there's no need to actively
signal an irq line change during the reset hook.
Move imx_spi_update_irq() out of imx_spi_reset(), along with the
disabling of chip selects, to a
Add TestEnv class, which will handle test environment in a new python
iotests running framework.
Difference with current ./check interface:
- -v (verbose) option dropped, as it is unused
- -xdiff option is dropped, until somebody complains that it is needed
- same for -n option
Signed-off-by: Vl
Add python script with new logic of searching for tests:
Current ./check behavior:
- tests are named [0-9][0-9][0-9]
- tests must be registered in group file (even if test doesn't belong
to any group, like 142)
Behavior of findtests.py:
- group file is dropped
- tests are all files in test
From: Bin Meng
This series fixes a bunch of bugs in current implementation of the imx
spi controller, including the following issues:
- chip select signal was not lower down when spi controller is disabled
- remove imx_spi_update_irq() in imx_spi_reset()
- transfer incorrect data when the burst
From: Xuzhou Cheng
When a write to ECSPI_CONREG register to disable the SPI controller,
imx_spi_reset() is called to reset the controller, but chip select
lines should have been disabled, otherwise the state machine of any
devices (e.g.: SPI flashes) connected to the SPI master is stuck to
its la
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/294 | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qemu-iotests/294 b/tests/qemu-iotests/294
index 87da35db49..4c375ed609 100755
--- a/tests/qemu-iotests/294
+++ b/tests/qemu-iotests/294
@@ -1,3 +1,4 @@
+#!/usr/bin/env
Just use classes introduced in previous three commits. Behavior
difference is described in these three commits.
Drop group file, as it becomes unused.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/check | 994 ++-
tests/qemu-iotests/group
All other test files are executable. Fix these.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/283 | 0
tests/qemu-iotests/298 | 0
tests/qemu-iotests/299 | 0
3 files changed, 0 insertions(+), 0 deletions(-)
mode change 100644 => 100755 tests/qemu-iotests/283
mode change 1
Rename bitmaps migration tests and move them to tests subdirectory to
demonstrate new human-friendly test naming.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
This patch is and RFC and may be postponed. Or may be applied as well..
tests/qemu-iotests/{199 => tests/migrate-bitmaps-postcopy-te
Add TestRunner class, which will run tests in a new python iotests
running framework.
There are some differences with current ./check behavior, most
significant are:
- Consider all tests self-executable, just run them, don't run python
by hand.
- Elapsed time is cached in json file
- Elapsed tim
Hi all!
These series has 3 goals:
- get rid of group file (to forget about rebase and in-list conflicts)
- introduce human-readable names for tests
- rewrite check into python
v6:
04: condense making 283 and 299 executable into one patch. add 298 too
06: handle three more tests
08: add qemu-
If you run './check 277', check includes common.config which adjusts
$PATH to include '.' first, and therefore finds nbd-fault-injector.py
on PATH. But if you run './277' directly, there is nothing to adjust
PATH, and if '.' is not already on your PATH by other means, the test
fails because the ex
We are going to be stricter about comparing test result with .out
files. So, fix some whitespaces now.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/qemu-iotests/175.out | 2 +-
tests/qemu-iotests/271.out | 12 ++--
tests/qemu-iotests/287.out | 10 +-
3 files changed, 12
If you run './check 303', check includes common.config which adjusts
$PATH to include '.' first, and therefore finds qcow2.py on PATH. But
if you run './303' directly, there is nothing to adjust PATH, and if
'.' is not already on your PATH by other means, the test fails because
the executable is n
On Samstag, 9. Januar 2021 00:13:36 CET BALATON Zoltan wrote:
> On Sat, 9 Jan 2021, Roman Bolshakov wrote:
> > On Fri, Jan 08, 2021 at 03:00:07PM +, Peter Maydell wrote:
> >> On Fri, 8 Jan 2021 at 13:50, Peter Maydell
wrote:
> >>> On Sat, 2 Jan 2021 at 15:14, Roman Bolshakov
wrote:
> u
On Sat, 9 Jan 2021 at 05:49, Roman Bolshakov wrote:
>
> On Fri, Dec 18, 2020 at 06:13:47PM -0800, Hill Ma wrote:
> > This prevents illegal instruction on cpus do not support xgetbv.
> >
> > Buglink: https://bugs.launchpad.net/qemu/+bug/1758819
> > Signed-off-by: Hill Ma
> > ---
> > target/i386/h
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