> > SoC changes easily:
> >
> > https://github.com/codyprime/git-scripts/blob/master/git-backport-diff
>
> I've been adding new peripherals incrementally after the basic SoC
> support patch. Is that OK to do without resetting the tags?
>
> But it's more l
On Thu, Jul 9, 2020 at 10:00 AM Philippe Mathieu-Daudé wrote:
>
> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> > This implements a device model for the NPCM7xx SPI flash controller.
> >
> > Direct reads and writes, and user-mode transactions have been tested in
> > various modes. Protection featu
From: Chen Gang
It is for i915 drm command, and next, I shall send another i915 commands
implementations.
Signed-off-by: Chen Gang
---
linux-user/ioctls.h| 3 +++
linux-user/syscall.c | 39 ++
linux-user/syscall_defs.h | 9 +
linux-u
From: Chen Gang
This fix does not consider about the lock feature which may cause
another issues, but excuse me, I don't know how to fix it. At present,
the fix runs OK for my case in windows oledb32.dll in wine.
Welcome anyone to fix it, thanks.
Signed-off-by: Chen Gang
---
target/i386/mem_h
Peter Maydell 于2020年6月29日周一 上午5:43写道：
>
> Replace the free-floating set of IRQs and palmte_onoff_gpios()
> function with a simple QOM device that encapsulates this
> behaviour.
>
> This fixes Coverity issue CID 1421944, which points out that
> the memory returned by qemu_allocate_irqs() is leaked.
Peter Maydell 于2020年6月29日周一 上午5:45写道：
>
> Remove hard-tabs from palm.c.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Li Qiang
> ---
> hw/arm/palm.c | 64 +--
> 1 file changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/hw/arm/palm.c b/h
Hi Mark, no that doesn't work sorry, same error.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1886318
Title:
Qemu after v5.0.0 breaks macos guests
Status in QEMU:
New
Bug description:
The De
Thanks for the bisection, that's really helpful - that particular patch
fixes the way in which memory region access sizes are treated as valid.
The obvious device to look at here is isa-apple-smc since I suspect that
has less CI coverage.
Looking at the access sizes of all 3 MemoryRegions within
h
yup, building debian 5.0-6 package minus that single patch gives me
working macos catalina again.
now just got to figure out why any kernel newer than 5.5 crashes the
host when using pci passthrough - i don't fancy bisecting a whole
kernel!
--
You received this bug notification because you are a
the debian patch is:
revert-memory-accept-mismatching-sizes-in-memory_region_access_valid-
CVE-2020-13754.patch
i'm currently building a deb package without it.
mailserver has a geoip block and doesn't use ipv6, synapticconsulting at
gmail dot com should work.
--
You received this bug notifica
that's an interesting observation. Thank you for finding this one. It'd
be much faster to find one of about 10 debian patches which affects this
but full qemu bisect works too, ofcourse.
Simon, I can't reach you by email, your mailserver apparently
malfunctioning, - I sent you instructions about h
Woohoo! Simply reverting that one commit
5d971f9e672507210e77d020d89e0e89165c8fc9 from today's master gets me
running again.
Not sure where that leaves us though?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launc
On Thu, Jul 09, 2020 at 15:13:22 +0100, Alex Bennée wrote:
> While there isn't any easy way to make the inline counts thread safe
Why not? At least in 64-bit hosts TCG will emit a single write to
update the 64-bit counter.
> we can ensure the callback based ones are. While we are at it we can
> r
On 6/25/20 9:20 AM, Peter Maydell wrote:
> On Fri, 5 Jun 2020 at 05:17, Richard Henderson
> wrote:
>>
>> This data can be allocated by page_alloc_target_data() and
>> released by page_set_flags(start, end, prot | PAGE_RESET).
>>
>> This data will be used to hold tag memory for AArch64 MTE.
>>
>> S
Thanks Mark, what an interesting exercise that was - and sorry, didn't
know 5.1 was due.
So the git bisect revealed this:
$ git bisect good
5d971f9e672507210e77d020d89e0e89165c8fc9 is the first bad commit
commit 5d971f9e672507210e77d020d89e0e89165c8fc9
Author: Michael S. Tsirkin
Date: Wed Jun
On Fri, Jul 10, 2020 at 14:03:27 -0700, Richard Henderson wrote:
> On 7/9/20 7:13 AM, Alex Bennée wrote:
> > Any write to a device might cause a re-arrangement of memory
> > triggering a TLB flush and potential re-size of the TLB invalidating
> > previous entries. This would cause users of qemu_plu
On Thu, Jul 09, 2020 at 15:13:18 +0100, Alex Bennée wrote:
> Any write to a device might cause a re-arrangement of memory
> triggering a TLB flush and potential re-size of the TLB invalidating
> previous entries. This would cause users of qemu_plugin_get_hwaddr()
> to see the warning:
>
> invali
On Thu, Jul 09, 2020 at 15:13:16 +0100, Alex Bennée wrote:
> This attempts to bring together my understanding of the requirements
> for icount behaviour into one reference document for our developer
> notes.
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
Reviewed-by: Emilio G.
On Thu, Jul 09, 2020 at 15:13:15 +0100, Alex Bennée wrote:
> @@ -92,6 +107,7 @@ including:
>
>- debugging operations (breakpoint insertion/removal)
>- some CPU helper functions
> + - linux-user spawning it's first thread
s/it's/its/
Reviewed-by: Emilio G. Cota
Thanks,
On 7/11/20 12:30 PM, Richard Henderson wrote:
>> The old implementation returns true for
>> HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
>> (because there's a different definition of guest_addr_valid() there)
>> but this one does a range check even in that case.
>
> It's part and parcel with patc
On 6/25/20 9:34 AM, Peter Maydell wrote:
> On Fri, 5 Jun 2020 at 05:17, Richard Henderson
> wrote:
>>
>> This is the only use of guest_addr_valid that does not begin
>> with a guest address, but a host address being transformed to
>> a guest address.
>>
>> We will shortly adjust guest_addr_valid t
On 6/25/20 9:37 AM, Peter Maydell wrote:
> On Fri, 5 Jun 2020 at 05:17, Richard Henderson
> wrote:
>>
>> We must always use GUEST_ADDR_MAX, because even 32-bit hosts can
>> use -R to restrict the memory address of the guest.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> include/exec/cpu_ldst
Here's a qtest reproducer:
./i386-softmmu/qemu-system-i386 -M pc,accel=qtest \
-qtest null -nographic -vga qxl -qtest stdio \
-drive if=none,id=drive0,file=null-co://,file.read-zeroes=on,format=raw \
-drive if=none,id=drive1,file=null-co://,file.read-zeroes=on,format=raw \
-device ide-cd,drive=dri
03.07.2020 16:13, Andrey Shinkevich wrote:
Read and dump entries from the bitmap directory of QCOW2 image.
It extends the output in the test case #291.
Header extension:
magic 0x23852875 (Bitmaps)
...
Bitmap name bitmap-1
bitmap_table_offset 0xf
bitma
Alright thanks for the assistance. Regards.
On Sat, 11 Jul 2020 at 19:44, Peter Maydell
wrote:
> On Fri, 3 Jul 2020 at 15:56, Peter Maydell
> wrote:
> >
> > This patchset is essentially a resend of David Carlier's build fixes
> > for the Haiku platform. I've taken David's patches and put them t
On Fri, 10 Jul 2020 at 16:46, Wentong Wu wrote:
>
> Add DISAS_NORETURN case for nothing more to generate because at runtime
> execution will never return from some helper call. And at the same time
> replace DISAS_UPDATE in t_gen_helper_raise_exception and gen_exception
> with the newly added DISA
On Fri, 3 Jul 2020 at 15:56, Peter Maydell wrote:
>
> This patchset is essentially a resend of David Carlier's build fixes
> for the Haiku platform. I've taken David's patches and put them together
> into a set of emails threaded in the way our CI tools expect, as the
> easiest way to get the patc
Here's a qtest reproducer
cat << EOF | ./i386-softmmu/qemu-system-i386 \
-M pc,accel=qtest -qtest null -nographic -vga qxl -qtest stdio -nodefaults \
-drive if=none,id=drive0,file=null-co://,file.read-zeroes=on,format=raw \
-drive if=none,id=drive1,file=null-co://,file.read-zeroes=on,format=raw \
On Sun, 28 Jun 2020 at 22:42, Peter Maydell wrote:
>
> As for spitz and tosa, fix the Coverity issue CID 1421944 which
> points out that memory returned from qemu_allocate_irqs() is leaked
> by encapsulating the GPIO handling into a simple device.
> As with the other series, detabify the file firs
On Sat, 11 Jul 2020 at 00:50, Paolo Bonzini wrote:
>
> The following changes since commit 45db94cc90c286a9965a285ba19450f448760a09:
>
> Merge remote-tracking branch 'remotes/mcayland/tags/qemu-openbios-20200707'
> into staging (2020-07-10 16:43:40 +0100)
>
> are available in the Git repository
Thiago Jung Bauermann writes:
> Alex Bennée writes:
>
>> Thiago Jung Bauermann writes:
>>
>>> Eduardo Habkost writes:
>>>
On Wed, Jul 08, 2020 at 09:11:55PM +0100, Peter Maydell wrote:
> On Wed, 8 Jul 2020 at 18:36, Eduardo Habkost wrote:
> >
> > On Wed, Jul 08, 2020 at 06:
Robert Foley writes:
> Hi,
> Thanks for the detailed feedback! I will look at making these
> changes.
In the interest of getting the CI green I've submitted v2 as is but I'll
roll up Robert's cleanups in my rc0 series (which is hopefully a lot
smaller!).
--
Alex Bennée
On Thu, Jul 9, 2020 at 10:07 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Update virt and sifive_u machines to use the opensbi fw_dynamic bios
> image built for the generic FDT platform.
>
> Remove the out-of-date no longer used bios images.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Anup Patel
>
On Fri, Jul 10, 2020 at 11:36 AM Alistair Francis wrote:
>
> On Thu, Jul 9, 2020 at 10:11 PM Bin Meng wrote:
> >
> > From: Bin Meng
> >
> > Update the install blob list to include the generic platform
> > fw_dynamic bios images.
> >
> > Signed-off-by: Bin Meng
>
> You didn't address the comment
From: Gerd Hoffmann
This reverts commit 8d5a24c83dba90b08ef163bbf166d6dfbad9019b.
Compiling all virtio-gpu objects into a single module isn't a good plan
because the individual objects have different CONFIG_* dependencies.
Leads to module load failures on s390x due to vga support being
disabled,
From: Max Filippov
Switch to the prebuilt xtensa toolchains release 2020.07.
Drop csp toolchain as the csp core is not a part of QEMU.
Add de233_fpu and dsp3400 toolchains to enable DFPU and FPU2000 tests.
Signed-off-by: Max Filippov
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Dau
From: Max Reitz
Otherwise the result is basically unpredictable.
(Note that the precise environment variable to control sorting order is
LC_COLLATE, but LC_ALL overrides LC_COLLATE, and we do not want the
sorting order to be messed up if LC_ALL is set in the environment.)
Reported-by: John Snow
I only spotted this in the small window between my testing with my
registry while waiting for the gitlab PR to go in. As we pre-pull the
registry image we know if that fails there isn't any point attempting
to use the cache. Fall back to the way we used to do it at that point.
Signed-off-by: Alex
From: Gerd Hoffmann
Signed-off-by: Gerd Hoffmann
Signed-off-by: Alex Bennée
Message-Id: <20200710203652.9708-2-kra...@redhat.com>
diff --git a/tests/qtest/Makefile.include b/tests/qtest/Makefile.include
index 98af2c2d93..6a0276fd42 100644
--- a/tests/qtest/Makefile.include
+++ b/tests/qtest/Ma
Do a light conversion to .rst and clean-up some of the language at the
start now MTTCG has been merged for a while.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20200709141327.14631-2-alex.ben...@linaro.org>
diff --git a/docs/devel/index.rst b/docs/devel/index.rst
inde
From: Robert Foley
Added use of a configuration to tests/vm/basevm.py.
The configuration provides parameters used to configure a VM.
This allows for providing alternate configurations to the VM being
created/launched. cpu, machine, memory, and NUMA configuration are all
examples of configuration
From: Jon Doron
The PhyMemMode gdb extension command was missing from the gdb.rst
document.
Signed-off-by: Jon Doron
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200601171609.1665397-1-ari...@gmail.com>
Message-Id: <20200709141327.14631-4-alex.ben...@linaro.or
Like the sed we include earlier we want something more recent for
iotests to work.
Fixes: 57ee95ed
Cc: Max Reitz
Signed-off-by: Alex Bennée
Message-Id: <20200710182238.10675-1-alex.ben...@linaro.org>
diff --git a/.cirrus.yml b/.cirrus.yml
index 69342ae031..f287d23c5b 100644
--- a/.cirrus.yml
++
Fixed a few, dropped a few, added a few
---
The following changes since commit 827937158b72ce2265841ff528bba3c44a1bfbc8:
Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200710' into
staging (2020-07-11 13:56:03 +0100)
are available in the Git repository at:
https://github.co
This attempts to bring together my understanding of the requirements
for icount behaviour into one reference document for our developer
notes.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Cc: Paolo Bonzini
Cc: Pavel Dovgalyuk
Cc: Peter Maydell
Message-Id: <20200709141327.14631-3-
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: d4a6bab1 (
https://gitlab.com/qemu-project/qemu/-/commit/d4a6bab1ecf23d86e20e2f08a144e4e48643a6e4
)
Commit Message: Merge remote-tr
03.07.2020 16:13, Andrey Shinkevich wrote:
Introduce the class BitmapFlags that parses a bitmap flags mask.
Suggested-by: Vladimir Sementsov-Ogievskiy
Signed-off-by: Andrey Shinkevich
---
tests/qemu-iotests/qcow2_format.py | 16
1 file changed, 16 insertions(+)
diff --git
03.07.2020 16:13, Andrey Shinkevich wrote:
There are two ways to initialize a class derived from Qcow2Struct:
1. Pass a block of binary data to the constructor.
2. Pass the file descriptor to allow reading the file from constructor.
Let's change the Qcow2BitmapExt initialization method from 1 to
For supporting multi-precison, split all 32 fp registers into two groups.
The RV64D instructions will use only the 16 fp registers selected by
gfp64().
Signed-off-by: LIU Zhiwei
---
rv64.risu | 100 ++
1 file changed, 100 insertions(+)
diff --
Avoid using stack pointer(x2), thread pointer(x3), global pointer(x4),
as they are not under control of risu.
Besides, avoid using x0 as base address register, because we can't
emit a valid random address by setting x0.
Signed-off-by: LIU Zhiwei
---
rv64.risu | 141 ++
Signed-off-by: LIU Zhiwei
---
risu_reginfo_riscv64.h | 28
1 file changed, 28 insertions(+)
create mode 100644 risu_reginfo_riscv64.h
diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h
new file mode 100644
index 000..4536480
--- /dev/null
+++ b/risu_re
Signed-off-by: LIU Zhiwei
Reviewed-by: Richard Henderson
---
test_riscv64.s | 85 ++
1 file changed, 85 insertions(+)
create mode 100644 test_riscv64.s
diff --git a/test_riscv64.s b/test_riscv64.s
new file mode 100644
index 000..22a22b6
--- /
Signed-off-by: LIU Zhiwei
---
rv64.risu | 41 +
1 file changed, 41 insertions(+)
diff --git a/rv64.risu b/rv64.risu
index edf0d1f..2c4154e 100644
--- a/rv64.risu
+++ b/rv64.risu
@@ -139,3 +139,44 @@ SRLW RISCV 000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW
In general, generate payload.
1. Setup memory for load/store instructions.
2. Initialize the registers.
3. Emit instructions according to instruction format description.
Specially, modify according to RISC-V ISA.
1. Support multi-precision by dividing fp registers into two groups.
2. Use $bytecoun
Ensure $rs2 != $rs1, so that the $rs2 register's value
will not be covered when setting the $rs1 register's value to get
a valid address.
Signed-off-by: LIU Zhiwei
---
rv64.risu | 90 +++
1 file changed, 90 insertions(+)
diff --git a/rv64.risu
For RV64 risu, make CFLAGS="-march=rv64g"
Signed-off-by: LIU Zhiwei
---
configure | 4 +-
upstream/configure | 204 +
2 files changed, 207 insertions(+), 1 deletion(-)
create mode 100644 upstream/configure
diff --git a/configure b/configur
Make it a separate file, so that we can get subarch to recgonize the
instrcution length.
Signed-off-by: LIU Zhiwei
---
rv64c.risu | 97 ++
1 file changed, 97 insertions(+)
create mode 100644 rv64c.risu
diff --git a/rv64c.risu b/rv64c.risu
new
In contrast to the RFC, add more instructions description. Now it supports
RV64IMACFD. Some cross verifications have been done, such as comparison
between QEMU and TinyEMU, and comparison between QEMU and C906 FPGA.
Now it has some productive.
Features:
* support RV64IMACFD.
* support multi-preci
When a risu op emits, the signal handler wll take over execution before
running the payload again.
The signal handler need some interfaces, such as setting struct reginfo
and the comparison of struct reginfo.
Signed-off-by: LIU Zhiwei
---
risu_reginfo_riscv64.c | 132 +++
For supporting multi-precision, split all 32 fp registers into two groups.
The RV64F instructions will use only 16 fp registers selected by gfp32().
Signed-off-by: LIU Zhiwei
---
rv64.risu | 94 +++
1 file changed, 94 insertions(+)
diff --git
Hi,
Thanks for the detailed feedback! I will look at making these changes.
On Fri, 10 Jul 2020 at 15:20, John Snow wrote:
>
>
>
> On 7/7/20 3:08 AM, Alex Bennée wrote:
> > From: Robert Foley
> >
>
> > +def recv(self, n=1, sleep_delay_s=0.1):
> > +"""Return chars from in memory buff
On Thu, Jul 9, 2020 at 5:50 PM Bin Meng wrote:
>
> Hi Palmer,
>
> On Fri, Jul 10, 2020 at 8:45 AM Palmer Dabbelt
> wrote:
> >
> > On Thu, 09 Jul 2020 15:09:18 PDT (-0700), alistai...@gmail.com wrote:
> > > On Thu, Jul 9, 2020 at 3:07 AM Bin Meng wrote:
> > >>
> > >> From: Bin Meng
> > >>
> > >
On Thu, Jul 9, 2020 at 5:48 PM Bin Meng wrote:
>
> Hi Alistair,
>
> On Fri, Jul 10, 2020 at 6:19 AM Alistair Francis wrote:
> >
> > On Thu, Jul 9, 2020 at 3:07 AM Bin Meng wrote:
> > >
> > > From: Bin Meng
> > >
> > > The reset vector codes are subject to change, e.g.: with recent
> > > fw_dyna
On Fri, 10 Jul 2020 at 17:35, Greg Kurz wrote:
>
> The following changes since commit b6d7e9b66f59ca6ebc6e9b830cd5e7bf849d31cf:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
> into staging (2020-07-10 09:01:28 +0100)
>
> are available in the Git repository at:
>
Cleanup read operation.
This module different return of access size.
Signed-off-by: Yoshinori Sato
---
hw/timer/renesas_tmr.c | 106 ++---
1 file changed, 57 insertions(+), 49 deletions(-)
diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c
index 446
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: 82793715 (
https://gitlab.com/qemu-project/qemu/-/commit/827937158b72ce2265841ff528bba3c44a1bfbc8
)
Commit Message: Merge remote-tr
Le 10/07/2020 à 21:53, Josh Kunz a écrit :
> This change includes most widely-available if_tun ioctls that are
> integer typed.
>
> Tested by compiling all linux-user emulators. This patch has also been
> used successfully to run several binaries that utilize these ioctls for
> several months.
>
Hi all
On my 4.17.0-rc1 linux kernel i386 running on qemu, I can't register
the wacom driver emulation
QEMU emulator version 4.2.0 (Debian 1:4.2-3ubuntu6.3)
Copyright (c) 2003-2019 Fabrice Bellard and the QEMU Project developers
[0.395368] ata2.00: configured for MWDMA2
[0.397049] scsi 1:
The doc-comments which document the qdev API are split between the
header file and the C source files, because as a project we haven't
been consistent about where we put them.
Move all the doc-comments in qdev.c to the header files, so that
users of the APIs don't have to look at the implementatio
This patchset adds documentation comments to qdev-core.h (and in a few
cases qdev-properties.h) to functions (but not all functions!) which
were missing them.
The prompt for this was Markus' recent welcome cleanup and correction
of the qdev realize functions to get reference count and bus parentin
Add documentation comments for the various qdev functions
related to creating and connecting GPIO lines.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 191 -
1 file changed, 189 insertions(+), 2 deletions(-)
diff --git a/include/hw/qdev-core.h
Add a doc comment for qdev_unrealize(), to go with the new
documentation for the realize part of the qdev lifecycle.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
in
On Fri, 10 Jul 2020 at 14:11, Anthony PERARD wrote:
>
> The following changes since commit b6d7e9b66f59ca6ebc6e9b830cd5e7bf849d31cf:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request'
> into staging (2020-07-10 09:01:28 +0100)
>
> are available in the Git repository a
26.06.2020 17:31, Andrey Shinkevich wrote:
The script 'bench_write_req.py' allows comparing performances of write
request for two qemu-img binary files.
An example with (qemu-img binary 1) and without (qemu-img binary 2) the
applied patch "qcow2: skip writing zero buffers to empty COW areas"
(git
Hello
I am a student from Fudan University in China. I am doing research on CVE
patch recently. But i can not find the PATCH COMMIT of CVE-2019-12247
cve-2019-12155 cve-2019-6778.Can you give me the commit fix this cve?
On Fri, 10 Jul 2020 at 00:04, Michael S. Tsirkin wrote:
>
> Fixes a single bug in vdpa.
>
> The following changes since commit eb2c66b10efd2b914b56b20ae90655914310c925:
>
> Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-07-06'
> into staging (2020-07-07 19:47:26 +0100)
>
>
On 7/11/20 2:19 PM, Paolo Bonzini wrote:
> On 11/07/20 13:49, Claudio Fontana wrote:
>>> Apart from the name, icount is more like deterministic execution than
>>
>> Maybe we should start choosing names more carefully in a way to express what
>> we mean?
>
> I don't disagree. For icount in partic
On 11/07/20 13:49, Claudio Fontana wrote:
>> Apart from the name, icount is more like deterministic execution than
>
> Maybe we should start choosing names more carefully in a way to express what
> we mean?
I don't disagree. For icount in particular however we're about 12 years
too late.
>> q
When I switch to armv7 the issue goes away
$ cat Dockerfile.armv7
FROM arm32v7/ubuntu
RUN apt-get update && \
apt-get install -y \
gcc make libpcre3-dev libreadline-dev git
RUN cd /home && git clone https://github.com/nginx/njs
RUN cd /home/njs && ./configure --cc-opt='-O0 -static -lm -
Indeed it is, but bear in mind it was QEMU 5.1 release feature freeze
this week so most developers are busy rebasing and fixing up bugs from
the resulting merge.
Given that you have already built QEMU from source, what would help
enormously is if you can do a "git bisect" between the v5.0.0 tag
(w
On 7/11/20 11:39 AM, Paolo Bonzini wrote:
> On 11/07/20 11:14, Claudio Fontana wrote:
>> On 7/11/20 12:45 AM, Paolo Bonzini wrote:
>>> On 10/07/20 06:36, Thomas Huth wrote:
In short this goes away if I again set icount to enabled for qtest,
basically ensuring that --enable-tcg is the
On 7/10/20 8:33 AM, Cornelia Huck wrote:
> On Thu, 9 Jul 2020 20:46:56 +0200
> Claudio Fontana wrote:
>
>> On 7/9/20 8:38 PM, Claudio Fontana wrote:
>>> On 7/8/20 5:05 PM, Paolo Bonzini wrote:
On 08/07/20 17:00, Claudio Fontana wrote:
>> Bisectable, 100% failure rate, etc. :( Can yo
qemu console screenshot, this is as far as it gets after clover:
https://i.imgur.com/HWY96Kq.png
same result with or without usb/pci passthrough, qxl/vnc, git master
HEAD or debian 5.0-6
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 47 +++--
1 file changed, 34 insertions(+), 13 deletio
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 123
1 file changed, 123 insertions(+)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 9d59c1815a9e..348822bd
Test exact division/sqrt DFPU sequences.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_div.S | 82
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +
2 files changed, 158 insertions(+)
create mode 100644 tests/tcg/xtensa/test_fp0_d
DFPU conversion opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp0_conv.S | 299 ---
1 file changed, 155 insertions(+), 144 deletions(-)
diff --git a/tests/
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/fpu.h| 142
tests/tcg/xtensa/test_fp0_arith.S | 178 ++
2 file
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_fp1.S | 62 -
1 file changed
Test that madd doesn't do rounding after multiplication.
Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for FPU2000 and DFPU
tests/tcg/xtensa/test_fp0_arith.S | 104 ++
1 file chan
DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA
does not specify how single-precision values are stored in 64-bit
registers. Existing implementations store them in the low half of the
registers.
Add value extraction and write back to single-precision opcodes.
Add new double
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b/te
BR registers used in FPU comparison opcodes are available as opcode
arguments for translators. Use them. This simplifies comparison helpers
interface and makes them usable in FLIX bundles.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/fpu_helper.c | 42 +++
Add test for basic double precision opcode properties.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- add more infzero tests for DFPU
- fix test names in test_dfp0_arith.S
tests/tcg/xtensa/test_dfp0_arith.S | 162 +
1 file changed, 162 insertions(+)
create mode 1
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumula
This does not implement all opcodes related to div/sqrt as specified in
the xtensa ISA, partly because the official specification is not
complete and partly because precise implementation is unnecessarily
complex. Instead instructions specific to the div/sqrt sequences are
implemented differently,
Move FSR/FCR register accessors from core opcodes to FPU2000 opcodes as
they are FPU2000-specific.
Reviewed-by: Richard Henderson
Signed-off-by: Max Filippov
---
target/xtensa/translate.c | 64 +++
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git
FLIX dependency breaking code assumes that all registers are 32 bit
wide. This may not always be correct.
Extract actual register width from the associated register file and use
it to create temporaries of correct width and generate correct data
movement instructions.
Signed-off-by: Max Filippov
Add _s suffix to all FPU2000 opcode translators and helpers that also
have double-precision variant to unify naming and allow adding DFPU
implementations. Add _fpu2k_ to the names of helpers that will have
different implementation for the DFPU .
Reviewed-by: Richard Henderson
Signed-off-by: Max F
Register file name may not uniquely identify a register file in the set
of configurations. E.g. floating point registers may have different size
in different configurations. Use register file geometry as additional
identifier.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 2 +-
ta
1 - 100 of 120 matches
Mail list logo
