On Wed, Jul 8, 2020 at 11:04 PM Philippe Mathieu-Daudé wrote:
>
> On 7/9/20 2:35 AM, Havard Skinnemoen wrote:
> > Implement a device model for the System Global Control Registers in the
> > NPCM730 and NPCM750 BMC SoCs.
> >
> > This is primarily used to enable SMP boot (the boot ROM spins reading
On Jul 8 21:47, Dmitry Fomichev wrote:
>
> > -Original Message-
> > From: Klaus Jensen
> > Sent: Wednesday, July 8, 2020 5:24 PM
> > To: Dmitry Fomichev
> > Cc: qemu-bl...@nongnu.org; qemu-devel@nongnu.org; f...@euphon.net;
> > javier.g...@samsung.com; kw...@redhat.com; mre...@redhat.co
On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> The Nuvoton NPCM7xx SoC family are used to implement Baseboard
> Management Controllers in servers. While the family includes four SoCs,
> this patch implements limited support for two of them: NPCM730 (targeted
> for Data Center applications) and NPCM7
On 7/9/20 7:57 AM, Philippe Mathieu-Daudé wrote:
> On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
>> This adds two new machines, both supported by OpenBMC:
>>
>> - npcm750-evb: Nuvoton NPCM750 Evaluation Board.
>> - quanta-gsj: A board with a NPCM730 chip.
>>
>> They rely on the NPCM7xx SoC device
On 7/9/20 2:35 AM, Havard Skinnemoen wrote:
> Implement a device model for the System Global Control Registers in the
> NPCM730 and NPCM750 BMC SoCs.
>
> This is primarily used to enable SMP boot (the boot ROM spins reading
> the SCRPAD register) and DDR memory initialization; other registers are
On Wed, Jul 8, 2020 at 3:30 AM Gerd Hoffmann wrote:
> Hi,
>
> > IIRC, without the dev-storage patch, the very first SCSI command
> > would get stuck waiting for the CSW, because the CSW is not a
> > multiple of MPS. I will have to work on getting a debug trace for
> > you, I'll get back to you
On 2020/7/8 下午10:16, Peter Xu wrote:
On Wed, Jul 08, 2020 at 01:42:30PM +0800, Jason Wang wrote:
So it should be functional equivalent to vtd_as_has_notifier().
For example: in vtd_iommu_replay() we'll skip the replay if vhost has
registered the iommu notifier because vtd_as_has_map_notifier(
On 7/9/20 2:36 AM, Havard Skinnemoen wrote:
> This adds two new machines, both supported by OpenBMC:
>
> - npcm750-evb: Nuvoton NPCM750 Evaluation Board.
> - quanta-gsj: A board with a NPCM730 chip.
>
> They rely on the NPCM7xx SoC device to do the heavy lifting. They are
> almost completely
On 2020/7/8 上午2:45, Laurent Vivier wrote:
v4: use qemu_try_set_nonblock() with vhostfd in net_init_tap_one(),
and with fd in net_init_socket()
v3: move qemu_fd_is_valid() checking into a new function
qemu_try_set_nonblock(), and use qemu_try_set_nonblock() in
qemu_set_nonblock()
GCC supports "#pragma GCC diagnostic" since version 4.6, and
Clang seems to support it, too, since its early versions 3.x.
That means that our minimum required compiler versions all support
this pragma already and we can remove the test from configure and
all the related #ifdefs in the code.
Signe
On 7/9/20 2:06 AM, Havard Skinnemoen wrote:
> On Wed, Jul 8, 2020 at 11:13 AM Havard Skinnemoen
> wrote:
>> On Wed, Jul 8, 2020 at 10:31 AM Philippe Mathieu-Daudé
>> wrote:
>>> On 7/7/20 8:47 PM, Havard Skinnemoen wrote:
+typedef struct NPCM7xxClass {
+DeviceClass parent;
>
Python script that dissects QEMU execution into three main phases:
code generation, JIT execution and helpers execution.
Syntax:
dissect.py [-h] -- [] \
[]
[-h] - Print the script arguments help message.
Example of usage:
dissect.py -- qemu-arm coulomb_double-arm
Example outp
Hi,
This series adds the dissect.py script which breaks down the execution
of QEMU into three main phases:
code generation, JIT execution, and helpers execution.
It prints the number of instructions executed by QEMU in each of these
three phases, plus the total number of executed instructions.
T
On 08/07/2020 22.01, Alexander Bulekov wrote:
> In 45222b9a90, I fixed a broken check for rcu_enable_atfork introduced
> in d6919e4cb6. I added a call to rcu_enable_atfork after the
> call to qemu_init in fuzz.c, but forgot to include the corresponding
> header, breaking --enable-fuzzing --enable-w
On 7/9/20 2:23 AM, Havard Skinnemoen wrote:
> On Wed, Jul 8, 2020 at 10:56 AM Philippe Mathieu-Daudé
> wrote:
>>
>> On 7/8/20 7:31 PM, Philippe Mathieu-Daudé wrote:
>>> Hi Havard,
>>>
>>> On 7/7/20 8:47 PM, Havard Skinnemoen wrote:
The Nuvoton NPCM7xx SoC family are used to implement Baseboa
On 09/07/2020 07.09, Philippe Mathieu-Daudé wrote:
> On 7/9/20 7:03 AM, Philippe Mathieu-Daudé wrote:
>> On 7/8/20 10:01 PM, Alexander Bulekov wrote:
>>> In 45222b9a90, I fixed a broken check for rcu_enable_atfork introduced
>>> in d6919e4cb6. I added a call to rcu_enable_atfork after the
>>> call
On 7/9/20 3:09 AM, Bin Meng wrote:
> From: Bin Meng
>
> At present the size of Mask ROM for sifive_u / spike / virt machines
> is set to 0x11000, which ends at an unusual address. This changes the
> size to 0xf000 so that it ends at 0x1.
Maybe the size is correct but the first 4K are shadowe
On Wed, Jul 8, 2020 at 5:19 PM Richard Henderson
wrote:
> Do I read that right,
[...]
> means that if DFP is present, float64 has use_first_nan, but float32 does
> not?!?
That's correct. And float64 madd.d/msub.d again don't have it.
> What in the world is going on?
My thoughts exactly. What I
On 7/8/20 11:39 PM, Eduardo Habkost wrote:
> On Wed, Jul 08, 2020 at 06:45:57PM +0200, Philippe Mathieu-Daudé wrote:
>> On 7/8/20 5:25 PM, Eduardo Habkost wrote:
>>> On Wed, Jul 08, 2020 at 02:14:03PM +0100, Peter Maydell wrote:
On Wed, 8 Jul 2020 at 12:12, David Gibson
wrote:
> On
On 7/9/20 7:03 AM, Philippe Mathieu-Daudé wrote:
> On 7/8/20 10:01 PM, Alexander Bulekov wrote:
>> In 45222b9a90, I fixed a broken check for rcu_enable_atfork introduced
>> in d6919e4cb6. I added a call to rcu_enable_atfork after the
>> call to qemu_init in fuzz.c, but forgot to include the corresp
On Wed, Jul 8, 2020 at 5:41 PM Philippe Mathieu-Daudé wrote:
>
> Hi Ahmed,
>
> On 7/2/20 4:29 PM, Ahmed Karaman wrote:
> > Python script that dissects QEMU execution into three main phases:
> > code generation, JIT execution and helpers execution.
> >
> > Syntax:
> > dissect.py [-h] -- [] \
> >
On 7/8/20 10:01 PM, Alexander Bulekov wrote:
> In 45222b9a90, I fixed a broken check for rcu_enable_atfork introduced
> in d6919e4cb6. I added a call to rcu_enable_atfork after the
> call to qemu_init in fuzz.c, but forgot to include the corresponding
> header, breaking --enable-fuzzing --enable-we
On 7/8/20 10:01 PM, Alexander Bulekov wrote:
> When configuring with --enable-fuzzing, we overwrote the CFLAGS
> added by all the preceding checks. Instead of overwriting CFLAGS, append
> the ones we need.
>
> Fixes: adc28027ff ("fuzz: add configure flag --enable-fuzzing")
> Reported-by: Li Qiang
I shall try to send another DRM_IOCTL_* patches within this weekend.
Thanks.
On 2020/6/29 下午7:05, Laurent Vivier wrote:
> Le 05/06/2020 à 03:32, cheng...@emindsoft.com.cn a écrit :
>> From: Chen Gang
>>
>> Another DRM_IOCTL_* commands will be done later.
>>
>> Signed-off-by: Chen Gang
>>
...
>
Patchew URL:
https://patchew.org/QEMU/1594266433-21621-1-git-send-email-zhengch...@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SC
From: Zheng Chuan
"tmp.tls_hostname" and "tmp.tls_creds" allocated by migrate_params_test_apply()
is forgot to free at the end of qmp_migrate_set_parameters(). Fix that.
The leak stack:
Direct leak of 2 byte(s) in 2 object(s) allocated from:
#0 0xb597c20b in __interceptor_malloc (/usr/lib
Thiago Jung Bauermann writes:
> I'm seeing the vcpu being KVM_RUN'd too early twice during hotplug.
> Both of them are before cpu_reset() and ppc_cpu_reset().
Hm, rereading the message obviously the above is partially wrong. The
second case happens during ppc_cpu_reset().
> Here's the second:
Eduardo Habkost writes:
> On Wed, Jul 08, 2020 at 09:11:55PM +0100, Peter Maydell wrote:
>> On Wed, 8 Jul 2020 at 18:36, Eduardo Habkost wrote:
>> >
>> > On Wed, Jul 08, 2020 at 06:09:49PM +0100, Peter Maydell wrote:
>> > > Exactly. It appears that there's a bug in our mechanisms,
>> > > which
You should then find out why libqemu_plugin.dll.a is not working. It is
possible though that your linked is calling the import library something
else, for instance adding a .dll extension to it.
You will have to run a few tests with your linker (I'd just use the
examples from the stackoverflow lin
This script is intended to be used right after a push to a branch.
By default, it will look for the pipeline associated with the commit
that is the HEAD of the *local* staging branch. It can be used as a
one time check, or with the `--wait` option to wait until the pipeline
completes.
If the pip
The idea about a public facing Gating CI for QEMU was summarized in an
RFC[1]. Since then, it was decided that a simpler version should be
attempted first.
At this point, there are two specific runners (an aarch64 and an s390)
registered with GitLab, at https://gitlab.com/qemu-project, currently
This is a mapping of Peter's "remake-merge-builds" and
"pull-buildtest" scripts, gone through some updates, adding some build
option and removing others.
The jobs currently cover the machines that the QEMU project owns, and that
are setup and ready to run jobs:
- Ubuntu 18.04 on S390x
- Ubuntu
From: Bin Meng
The reset vector codes are subject to change, e.g.: with recent
fw_dynamic type image support, it breaks oreboot again.
Add a subregion in the MROM, with the size of machine RAM stored,
so that we can provide a reliable way for bootloader to detect
whether it is running in QEMU.
From: Bin Meng
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x1.
Signed-off-by: Bin Meng
---
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c| 2 +-
hw/riscv/vir
On Wed, 8 Jul 2020, Philippe Mathieu-Daudé wrote:
On 7/7/20 8:08 PM, Volker Rümelin wrote:
In function oss_read() a read error currently does not exit the
read loop. With no data to read the variable pos will quickly
underflow and a subsequent successful read overwrites memory
outside the buffer
+qemu-trivial
On 7/8/20 8:45 AM, Michael S. Tsirkin wrote:
> On Fri, Jul 03, 2020 at 08:34:50PM +0200, Philippe Mathieu-Daudé wrote:
>> Add an entry to cover firmware.json (see commit 3a0adfc9bf:
>> schema that describes the different uses and properties of
>> virtual machine firmware).
>>
>> C
Daniel P. Berrangé writes:
> On Mon, Jul 06, 2020 at 06:23:00PM +0200, Christophe de Dinechin wrote:
>> There are a number of unnecessary trailing whitespaces that have
>> accumulated over time in the source code. They cause stray changes
>> in patches if you use tools that automatically remove t
Fix the compile issue in the system without the kvm support
Signed-off-by: Cindy Lu
---
hw/virtio/vhost-vdpa.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index a3d17fe0f9..65d5aaf08a 100644
--- a/hw/virtio/vhost-vdpa.c
++
Marc-André Lureau writes:
> This is a regression from commit
> d2623129a7dec1d3041ad1221dda1ca49c667532 ("qom: Drop parameter @errp of
> object_property_add() & friends").
>
> (qemu) chardev-add id=null,backend=null
> (qemu) chardev-add id=null,backend=null
> Unexpected error in object_property_t
This allows these NPCM7xx-based boards to boot from a flash image, e.g.
one built with OpenBMC. For example like this:
IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc
qemu-system-arm -machine quanta-gsj -nographic \
-bios ~/qemu/bootrom/npcm7xx_bootrom.bin \
-drive file=${IM
This implements a device model for the NPCM7xx SPI flash controller.
Direct reads and writes, and user-mode transactions have been tested in
various modes. Protection features are not implemented yet.
All the FIU instances are available in the SoC's address space,
regardless of whether or not the
Hi Thiago,
On 7/8/20 1:28 AM, Thiago Jung Bauermann wrote:
>
> Hello Eduardo,
>
> Eduardo Habkost writes:
>
>> On Tue, Jul 07, 2020 at 05:43:33PM -0300, Thiago Jung Bauermann wrote:
>>> PowerPC sPAPRs CPUs start in the halted state, but generic QEMU code
>>> assumes that CPUs start in the non-
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h| 2 +
include/hw/mem/npcm7xx_mc.h | 36
hw/arm/npcm7xx.c
Reviewed-by: Cédric Le Goater
Signed-off-by: Havard Skinnemoen
---
docs/system/arm/nuvoton.rst | 92 +
docs/system/target-arm.rst | 1 +
2 files changed, 93 insertions(+)
create mode 100644 docs/system/arm/nuvoton.rst
diff --git a/docs/system/arm/nuvoton.r
If a -bios option is specified on the command line, load the image into
the internal ROM memory region, which contains the first instructions
run by the CPU after reset.
A minimal Apache-2.0-licensed boot ROM can be found at
https://github.com/google/vbootrom
It is by no means feature complete,
The Nuvoton NPCM7xx SoC family are used to implement Baseboard
Management Controllers in servers. While the family includes four SoCs,
this patch implements limited support for two of them: NPCM730 (targeted
for Data Center applications) and NPCM750 (targeted for Enterprise
applications).
This pat
This adds two new machines, both supported by OpenBMC:
- npcm750-evb: Nuvoton NPCM750 Evaluation Board.
- quanta-gsj: A board with a NPCM730 chip.
They rely on the NPCM7xx SoC device to do the heavy lifting. They are
almost completely identical at the moment, apart from the SoC type,
which cu
Enough functionality to boot the Linux kernel has been implemented. This
includes:
- Correct power-on reset values so the various clock rates can be
accurately calculated.
- Clock enables stick around when written.
In addition, a best effort attempt to implement SECCNT and CNTR25M was
mad
Implement a device model for the System Global Control Registers in the
NPCM730 and NPCM750 BMC SoCs.
This is primarily used to enable SMP boot (the boot ROM spins reading
the SCRPAD register) and DDR memory initialization; other registers are
best effort for now.
The reset values of the MDLR and
The NPCM730 and NPCM750 SoCs have three timer modules each holding five
timers and some shared registers (e.g. interrupt status).
Each timer runs at 25 MHz divided by a prescaler, and counts down from a
configurable initial value to zero. When zero is reached, the interrupt
flag for the timer is s
This supports reading and writing OTP fuses and keys. Only fuse reading
has been tested. Protection is not implemented.
Reviewed-by: Avi Fishman
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Havard Skinnemoen
---
include/hw/arm/npcm7xx.h | 3 +
include/hw/nvram/npcm7xx_otp.h | 88
I also pushed this and the previous two patchsets to my qemu fork on github.
The branches are named npcm7xx-v[1-5].
https://github.com/hskinnemoen/qemu
This patch series models enough of the Nuvoton NPCM730 and NPCM750 SoCs to boot
an OpenBMC image built for quanta-gsj. This includes device mod
On 7/7/20 8:08 PM, Volker Rümelin wrote:
> In function oss_read() a read error currently does not exit the
> read loop. With no data to read the variable pos will quickly
> underflow and a subsequent successful read overwrites memory
> outside the buffer. This patch adds the missing break statement
On 7/7/20 8:37 PM, Peter Maydell wrote:
> On Mon, 6 Jul 2020 at 17:48, Paolo Bonzini wrote:
>>
>> The following changes since commit fc1bff958998910ec8d25db86cd2f53ff125f7ab:
>>
>> hw/misc/pca9552: Add missing TypeInfo::class_size field (2020-06-29
>> 21:16:10 +0100)
>>
>> are available in the
On Wed, Jul 8, 2020 at 8:08 AM Bruce Rogers wrote:
>
> On Fri, 2020-07-03 at 05:05 -0400, Michael S. Tsirkin wrote:
> > From: Cindy Lu
> >
> > Currently we have 2 types of vhost backends in QEMU: vhost kernel and
> > vhost-user. The above patch provides a generic device for vDPA
> > purpose,
> >
On 2020/7/8 下午3:12, Cindy Lu wrote:
Fix the compile issue in the system without the kvm support
Signed-off-by: Cindy Lu
---
hw/virtio/vhost-vdpa.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index a3d17fe0f9..65d5aaf
On Wed, Jul 8, 2020 at 10:56 AM Philippe Mathieu-Daudé wrote:
>
> On 7/8/20 7:31 PM, Philippe Mathieu-Daudé wrote:
> > Hi Havard,
> >
> > On 7/7/20 8:47 PM, Havard Skinnemoen wrote:
> >> The Nuvoton NPCM7xx SoC family are used to implement Baseboard
> >> Management Controllers in servers. While th
On 7/8/20 10:37 AM, Max Filippov wrote:
> On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
> wrote:
>>
>> On 7/6/20 4:47 PM, Max Filippov wrote:
>>> +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
>>> +{
>>> +set_use_first_nan(true, &env->fp_status);
>>> +return float64_a
Sorry for the late reply, response inline. Also I noticed a couple
mails ago I seemed to have removed the devel list and maintainers.
I've re-added them to the CC line.
On Wed, Jun 24, 2020 at 3:17 AM Alex Bennée wrote:
>
>
> Josh Kunz writes:
>
> > On Tue, Jun 23, 2020, 1:21 AM Alex Bennée wro
Hi,
qemu-system-ppc64 currently abort()s when it is started with a pcie
bridge device:
$ qemu-system-ppc64 -M pseries-5.1 -device pcie-pci-bridge
Unexpected error in object_property_find() at qom/object.c:1240:
qemu-system-ppc64: -device pcie-pci-bridge: Property '.chassis_nr' not found
Aborte
On Wed, Jul 8, 2020 at 11:13 AM Havard Skinnemoen
wrote:
> On Wed, Jul 8, 2020 at 10:31 AM Philippe Mathieu-Daudé
> wrote:
> > On 7/7/20 8:47 PM, Havard Skinnemoen wrote:
> > > +typedef struct NPCM7xxClass {
> > > +DeviceClass parent;
> >
> > Similar comment that elsewhere on this se
On 7/8/20 3:20 PM, Max Filippov wrote:
> pickNaNMulAdd logic on Xtensa is to apply pickNaN to the inputs of the
> expression (a * b) + c. However if default NaN is produces as a result
> of (a * b) calculation it is not considered when c is NaN.
> So with two pickNaN variants there must be two pick
On 08/07/20 09:40, Claudio Fontana wrote:
> Ciao Paolo,
>
> On 7/7/20 7:01 PM, Paolo Bonzini wrote:
>> On 07/07/20 15:58, Claudio Fontana wrote:
>>> +static void kvm_kick_vcpu_thread(CPUState *cpu)
>>> +{
>>> +cpus_kick_thread(cpu);
>>> +}
>>> +
>>
>> I would just use cpus_kick_thread instead
On 7/8/20 3:20 PM, Max Filippov wrote:
> Pass float_status structure pointer to the pickNaN so that
> machine-specific settings are available to NaN selection code.
> Add use_first_nan property to float_status and use it in Xtensa-specific
> pickNaN.
>
> Cc: Peter Maydell
> Cc: "Alex Bennée"
> R
On 7/8/20 3:20 PM, Max Filippov wrote:
> target/xtensa, the only user of NO_SIGNALING_NANS macro has FPU
> implementations with and without the corresponding property. With
> NO_SIGNALING_NANS being a macro they cannot be a part of the same QEMU
> executable.
> Replace macro with new property in fl
Alexander Bulekov 于2020年7月9日周四 上午4:02写道：
>
> When configuring with --enable-fuzzing, we overwrote the CFLAGS
> added by all the preceding checks. Instead of overwriting CFLAGS, append
> the ones we need.
>
> Fixes: adc28027ff ("fuzz: add configure flag --enable-fuzzing")
> Reported-by: Li Qiang
>
I did try the most recent OVMF from QEMU 5.0
(https://git.qemu.org/?p=qemu.git;a=blob_plain;f=pc-
bios/edk2-x86_64-code.fd.bz2;hb=fdd76fecdde) and there was no
difference.
I will re-build qemu sometime soon.
===
$ cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu famil
On 6/16/20 12:51 AM, Philippe Mathieu-Daudé wrote:
> -reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
> +reload = muldiv64(s->regs[WDT_RELOAD_VALUE],
> + NANOSECONDS_PER_SECOND / SCALE_US,
>s->pclk_freq);
Sim
On 6/16/20 12:51 AM, Philippe Mathieu-Daudé wrote:
> +timer_mod(NVRAM->alrm_timer_ms,
> + qemu_clock_get_ms(rtc_clock) + next_time_s *
> + NANOSECONDS_PER_SECOND /
> SCALE_MS);
I'm not keen on this last.
I would much prefer a MILLISECO
On 6/16/20 12:51 AM, Philippe Mathieu-Daudé wrote:
> This series contains few patches resulting from the notes I
> took while reviewing Mark ADB series last Sunday, in particular:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg712078.html
>
> I have another patch for hw/input/hid.c but I
On Wed, Jul 8, 2020 at 12:16 AM Stefan Berger
wrote:
>
> The TPM 2 code in libtpms was fixed to handle the PCR 'TCB group' according
> to the PCClient profile. The change of the PCRs belonging to the 'TCB group'
> now affects the pcrUpdateCounter in the TPM2_PCRRead() responses where its
> value i
Hi,
> > Why does 7ad3d51ebb8a522ffcad391c4bef281245739dde look at short-not-ok?
>
> Because the patch changes dev-storage to terminate the transfer if a
> short packet is received, so I figured 'short-not-ok' should affect
> that behavior.
I don't think so. dev-storage should not need to look
Patchew URL: https://patchew.org/QEMU/20200708224615.114077-1-jus...@redhat.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
Patchew URL: https://patchew.org/QEMU/20200708224615.114077-1-jus...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
BALATON Zoltan writes:
> On Mon, 29 Jun 2020, Philippe Mathieu-Daudé wrote:
>> Use popcount instruction to count the number of bits set in
>> the RAM size. Allow at most 1 bit for each bank. This avoid
>> using invalid hardware configurations.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>
Fix the compile issue in the system without the kvm support
Signed-off-by: Cindy Lu
---
hw/virtio/vhost-vdpa.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index a3d17fe0f9..65d5aaf08a 100644
--- a/hw/virtio/vhost-vdpa.c
++
Add acpi_pcihp to ich9_pm and use ACPI PCI hot-plug by default.
Signed-off-by: Julia Suvorova
---
include/hw/acpi/ich9.h | 3 +++
hw/acpi/ich9.c | 45 ++
hw/acpi/pcihp.c| 3 ++-
hw/i386/pc.c | 4 +++-
4 files changed, 53 insert
Other methods may be used if the system is capable of this and the _OSC bit
is set. Disable them explicitly to force ACPI PCI hot-plug use. The older
versions will still use PCIe native.
Signed-off-by: Julia Suvorova
---
hw/i386/acpi-build.c | 12
1 file changed, 8 insertions(+), 4
> It seems systemd is trying to use RTM_SETLINK.
> Could you try this patch:
Yes, you are right!
With the patch, I am able to boot containers of
Debian Bullseye of armhf and armel architectures!!
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Implement notifications and gpe to support q35 ACPI PCI hot-plug.
The addresses specified in [1] remain the same to make fewer changes.
[1] docs/spec/acpi_pci_hotplug.txt
Signed-off-by: Julia Suvorova
---
hw/i386/acpi-build.c | 20 +---
1 file changed, 13 insertions(+), 7 deleti
On Wed, Jul 08, 2020 at 04:49:22PM +0800, Cindy Lu wrote:
> Fix the compile issue in the system without the kvm support
>
> Signed-off-by: Cindy Lu
Applied, thanks!
Peter if we need this fixed quickly, I pushed out for_upstream
just with this one fix.
Thanks!
> ---
> hw/virtio/vhost-vdpa.c |
Returns the current host bus with ACPI PCI hot-plug support: q35 or i440fx.
Signed-off-by: Julia Suvorova
---
hw/i386/acpi-build.h | 2 ++
hw/acpi/pcihp.c | 13 +
hw/i386/acpi-build.c | 2 +-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/i386/acpi-build.h b
The SMMU IIDR register is at 0x018 offset.
Signed-off-by: Eric Auger
Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton")
---
hw/arm/smmuv3-internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 5babf72f7d..ef093eaff5 10
Let's introduce an helper for S1 IOVA range invalidation.
This will be used for NH_VA and NH_VAA commands. It decodes
the same fields, trace, calls the UNMAP notifiers and
invalidate the corresponding IOTLB entries.
At the moment, we do not support 3.2 range invalidation yet.
So it reduces to a si
PCIe native hot-plug has numerous problems with racing events and unpredictable
guest behaviour (Windows). Switching to ACPI hot-plug for now.
Tested on RHEL 8 and Windows 2019.
pxb-pcie is not yet supported.
Julia Suvorova (5):
hw/acpi/pcihp: Introduce find_host()
hw/acpi/ich9: Trace ich9_g
Add ldi[p]/sdi[p]/ldx[p]/sdx[p] opcode tests to test_lsc.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/test_lsc.S | 123
1 file changed, 123 insertions(+)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 9d59c1815a9e..348822bd
Daniel P. Berrangé writes:
> Currently at startup if using cache=none on a filesystem lacking
> O_DIRECT such as tmpfs, at startup QEMU prints
>
> qemu-system-x86_64: -drive file=/tmp/foo.img,cache=none: file system may not
> support O_DIRECT
> qemu-system-x86_64: -drive file=/tmp/foo.img,cache=
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/fpu.h| 142
tests/tcg/xtensa/test_fp0_arith.S | 178 ++
2 file
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/macros.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b/te
Daniel P. Berrangé writes:
> Create a "qemu_open_err" method which does the same as "qemu_open",
> but with a "Error **errp" for error reporting. There should be no
> behavioural difference for existing callers at this stage.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> include/qemu/osdep.h |
Register file name may not uniquely identify a register file in the set
of configurations. E.g. floating point registers may have different size
in different configurations. Use register file geometry as additional
identifier.
Signed-off-by: Max Filippov
---
target/xtensa/cpu.h | 2 +-
ta
On Wed, Jul 08, 2020 at 09:23:54PM +, Vikram Garhwal wrote:
> Hi Edgar,
> Thanks for reviewing the patch. Please see some comments.
>
> > -Original Message-
> > From: Edgar E. Iglesias
> > Sent: Tuesday, July 7, 2020 5:49 AM
> > To: Vikram Garhwal
> > Cc: qemu-devel@nongnu.org; Franc
On 08/07/20 17:17, Claudio Fontana wrote:
> On 7/8/20 5:05 PM, Paolo Bonzini wrote:
>> On 08/07/20 17:00, Claudio Fontana wrote:
Bisectable, 100% failure rate, etc. :( Can you split the patch in
multiple parts, specifically separating any rename or introducing of
includes from the f
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: cd955761 (
https://gitlab.com/qemu-project/qemu/-/commit/cd9557616fe30a1926a57b516ee2ceb07faf1cb7
)
Commit Message: Merge remote-tr
On Wed, Jul 08, 2020 at 04:06:45PM +0300, Maxim Levitsky wrote:
> On Wed, 2020-07-08 at 14:33 +0200, Gerd Hoffmann wrote:
> > On Mon, Jun 08, 2020 at 12:40:27PM +0300, Maxim Levitsky wrote:
> > > blockdev-amend will be used similiar to blockdev-create
> > > to allow on the fly changes of the struct
pickNaNMulAdd logic on Xtensa is to apply pickNaN to the inputs of the
expression (a * b) + c. However if default NaN is produces as a result
of (a * b) calculation it is not considered when c is NaN.
So with two pickNaN variants there must be two pickNaNMulAdd variants.
In addition the invalid fla
On Tue, Jul 07, 2020 at 06:50:55PM +0100, Peter Maydell wrote:
> On Tue, 7 Jul 2020 at 13:04, Michael S. Tsirkin wrote:
> >
> > On Tue, Jul 07, 2020 at 12:40:38PM +0100, Peter Maydell wrote:
> > > On Sat, 4 Jul 2020 at 19:29, Michael S. Tsirkin wrote:
> > > >
> > > >
> > > > v2 of the pull, fixin
On Fri, Jul 03, 2020 at 08:34:50PM +0200, Philippe Mathieu-Daudé wrote:
> Add an entry to cover firmware.json (see commit 3a0adfc9bf:
> schema that describes the different uses and properties of
> virtual machine firmware).
>
> Cc: Laszlo Ersek
> Cc: Gerd Hoffmann
> Cc: Michael S. Tsirkin
> Cc
Pass float_status structure pointer to the pickNaN so that
machine-specific settings are available to NaN selection code.
Add use_first_nan property to float_status and use it in Xtensa-specific
pickNaN.
Cc: Peter Maydell
Cc: "Alex Bennée"
Reviewed-by: Alex Bennée
Signed-off-by: Max Filippov
-
Daniel P. Berrangé writes:
> Currently we suggest that a filesystem may not support O_DIRECT after
> seeing an EINVAL. Other things can cause EINVAL though, so it is better
> to do an explicit check, and then report a definitive error message.
>
> Signed-off-by: Daniel P. Berrangé
> ---
> util/
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