On 2020/6/28 下午10:47, Peter Xu wrote:
On Sun, Jun 28, 2020 at 03:03:41PM +0800, Jason Wang wrote:
On 2020/6/27 上午5:29, Peter Xu wrote:
Hi, Eugenio,
(CCing Eric, Yan and Michael too)
On Fri, Jun 26, 2020 at 08:41:22AM +0200, Eugenio Pérez wrote:
diff --git a/memory.c b/memory.c
index 2f15a4
Dear Peter Maydell (@pmaydell), is there any update on this bug?
--
You received this bug notification because you are a member of qemu-
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https://bugs.launchpad.net/bugs/1882123
Title:
ARM cpu emulation regression on QEMU 4.2.0
Status in QEMU:
New
Bug
Hi all:
Secure boot for virtual machine NOWADAYS starts from edk2’s vBIOS, which
verifies guest OS’s shim/grub2. Then grub2 verifies guest OS’s kernel.
From the view of the whole complete trust chain, the GUEST part is
disconnected from the HOST part, as the verification of vBIOS is missing
On 2020/6/29 6:51, Alistair Francis wrote:
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell wrote:
On Fri, 26 Jun 2020 at 22:53, Alistair Francis wrote:
The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-t
From: Andrew
Added fix for checksum offload for IPv6 if a backend doesn't
have a virtual header.
This patch is a part of IPv6 fragmentation.
Signed-off-by: Andrew Melnychenko
---
hw/net/net_tx_pkt.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/hw/net/net
From: Andrew
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1708065
Overall, there was an issue that big frames of IPv6 doesn't sent.
With network backend with 'virtual header' - there was an issue
in 'plen' field. Overall, during TSO, 'plen' would be changed,
but with 'vheader' this field
There's nothing wrong with the atomic operation, which
makes sense since it's against a NULL pointer. The
problem that I see is in the unwinding -- the catch
never happens and std::terminate gets called.
There must be some sort of 32-bit TCG error though,
because the same binary works on x86_64 h
On Sun, Jun 28, 2020 at 7:30 AM Peter Maydell wrote:
>
> On Fri, 26 Jun 2020 at 22:53, Alistair Francis
> wrote:
> >
> > The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
> >
> > Merge remote-tracking branch
> > 'remotes/pmaydell/tags/pull-target-arm-20200626' into
FWIW, I cannot reproduce the problem with x86_64 host,
but I can reproduce it on a 32-bit i686 host.
** Changed in: qemu
Status: New => Confirmed
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https://bugs.launchpad.net/bugs/
Remove hard-tabs from palm.c.
Signed-off-by: Peter Maydell
---
hw/arm/palm.c | 64 +--
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index 97ca105d297..569836178f6 100644
--- a/hw/arm/palm.c
+++ b/hw/
Replace the free-floating set of IRQs and palmte_onoff_gpios()
function with a simple QOM device that encapsulates this
behaviour.
This fixes Coverity issue CID 1421944, which points out that
the memory returned by qemu_allocate_irqs() is leaked.
Signed-off-by: Peter Maydell
---
hw/arm/palm.c |
As for spitz and tosa, fix the Coverity issue CID 1421944 which
points out that memory returned from qemu_allocate_irqs() is leaked
by encapsulating the GPIO handling into a simple device.
As with the other series, detabify the file first.
thanks
-- PMM
Peter Maydell (2):
hw/arm/palm.c: Detabif
If a test is unsuccessful, the result is "not ok", which does not match
the regex because it includes a space.
This regex matches both "ok" and "not ok".
Signed-off-by: Havard Skinnemoen
---
tests/Makefile.include | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/Makefil
Currently we have a free-floating set of IRQs and a function
tosa_out_switch() which handle the GPIO lines on the tosa board which
connect to LEDs, and another free-floating IRQ and tosa_reset()
function to handle the GPIO line that resets the system. Encapsulate
this behaviour in a simple QOM dev
Remove the hardcoded tabs from hw/arm/tosa.c. There aren't
many, but since they're all in constant #defines they're not
going to go away with our usual "only when we touch a function"
policy on reformatting.
Signed-off-by: Peter Maydell
---
hw/arm/tosa.c | 44 ++--
This series fixes Coverity issue CID 1421929, which pointed out that
the 'outsignals' in tosa_gpio_setup() were leaked, in the same way
that the equivalent bug for spitz was fixed in the series I posted
earlier: instead of using qemu_allocate_irqs() we create a device
to encapsulate the handling of
The i.MX6UL EVK 14x14 board uses:
- PHY 2 for FEC 1
- PHY 1 for FEC 2
Signed-off-by: Jean-Christophe Dubois
---
hw/arm/mcimx6ul-evk.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 2f845cedfce..9033d3f8f38 100644
--- a/hw/arm/mcimx6ul-ev
Add properties to the i.MX6UL processor to be able to select a
particular PHY on the MDIO bus for each FEC device.
Signed-off-by: Jean-Christophe Dubois
---
hw/arm/fsl-imx6ul.c | 10 ++
include/hw/arm/fsl-imx6ul.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/hw/arm/fs
We need a solution to use an Ethernet PHY that is not the first device
on the MDIO bus (device 0 on MDIO bus).
As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
only one MDIO bus on which the 2 related PHY are connected but at unique
addresses.
Signed-off-by: Jean-Christophe D
The PHY device associated to a specific i.MX Ethernet device is not
necessarily at address 0 on the MDIO bus.
This patch series adds the ability to set the PHY number on the MDIO bus
for any i.MX6UL based board.
Jean-Christophe Dubois (3):
Add a phy-num property to the i.MX FEC emulator
Add
On Sun, Jun 28, 2020 at 7:20 PM Aleksandar Markovic
wrote:
>
> Now, thinking longer about topN scripts, I think one really missing
> thing is number of invocations (or calls, whatever term you prefer)
> for any function in the list. This data must be possible to obtain
> using callgrind_annotate (
In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
pass a pointer to a local struct to another function without
initializing all its fields. This is a real bug:
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
struct into s->config, so any fields we don't initi
I am not sure how it could influence the fact that I experience this bug
and others not necessarily but for what it is worth, I am using gcc
10.0.1 to compile Qemu.
I might try to use a previous version to check if it changes the overall
behavior.
JC
Le 28/06/2020 à 18:32, Jean-Christophe D
On Thu, 2020-06-25 at 14:55 +0200, Max Reitz wrote:
> That the luks driver is present is little indication on whether it is
> actually working. Without the crypto libraries linked in, it does not
> work. So add this function, which tries to create a luks image to see
> whether that actually works
On Fri, 26 Jun 2020, Mark Cave-Ayland wrote:
On 26/06/2020 11:21, BALATON Zoltan wrote:
What about these patches? At least those that are finished (up to patch 9)
could be
merged. I've seen you sent a pull request but not including any of these. Will
this
need another rebase after your patches
OpenBIOS gets RAM size via fw_cfg but rhe original board firmware
detects RAM using SPD data so generate and add SDP eeproms to cover as
much RAM as possible to describe with SPD (this may be less than the
actual ram_size due to SDRAM size constraints).
This patch is more complex as it should be w
This function resets a CPU not the whole machine so reflect that in
its name.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/ppc/mac_oldworld.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
index 4
These functions have a parameter that decides the direction of
transfer but totally confusingly they don't match but inverted sense.
To avoid frequent mistakes when using these functions change
i2c_send_recv to match i2c_start_transfer. Also use bool in
i2c_start_transfer instead of int to match i2
The G3 beige machine has a machine ID register that is accessed by the
firmware to deternine the board config. Add basic emulation of it.
Signed-off-by: BALATON Zoltan
---
v6: Make MemoryRegionOps static const
v4: Move MermoryRegion to MachineState, use constants
hw/ppc/mac.h | 1 +
h
This is not a final, RFC patch attempt to implement i2c bus in CUDA
needed for firmware to access SPD data of installed RAM. The skeleton
is there but actual implementation of I2C commands need to be refined
because I don't know how this is supposed to work. In my understanding
after an I2C command
Add a reset function that maps macio to the address expected by the
firmware of the board at startup.
Signed-off-by: BALATON Zoltan
---
hw/ppc/mac.h | 12
hw/ppc/mac_oldworld.c | 15 ++-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/mac.h
Signed-off-by: BALATON Zoltan
---
hw/pci-host/grackle.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c
index 4b3af0c704..48d11f13ab 100644
--- a/hw/pci-host/grackle.c
+++ b/hw/pci-host/grackle.c
@@ -130,7 +130,7 @@ static void gra
Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Mark Cave-Ayland
---
hw/ppc/mac_oldworld.c | 5 ++---
Latest version of this series with addressing review comments, adding
review tags and tweaks to the WIP CUDA I2C support so with this on top
of Mark's screaper patches (with a small fix) the ROM now plays the
startup sound but then gets confused about some memory addresses. I
don't want to debug th
Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables.
Signed-off-by: BALATON Zoltan
The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to loading a binary image with -bios if
loading ELF image failed. This allows testing emulation with a ROM
image from real hardware as well as using an ELF OpenBIOS image.
Signed-off-by: BALATON Zolta
Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.
Signed-off-by: BALATON Zoltan
---
Unlike mac
пон, 22. јун 2020. у 12:31 Ahmed Karaman
је написао/ла:
>
> Greetings,
>
> Welcome to the TCG Continuous Benchmarking GSoC project!
> This is the first report in a series that will be posted here on the
> mailing list as part of the project.
>
> During the project, multiple Linux profiling tools w
On Sun, 28 Jun 2020 at 17:46, Jean-Christophe DUBOIS
wrote:
>
> Le 28/06/2020 à 16:38, Peter Maydell a écrit :
> > On Sun, 28 Jun 2020 at 11:56, Jean-Christophe DUBOIS
> > wrote:
> >> jcd@jcd-UX305CA:~/Projects/µCOS/work$
> >> ../../qemu/qemu/arm-softmmu/qemu-system-arm -machine mcimx6ul-evk -m
>
By reverting the recent (june 23) commit series on PCA9552 I can run
Qemu again.
Here is the git revert command I did.
jcd@jcd-UX305CA:~/Projects/qemu/qemu$ git revert
8208335b9539e7b5aa4702b36e2f9a8abd704079..586f495b1e78c27e141ff432dd971eb41866fb80
Regards
JC
Le 28/06/2020 à 17:57, Jean-
When ran from valgrind, qemu does not crash but the following output is
returned.
valgrind --track-origins=yes ../../qemu/qemu/arm-softmmu/qemu-system-arm
-machine mcimx6ul-evk -m 128M -display none -serial stdio -kernel ./OS.elf
==77479== Memcheck, a memory error detector
==77479== Copyright
On Thu, 2020-06-25 at 14:55 +0200, Max Reitz wrote:
> Right now, _filter_img_create just filters out everything that looks
> format-dependent, and applies some filename filters. That means that we
> have to add another filter line every time some format gets a new
> creation option. This can be a
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate those instruction which is one of the
(many) reasons why KVM will not even try to do so.
Add support for handling tho
Injecting external data abort through KVM might trigger
an issue on kernels that do not get updated to include the KVM fix.
For those and aarch32 guests, the injected abort gets misconfigured
to be an implementation defined exception. This leads to the guest
repeatedly re-running the faulting instr
On Sun, 28 Jun 2020, BALATON Zoltan wrote:
SCREAMER: ### AUDIO WRITE! 0 / 11104 - 11104
Unassigned mem write f3011190 = 0x900
Unassigned mem write f3011190 = 0xb00
Unassigned mem write f3011190 = 0x900
Unassigned mem write f3011190 = 0x900
U
Some of the ARMv7 & ARMv8 load/store instructions might trigger a data abort
exception with no valid ISS info to be decoded. The lack of decode info
makes it at least tricky to emulate the instruction which is one of the
(many) reasons why KVM will not even try to do so.
So far, if a guest made an
With increasing screamer buffer size (you may want to fix this and
prevent buffer overflows, maybe should allocate it dynamically based on
what the guest programs?):
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 75f1853a7b..05b289e086 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -108,7 +108
Your pipeline has failed.
Project: QEMU ( https://gitlab.com/qemu-project/qemu )
Branch: master ( https://gitlab.com/qemu-project/qemu/-/commits/master )
Commit: e7651153 (
https://gitlab.com/qemu-project/qemu/-/commit/e7651153a8801dad6805d450ea8bef9b46c1adf5
)
Commit Message: Merge remote-tr
On Sun, Jun 28, 2020 at 03:03:41PM +0800, Jason Wang wrote:
>
> On 2020/6/27 上午5:29, Peter Xu wrote:
> > Hi, Eugenio,
> >
> > (CCing Eric, Yan and Michael too)
> >
> > On Fri, Jun 26, 2020 at 08:41:22AM +0200, Eugenio Pérez wrote:
> > > diff --git a/memory.c b/memory.c
> > > index 2f15a4b250..7f
Patchew URL:
https://patchew.org/QEMU/20200628142429.17111-1-peter.mayd...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 00/17] spitz: fix hacks, fix CID 1421913, various cleanups
Type: series
Message-id: 202006281
On Fri, 26 Jun 2020 at 22:53, Alistair Francis wrote:
>
> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26
> 18:22:36 +0100)
>
> are available in the Git rep
On Sun, 28 Jun 2020 at 11:56, Jean-Christophe DUBOIS
wrote:
> Since the last pull I did this week end on the qemu git tree (master
> branch) I am unable to "start" qemu anymore (It was working OK from git
> master previously).
>
> Traces are provided bellow.
>
> Am I the only one to get this behav
The test of the write of the dblac register was testing the old value
instead of the new value. This would accept the write of an invalid value
but subsequently refuse any following valid writes.
Signed-off-by: erik-smit
---
Changes since v1:
Changed %ld to HWADDR_PRIx to fix building on mingw
The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
to cast from an SSISlave* to the instance struct of a subtype of
TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which
have the same effect (by writing the QOM macros if the types were
previously missing them.)
(Th
On Sun, 28 Jun 2020, BALATON Zoltan wrote:
Here it is with --enable-debug and additional screamer debug:
SCREAMER: screamer_read: addr -> 0
SCREAMER: screamer_write: addr val 11
SCREAMER: screamer_control_write: val 17
SCREAMER: basic rate: 44100
DBDMA[10]: writ
The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
usual QOM TYPE and casting macros; provide and use them.
In particular, we can safely use the QOM cast macros instead of
FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
the instance state struct is the first field in it.
Sig
Instead of logging guest accesses to invalid register offsets in this
device using zaurus_printf() (which just prints to stderr), use the
usual qemu_log_mask(LOG_GUEST_ERROR,...).
Since this was the only use of the zaurus_printf() macro outside
spitz.c, we can move the definition of that macro fro
Instead of logging guest accesses to invalid register offsets in the
Spitz flash device with zaurus_printf() (which just prints to stderr),
use the usual qemu_log_mask(LOG_GUEST_ERROR,...).
Signed-off-by: Peter Maydell
---
hw/arm/spitz.c | 12 +++-
1 file changed, 7 insertions(+), 5 dele
Currently we have a free-floating set of IRQs and a function
spitz_out_switch() which handle some miscellaneous GPIO lines for the
spitz board. Encapsulate this behaviour in a simple QOM device.
At this point we can finally remove the 'max' global, because the
ADC battery-temperature value is
Create a header file for the hw/misc/max111x device, in the
usual modern style for QOM devices:
* definition of the TYPE_ constants and macros
* definition of the device's state struct so that it can
be embedded in other structs if desired
* documentation of the interface
This allows us to u
Add some QOM properties to the max111x ADC device to allow the
initial values to be configured. Currently this is done by
board code calling max111x_set_input() after it creates the
device, which doesn't work on system reset.
This requires us to implement a reset method for this device,
so while w
Use the new max111x qdev properties to set the initial input
values rather than calling max111x_set_input(); this means that
on system reset the inputs will correctly return to their initial
values.
Signed-off-by: Peter Maydell
---
hw/arm/spitz.c | 11 +++
1 file changed, 7 insertions(+)
Instead of using printf() for logging guest accesses to invalid
register offsets in the pxa2xx PIC device, use the usual
qemu_log_mask(LOG_GUEST_ERROR,...).
This was the only user of the REG_FMT macro in pxa.h, so we can
remove that.
Signed-off-by: Peter Maydell
---
include/hw/arm/pxa.h | 1 -
Currently the Spitz board uses a nasty hack for the GPIO lines
that pass "bit5" and "power" information to the LCD controller:
the lcdtg realize function sets a global variable to point to
the instance it just realized, and then the functions spitz_bl_power()
and spitz_bl_bit5() use that to find th
Add an ssi_realize_and_unref(), for the benefit of callers
who want to be able to create an SSI device, set QOM properties
on it, and then do the realize-and-unref afterwards.
The API works on the same principle as the recently added
qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.
Sign
For the four Spitz-family machines (akita, borzoi, spitz, terrier)
create a proper abstract class SpitzMachineClass which encapsulates
the common behaviour, rather than having them all derive directly
from TYPE_MACHINE:
* instead of each machine class setting mc->init to a wrapper
function whic
Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
that to spitz_scoop_gpio_setup().
(We'll want to use some of the other fields in SpitzMachineState
in that function in the next commit.)
Signed-off-by: Peter Maydell
---
hw/arm/spitz.c | 34 +++---
1 fil
The max111x ADC device model allows other code to set the level on
the 8 ADC inputs using the max111x_set_input() function. Replace
this with generic qdev GPIO inputs, which also allow inputs to be set
to arbitrary values.
Using GPIO lines will make it easier for board code to wire things
up, so
This series of patches makes various cleanups to the spitz board
family code; the main driver here was fixing the minor Coverity
nit CID 1421913, which is a complaint that the call to
qemu_allocate_irqs() creates memory that is leaked.
We fix this by replacing the free-standing irq array and
callb
The spitz board has been around a long time, and still has a fair number
of hard-coded tab characters in it. We're about to do some work on
this source file, so start out by expanding out the tabs.
This commit is a pure whitespace only change.
Signed-off-by: Peter Maydell
---
Couple of checkpatc
Keep pointers to the MPU and the SSI devices in SpitzMachineState.
We're going to want to make GPIO connections between some of the
SSI devices and the SCPs, so we want to keep hold of a pointer to
those; putting the MPU into the struct allows us to pass just
one thing to spitz_ssp_attach() rather
The max111x is a proper qdev device; we can use dc->vmsd rather than
directly calling vmstate_register().
It's possible that this is a migration compat break, but the only
boards that use this device are the spitz-family ('akita', 'borzoi',
'spitz', 'terrier').
Signed-off-by: Peter Maydell
---
On Sun, Jun 28, 2020 at 2:23 PM Peter Maydell
wrote:
> On Sat, 27 Jun 2020 at 23:05, Michele Denber
> wrote:
> >
> > Well I removed the "static" from the line
> >
> > static int openpty(int *amaster, int *aslave, char *name,
> >struct termios *termp, struct winsize *winp)
> >
Here it is with --enable-debug and additional screamer debug:
SCREAMER: screamer_read: addr -> 0
SCREAMER: screamer_write: addr val 11
SCREAMER: screamer_control_write: val 17
SCREAMER: basic rate: 44100
DBDMA[10]: writel 0x080c <= 0x0010
DBDMA[10
On Sat, 27 Jun 2020 at 20:51, Aleksandar Markovic
wrote:
>
> The following changes since commit 553cf5d7c47bee05a3dec9461c1f8430316d516b:
>
> Merge remote-tracking branch
> 'remotes/pmaydell/tags/pull-target-arm-20200626' into staging (2020-06-26
> 18:22:36 +0100)
>
> are available in the git
On Sat, 27 Jun 2020 at 23:05, Michele Denber wrote:
>
> Well I removed the "static" from the line
>
> static int openpty(int *amaster, int *aslave, char *name,
>struct termios *termp, struct winsize *winp)
>
> in util/qemu-openpty.c. I odn't know if that was the right thing to
This is a non-working RFC patch attempt to implement i2c bus in CUDA
needed for firmware to access SPD data of installed RAM. The skeleton
is there but actual operation fails because I don't know how this is
supposed to work and the i2c bus state becomes invalid quickly. Also
sending back result
On Fri, 26 Jun 2020, Mark Cave-Ayland wrote:
Again I'm wary of adding empty devices here as the main issue around the
screamer
code (and why it has not been submitted upstream) is that it can cause random
hangs
for MacOS on startup. Does it regress any MacOS 9 through 10.5 boot tests?
FWIW I'v
Patchew URL:
https://patchew.org/QEMU/20200628114057.-1-erik.lucas.s...@gmail.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGI
The test of the write of the dblac register was testing the old value
instead of the new value. This would accept the write of an invalid value
but subsequently refuse any following valid writes.
Signed-off-by: erik-smit
---
hw/net/ftgmac100.c | 12 ++--
1 file changed, 6 insertions(+),
Hi, Ping for comments:)
On Thu, 2020-06-11 at 10:47 +0800, Robert Hoo wrote:
> Complement versioned CPU model framework with the ability of marking
> some
> versions deprecated. When that CPU model is chosen, get some warning.
> The
> warning message is customized, e.g. telling in which future QEMU
Now that the implementation of subclusters is complete we can finally
add the necessary options to create and read images with this feature,
which we call "extended L2 entries".
Signed-off-by: Alberto Garcia
Reviewed-by: Eric Blake
---
qapi/block-core.json | 7 +++
block/qcow2.h
This patch adds QCow2SubclusterType, which is the subcluster-level
version of QCow2ClusterType. All QCOW2_SUBCLUSTER_* values have the
the same meaning as their QCOW2_CLUSTER_* equivalents (when they
exist). See below for details and caveats.
In images without extended L2 entries clusters are trea
This works now at the subcluster level and pwrite_zeroes_alignment is
updated accordingly.
qcow2_cluster_zeroize() is turned into qcow2_subcluster_zeroize() with
the following changes:
- The request can now be subcluster-aligned.
- The cluster-aligned body of the request is still zeroized
There are situations in which we want to know how many contiguous
subclusters of the same type there are in a given cluster. This can be
done by simply iterating over the subclusters and repeatedly calling
qcow2_get_subcluster_type() for each one of them.
However once we determined the type of a s
In order to support extended L2 entries some functions of the qcow2
driver need to start dealing with subclusters instead of clusters.
qcow2_get_host_offset() is modified to return the subcluster type
instead of the cluster type, and all callers are updated to replace
all values of QCow2ClusterTyp
This function is only used by qcow2_expand_zero_clusters() to
downgrade a qcow2 image to a previous version. This would require
transforming all extended L2 entries into normal L2 entries but this
is not a simple task and there are no plans to implement this at the
moment.
Signed-off-by: Alberto G
The logic of this function remains pretty much the same, except that
it uses count_contiguous_subclusters(), which combines the logic of
count_contiguous_clusters() / count_contiguous_clusters_unallocated()
and checks individual subclusters.
qcow2_cluster_to_subcluster_type() is not necessary as a
This field allows us to indicate that the L2 metadata update does not
come from a write request with actual data but from a preallocation
request.
For traditional images this does not make any difference, but for
images with extended L2 entries this means that the clusters are
allocated normally i
Two things need to be taken into account here:
1) With full_discard == true the L2 entry must be cleared completely.
This also includes the L2 bitmap if the image has extended L2
entries.
2) With full_discard == false we have to make the discarded cluster
read back as zeroes. With normal
qcow2 images with subclusters have 128-bit L2 entries. The first 64
bits contain the same information as traditional images and the last
64 bits form a bitmap with the status of each individual subcluster.
Because of that we cannot assume that L2 entries are sizeof(uint64_t)
anymore. This function
This patch adds the following new fields to BDRVQcow2State:
- subclusters_per_cluster: Number of subclusters in a cluster
- subcluster_size: The size of each subcluster, in bytes
- subcluster_bits: No. of bits so 1 << subcluster_bits = subcluster_size
Images without subclusters are treated as if
Signed-off-by: Alberto Garcia
---
tests/qemu-iotests/271 | 901 +
tests/qemu-iotests/271.out | 724 +
tests/qemu-iotests/group | 1 +
3 files changed, 1626 insertions(+)
create mode 100755 tests/qemu-iotests/271
create mode
Traditional qcow2 images don't allow preallocation if a backing file
is set. This is because once a cluster is allocated there is no way to
tell that its data should be read from the backing file.
Extended L2 entries have individual allocation bits for each
subcluster, and therefore it is perfectl
The L2 bitmap needs to be updated after each write to indicate what
new subclusters are now allocated. This needs to happen even if the
cluster was already allocated and the L2 entry was otherwise valid.
In some cases however a write operation doesn't need change the L2
bitmap (because all affecte
The QCOW_OFLAG_ZERO bit that indicates that a cluster reads as
zeroes is only used in standard L2 entries. Extended L2 entries use
individual 'all zeroes' bits for each subcluster.
This must be taken into account when updating the L2 entry and also
when deciding that an existing entry does not nee
If an image has subclusters then there are more copy-on-write
scenarios that we need to consider. Let's say we have a write request
from the middle of subcluster #3 until the end of the cluster:
1) If we are writing to a newly allocated cluster then we need
copy-on-write. The previous contents
Hi,
here's the new version of the patches to add subcluster allocation
support to qcow2.
Please refer to the cover letter of the first version for a full
description of the patches:
https://lists.gnu.org/archive/html/qemu-block/2019-10/msg00983.html
The important change from v8 is patch 24.
Extended L2 entries are bigger than normal L2 entries so this has an
impact on the amount of metadata needed for a qcow2 file.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
block/qcow2.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/block/q
The file_cluster_offset field of Qcow2AioTask stores a cluster-aligned
host offset. In practice this is not very useful because all users(*)
of this structure need the final host offset into the cluster, which
they calculate using
host_offset = file_cluster_offset + offset_into_cluster(s, offse
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