On Fri, Jan 17, 2020 at 10:15:52AM +0100, Greg Kurz wrote:
> Most of the option vector helpers have assertions to check their
> arguments aren't null. The guest can provide an arbitrary address
> for the CAS structure that would result in such null arguments.
> Fail CAS with H_PARAMETER and print a
On 1/18/20 12:02 PM, Peter Maydell wrote:
On Sat, 18 Jan 2020 at 15:08, Guenter Roeck wrote:
Do only the pointers have to be in Exynos4210State, or the entire
data structures ? In the armsse code it looks like it is the complete
data structures.
Either works. Embedding the entire data structu
OK, I will modify it.
Due to the mach-virt.ram is sent by the multiRDMA channels instead of the main
channel, it don't to register on the main channel.
It takes a long time to register the mach-virt.ram for VM with large capacity
memory, so we shall try our best not to register it.
Thanks for y
There is a mistake in defining CSR operations for pmpcfg registers.
This patch fixes the bug.
Signed-off-by: Ian Jiang
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..e07b5267be 100644
--- a/targ
From: Philippe Mathieu-Daudé
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compr
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII int
From: Philippe Mathieu-Daudé
We need a function to interrupt interactive consoles.
Example: Interrupt U-Boot to set different environment values.
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Niek Linnenbank
Signed-off-by: Niek Linnenbank
---
tests/acceptance/avocado_qemu/__init__.py | 3
From: Philippe Mathieu-Daudé
Since we are going to re-use the code shared between
wait_for_console_pattern() and exec_command_and_wait_for_pattern(),
extract the common part into a local function.
Signed-off-by: Philippe Mathieu-Daudé
Tested-by: Niek Linnenbank
Signed-off-by: Niek Linnenbank
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The followin
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM
From: Philippe Mathieu-Daudé
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" w
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-bui
From: Philippe Mathieu-Daudé
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The ker
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC b
From: Philippe Mathieu-Daudé
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Sign
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
O
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-
Dear QEMU developers,
Hereby I would like to contribute the following set of patches to QEMU
which add support for the Allwinner H3 System on Chip and the
Orange Pi PC machine. The following features and devices are supported:
* SMP (Quad Core Cortex A7)
* Generic Interrupt Controller configura
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank
---
include/hw/arm/allwi
Hi Philippe,
For some reason, I can't apply this patch with git am:
Applying: .travis.yml: Allow untrusted code and large files
error: patch failed: .travis.yml:260
error: .travis.yml: patch does not apply
Patch failed at 0001 .travis.yml: Allow untrusted code and large files
Use 'git am --show-c
On Sat, Jan 18, 2020 at 8:16 PM Philippe Mathieu-Daudé
wrote:
> We need a function to interrupt interactive consoles.
>
> Example: Interrupt U-Boot to set different environment values.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
Tested-by: Niek Linnenbank
> ---
> tests/acceptance/avocado_qemu
On Sat, Jan 18, 2020 at 8:16 PM Philippe Mathieu-Daudé
wrote:
> Since we are going to re-use the code shared between
> wait_for_console_pattern() and exec_command_and_wait_for_pattern(),
> extract the common part into a local function.
>
> Signed-off-by: Philippe Mathieu-Daudé
>
Tested-by: Niek
Hi Philippe,
On Sat, Jan 18, 2020 at 8:16 PM Philippe Mathieu-Daudé
wrote:
> This test boots U-Boot then NetBSD (stored on a SD card) on
> a OrangePi PC board.
>
> As it requires ~1.3GB of storage, it is disabled by default.
>
> U-Boot is built by the Debian project [1], and the SD card image
>
On Sun, 19 Jan 2020, BALATON Zoltan wrote:
On Sat, 18 Jan 2020, Peter Maydell wrote:
On Sat, 18 Jan 2020 at 22:41, BALATON Zoltan wrote:
I'm getting errors about missing headers in qapi/* and build fails on
current master.
I've tried bisecting it which lead to commit 3e7fb5811b where I get:
On Sat, 18 Jan 2020, Peter Maydell wrote:
On Sat, 18 Jan 2020 at 22:41, BALATON Zoltan wrote:
I'm getting errors about missing headers in qapi/* and build fails on
current master.
I've tried bisecting it which lead to commit 3e7fb5811b where I get:
CC qapi/qapi-types-audio.o
cc: error
Hi Philippe,
On Sat, Jan 18, 2020 at 4:37 PM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 1/13/20 8:18 PM, Niek Linnenbank wrote:
> > Hi,
> >
> > Just a friendly reminder for review of this patch and the others in this
> > series
> > that don't yet have a reviewed-by tag :-)
>
> You are right
On Sat, 18 Jan 2020 at 22:41, BALATON Zoltan wrote:
> I'm getting errors about missing headers in qapi/* and build fails on
> current master.
>
> I've tried bisecting it which lead to commit 3e7fb5811b where I get:
>
>CC qapi/qapi-types-audio.o
> cc: error: qapi/qapi-types-audio.c: No suc
On Sat, Jan 18, 2020 at 12:22 PM Philippe Mathieu-Daudé
wrote:
> On 1/8/20 9:00 PM, Niek Linnenbank wrote:
> > From: Philippe Mathieu-Daudé
> >
> > This test boots a Linux kernel on a OrangePi PC board and verify
> > the serial output is working.
> >
> > The kernel image and DeviceTree blob are
Hi Philippe,
On Sat, Jan 18, 2020 at 4:05 PM Philippe Mathieu-Daudé
wrote:
> Hi Niek,
>
> On 1/14/20 11:57 PM, Niek Linnenbank wrote:
> > On Tue, Jan 14, 2020 at 11:52 PM Niek Linnenbank
> > mailto:nieklinnenb...@gmail.com>> wrote:
> >
> > Hi Philippe,
> >
> > On Mon, Jan 13, 2020 at 11:
Hello,
I'm getting errors about missing headers in qapi/* and build fails on
current master.
I've tried bisecting it which lead to commit 3e7fb5811b where I get:
CC qapi/qapi-types-audio.o
cc: error: qapi/qapi-types-audio.c: No such file or directory
cc: fatal error: no input files
(T
Hi Philippe,
On Sat, Jan 18, 2020 at 10:38 AM Philippe Mathieu-Daudé
wrote:
> On 1/8/20 9:00 PM, Niek Linnenbank wrote:
> > The Xunlong Orange Pi PC machine is a functional ARM machine
> > based on the Allwinner H3 System-on-Chip. It supports mainline
> > Linux, U-Boot, NetBSD and is covered by
On Sat, Jan 18, 2020 at 10:09 AM Philippe Mathieu-Daudé
wrote:
> On 1/15/20 12:10 AM, Niek Linnenbank wrote:
> > On Tue, Jan 14, 2020 at 12:28 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> > On 1/8/20 9:00 PM, Niek Linnenbank wrote:
> > > A real Allwinner H3 SoC c
On Sat, Jan 18, 2020 at 10:06 AM Philippe Mathieu-Daudé
wrote:
> On 1/15/20 12:04 AM, Niek Linnenbank wrote:
> > On Tue, Jan 14, 2020 at 12:14 AM Philippe Mathieu-Daudé
> > mailto:phi...@redhat.com>> wrote:
> >
> > On 1/8/20 9:00 PM, Niek Linnenbank wrote:
> > > Various Allwinner System
On 18/01/20 17:23, Philippe Mathieu-Daudé wrote:
> When adding new devices implementing QOM interfaces, we might
> forgot to add the Kconfig dependency that pulls the required
> objects in when building.
>
> Since QOM dependencies are resolved at runtime, we don't get any
> link-time failures, and
On 14/01/20 03:31, zhenwei pi wrote:
> +# @info: information about a panic (since 2.9)
Removed this "since 2.9" and queued both patches, thanks.
Paolo
On 14/01/20 03:31, zhenwei pi wrote:
> Add bit 1 for pvpanic. This bit means that guest hits a panic, but
> guest wants to handle error by itself. Typical case: Linux guest runs
> kdump in panic. It will help us to separate the abnormal reboot from
> normal operation.
>
> Signed-off-by: zhenwei pi
On 13/01/20 15:01, Markus Armbruster wrote:
> Philippe Mathieu-Daudé writes:
>
>> When configured with --without-default-devices and setting
>> MC146818RTC=n, the build fails:
>>
>> LINKx86_64-softmmu/qemu-system-x86_64
>> /usr/bin/ld: qapi/qapi-commands-misc-target.o: in function
>> `
On 04/01/20 22:16, Philippe Mathieu-Daudé wrote:
> 1/ the Radeon chip is soldered on the motherboard,
>
> 2/ the default BIOS expects the Radeon chip to be
> unconditionally present,
>
> I insist this patch is incorrect for the particular case of the
> Fuloong2e board. I plan to revert it when
On Sat, 18 Jan 2020 at 15:08, Guenter Roeck wrote:
> Do only the pointers have to be in Exynos4210State, or the entire
> data structures ? In the armsse code it looks like it is the complete
> data structures.
Either works. Embedding the entire data structure is the more
"modern" approach, but we
On 18/12/19 07:05, Markus Armbruster wrote:
> "Chubb, Peter (Data61, Kensington NSW)"
> writes:
>
>>> "Philippe" == Philippe Mathieu-Daudé writes:
>>
>> Philippe> Fix some trivial warnings when building with -O3.
>>
>> For compatibility with lint and other older checkers, it'd be good to kee
Include AVR maintaners in MAINTAINERS file
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 21 +
1 file changed, 21 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55d3642e6c..c70d77b1ae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -163,6 +163,15 @@ S: Maintained
On 16/12/19 16:01, Greg Kurz wrote:
> Each cpu subclass overloads the reset method of its parent class with
> its own. But since it needs to call the parent method as well, it keeps
> a parent_reset pointer to do so. This causes the same not very explicit
> boiler plate to be duplicated all around
Print out 'T' through serial port
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Acked-by: Thomas Huth
tests/Makefile.include
---
tests/qtest/boot-serial-test.c | 10 ++
tests/qtest/Makefile.include | 2 ++
2 files changed, 12 i
Make AVR support buildable
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
configure | 7 +++
default-configs/avr-softmmu.mak | 5 +
target/avr/Makefile.objs| 34 +
3 fi
Add AVR related definitions into QEMU
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
include/disas/dis-asm.h
---
qapi/machine.json | 3 ++-
include/disas/dis-asm.h| 19 +++
include/sysemu/arch_init.h | 1 +
arch_
The test is based on
https://github.com/seharris/qemu-avr-tests/tree/master/free-rtos/Demo
demo which. If working correctly, prints 'ABCDEFGHIJKLMNOPQRSTUVWX' out.
it also demostrates that timer and IRQ are working
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Phil
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
---
qemu-doc.texi | 51 +++
1 file changed, 51 insertions(+)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 39f950471f..515aacfae9 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -1741,6 +1741,7 @@ differences are
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Aleksandar Markovic
---
tests/qtest/machine-none-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
index 5953d31755..3e5c74e73e 100644
--- a/te
This is a simple device of just one register, whenver this register is
written it calls qemu_set_irq function for each of 8 bits/IRQs..
It is used to implement AVR Power Reduction
Signed-off-by: Michael Rolnik
---
include/hw/misc/avr_mask.h | 47
hw/misc/avr_mask.c | 11
This includes:
- LSR, ROR
- ASR
- SWAP
- SBI, CBI
- BST, BLD
- BSET, BCLR
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 241 +
target/avr/insn.decode | 14 +++
2 files changed, 255 in
Provide function disassembles executed instruction when `-d in_asm` is
provided
Example:
`./avr-softmmu/qemu-system-avr -bios free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf
-d in_asm` will produce something like the following
```
...
IN:
0x014a: CALL 0x3808
IN: main
0x
These were designed to facilitate testing but should provide enough function to
be useful in other contexts.
Only a subset of the functions of each peripheral is implemented, mainly due to
the lack of a standard way to handle electrical connections (like GPIO pins).
Signed-off-by: Sarah Harris
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 533 ++
Co-developed-by: Richard Henderson
Co-developed-by: Michael Rolnik
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 234 +
1 file changed, 234 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/tr
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 751 +
Signed-off-by: Michael Rolnik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
---
target/avr/translate.c | 172 +
1 file changed, 172 insertions(+)
create mode 100644 target/avr/translate.c
diff --git a/target/avr/translate.c b/tar
This includes:
- BREAK
- NOP
- SLEEP
- WDR
Signed-off-by: Michael Rolnik
---
target/avr/translate.c | 68 ++
target/avr/insn.decode | 9 ++
2 files changed, 77 insertions(+)
diff --git a/target/avr/translate.c b/target/avr/translate.c
Stubs for unimplemented instructions and helpers for instructions that need to
interact with QEMU.
SPM and WDR are unimplemented because they require emulation of complex
peripherals.
The implementation of SLEEP is very limited due to the lack of peripherals to
generate wake interrupts.
Memory a
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik
Tested-by: Philippe Mathieu-Daudé
---
tar
A simple board setup that configures an AVR CPU to run a given firmware image.
This is all that's useful to implement without peripheral emulation as AVR CPUs
include a lot of on-board peripherals.
NOTE: this is not a real board
NOTE: it's used for CPU testing
Signed-off-by: Michael Rol
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet
This series add a test on the OrangePi PC for:
- SD Card booting
- U-boot & UART
- NetBSD 9
I simply followed Niek description in docs/orangepi.rst:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
The sdcard image is big, but the test runs very quick (1min),
even on Travis CI: h
This includes:
- CPU data structures
- object model classes and functions
- migration functions
- GDB hooks
Co-developed-by: Michael Rolnik
Co-developed-by: Sarah Harris
Signed-off-by: Michael Rolnik
Signed-off-by: Sarah Harris
Signed-off-by: Michael Rolnik
Acked-by: Igor Mammedov
Tested-by:
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compressed SD card image is download
We need a function to interrupt interactive consoles.
Example: Interrupt U-Boot to set different environment values.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 32 +--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/t
Since we are going to re-use the code shared between
wait_for_console_pattern() and exec_command_and_wait_for_pattern(),
extract the common part into a local function.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/acceptance/avocado_qemu/__init__.py | 31 +--
1 file changed
As Travis CI runs our tests in a disposable environment, we don't
care much if the binaries are trusted. The more we test the better.
Also, as of this commmit, the smallest available announced [1] is
"approx 18GB", plenty of space to run our acceptance tests.
Enable the proper environment variabl
This replaces all remaining instances in the qcow2 code.
Signed-off-by: Alberto Garcia
---
block/qcow2.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/block/qcow2.c b/block/qcow2.c
index a6b0d4ee1d..6cc13e388c 100644
--- a/block/qcow2.c
+++ b/block/qcow2.c
@@ -3273,
The L1 table is read from disk using the byte-based bdrv_pread() and
is never accessed beyond its last element, so there's no need to
allocate more memory than that.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Reitz
---
block/qcow2-cluster.c | 5 ++---
block/qcow2-refcount.c | 2 +-
block/q
When updating an L1 entry the qcow2 driver writes a (512-byte) sector
worth of data to avoid a read-modify-write cycle. Instead of always
writing 512 bytes we should follow the alignment requirements of the
storage backend.
(the only exception is when the alignment is larger than the cluster
size
qcow2_alloc_cluster_offset() and qcow2_get_cluster_offset() always
return offsets that are cluster-aligned so don't just check that they
are sector-aligned.
The check in qcow2_co_preadv_task() is also replaced by an assertion
for the same reason.
Signed-off-by: Alberto Garcia
Reviewed-by: Max Re
This series gets rid of all the remaining instances of hardcoded
sector sizes in the qcow2 code and adds a check for images whose
virtual size is not a multiple of the sector size.
See the individual patches for details.
Berto
v3:
- Patch 2: Use offset_into_cluster() instead of QEMU_IS_ALIGNED
-
qemu-img's convert_co_copy_range() operates at the sector level and
block_copy() operates at the cluster level so this condition is always
true, but it is not necessary to restrict this here, so let's leave it
to the driver implementation return an error if there is any.
Signed-off-by: Alberto Gar
On Tue 14 Jan 2020 03:15:48 PM CET, Max Reitz wrote:
>> @@ -3836,7 +3837,7 @@ qcow2_co_copy_range_from(BlockDriverState *bs,
>> case QCOW2_CLUSTER_NORMAL:
>> child = s->data_file;
>> copy_offset += offset_into_cluster(s, src_offset);
>> -if ((copy_off
The driver already implements a receive FIFO, but it does not
handle receive FIFO trigger levels and timeout. Implement the
missing functionality.
Signed-off-by: Guenter Roeck
---
v2: Call exynos4210_uart_rx_timeout_set() from new post_load function
to set the receive timeout timer.
Add t
To support receive DMA, we need to inform the DMA controller if receive data
is available. Otherwise the DMA controller keeps requesting data, causing
receive errors.
Implement this using an interrupt line. The instantiating code then needs
to connect the interrupt with the matching DMA controller
Replace debug code with tracing to aid debugging.
Reviewed-by: Peter Maydell
Signed-off-by: Guenter Roeck
---
v2: Added Reviewed-by: tag
hw/char/exynos4210_uart.c | 96 ---
hw/char/trace-events | 17 +++
2 files changed, 47 insertions(+), 66 deletio
The Exynos4210 serial driver uses an interrupt line to signal if receive
data is available. Connect that interrupt with the DMA controller's
'peripheral busy' gpio pin to stop the DMA if there is no more receive
data available. Without this patch, receive DMA runs wild and fills the
entire receive
First parameter to exynos4210_get_irq() is not the SPI port number,
but the interrupt group number. Interrupt groups are 20 for mdma
and 21 for pdma. Interrupts are not inverted. Controllers support 32
events (pdma) or 31 events (mdma). Events must all be routed to a single
interrupt line. Set othe
After restoring a VM, serial parameters need to be updated to reflect
restored register values. Implement a post_load function to handle this
situation.
Signed-off-by: Guenter Roeck
---
v4: Additional patch to implement post-load functionality
in exynos uart driver. Required for next patch in
Replace debug logging code with tracing.
Signed-off-by: Guenter Roeck
---
v2: Make call to pl330_hexdump() conditional
hw/dma/pl330.c | 88 -
hw/dma/trace-events | 24 +
2 files changed, 72 insertions(+), 40 deletions(-)
diff --git a
Commit 59520dc65e ("hw/arm/exynos4210: Add DMA support for the Exynos4210")
introduced DMA support for Exynos4210. Unfortunately, it never really
worked. DMA interrupt line and polarity was wrong, and the serial port
needs extra code to support DMA. This patch series fixes the problem.
The series
When adding new devices implementing QOM interfaces, we might
forgot to add the Kconfig dependency that pulls the required
objects in when building.
Since QOM dependencies are resolved at runtime, we don't get any
link-time failures, and QEMU aborts while starting:
$ qemu ...
Segmentation fau
On Thu, Dec 12, 2019 at 04:37:57PM +, Dr. David Alan Gilbert (git) wrote:
> From: Miklos Szeredi
>
> We have two operations that cannot be done race-free on a symlink in
> certain cases: utimes and link.
>
> Add racy fallback for these if the race-free method doesn't work. We do
> our best
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated
Hi Niek,
On 1/13/20 8:18 PM, Niek Linnenbank wrote:
Hi,
Just a friendly reminder for review of this patch and the others in this
series
that don't yet have a reviewed-by tag :-)
You are right to ping the list after a week.
Cc'ing Damien for this particular patch, he might have good advises
Cc'ing Corey/David for good advices about using UUID.
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using
Cc'ing Igor and Alex for this one.
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capaci
Cc'ing the maintainers, please Cc them on v4.
On 1/8/20 9:00 PM, Niek Linnenbank wrote:
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A
On 1/17/20 10:44 AM, Peter Maydell wrote:
On Fri, 17 Jan 2020 at 18:29, Guenter Roeck wrote:
[ ... ]
Rather than having the uart and pl330 pointers be locals,
they should be fields in Exynos4210State. (Otherwise technically
we leak them, though this is unnoticeable in practice because there's
Hi Niek,
On 1/14/20 11:57 PM, Niek Linnenbank wrote:
On Tue, Jan 14, 2020 at 11:52 PM Niek Linnenbank
mailto:nieklinnenb...@gmail.com>> wrote:
Hi Philippe,
On Mon, Jan 13, 2020 at 11:57 PM Philippe Mathieu-Daudé
mailto:phi...@redhat.com>> wrote:
On 1/8/20 9:00 PM, Niek Li
Most of these developers have the Signed-off-by tag properly
written, but not the author/committer name. Fix this.
Also we incorrectly wrote Arei Gonglei name, update and reorder.
The committer name/email is displayed when using:
$ git log --format=fuller
(which can be set in git-config settin
On 1/18/20 3:06 PM, Philippe Mathieu-Daudé wrote:
In some configuration (linux-user, tools) we can ignore building
various objects (and the libfdt).
Tested with all the combinations of --[enable|disable]-tools,
--[enable|disable]-user and --[enable|disable]-system using the
following commands (s
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