On Thu, 28 Nov 2019 19:38:00 +0100
Laszlo Ersek wrote:
> Hi Cornelia,
>
> On 11/28/19 19:11, Cornelia Huck wrote:
> > The Posix implementation of guest-set-time invokes hwclock to
> > set/retrieve the time to/from the hardware clock. If hwclock
> > is not available, the user is currently informe
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Before using hmat-cache option, enable HMAT with -machine hmat=on.
Acked-by
On Thu, Nov 28, 2019 at 04:17:16PM +, Marc Zyngier wrote:
> HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
> CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
> completely ignores it, making impossible for hypervisors to
Nit: "making it impossible"
> virtual
On Tue, 12 Nov 2019 11:48:11 +0100
Cornelia Huck wrote:
> Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
>
> For i440fx and q35, unversioned cpu models are still translated
> to -v1; I'll leave changing this (if desired) to the respective
> maintainers.
>
> Signed-off-by: Cornelia Huck
On 28.11.19 16:05, Peter Maydell wrote:
> On Thu, 28 Nov 2019 at 12:48, Christian Borntraeger
> wrote:
>>
>>
>>
>> On 28.11.19 13:45, Cornelia Huck wrote:
>>> On Thu, 28 Nov 2019 13:35:29 +0100
>>> Christian Borntraeger wrote:
>>>
Ack.
Conny, I think this would be really nice to
Hi
On Fri, Nov 29, 2019 at 11:03 AM Gerd Hoffmann wrote:
>
> On Thu, Nov 28, 2019 at 06:15:16PM +0400, Marc-André Lureau wrote:
> > Hi,
> >
> > Setting up shared memory for vhost-user is a bit complicated from
> > command line, as it requires NUMA setup such as: m 4G -object
> > memory-backend-fi
On Thu, 28 Nov 2019 17:38:11 -0300
Eduardo Habkost wrote:
> On Thu, Nov 28, 2019 at 06:37:06PM +0100, Cornelia Huck wrote:
> > On Tue, 12 Nov 2019 11:48:11 +0100
> > Cornelia Huck wrote:
> >
> > > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
> > >
> > > For i440fx and q35, unversion
From: PanNengyuan
The BDRVNBDState cleanup code is common in two places, add
nbd_free_bdrvstate_prop() function to do these cleanups (suggested by
Stefano Garzarella).
Signed-off-by: PanNengyuan
---
block/nbd.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
di
From: PanNengyuan
In currently implementation there will be a memory leak when
nbd_client_connect() returns error status. Here is an easy way to
reproduce:
1. run qemu-iotests as follow and check the result with asan:
./check -raw 143
Following is the asan output backtrack:
Direct leak of 4
On Thu, Nov 28, 2019 at 06:15:16PM +0400, Marc-André Lureau wrote:
> Hi,
>
> Setting up shared memory for vhost-user is a bit complicated from
> command line, as it requires NUMA setup such as: m 4G -object
> memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on -numa
> node,memdev=mem.
>
Hi folks,
Right now some smbios fields are hard coded (like CPU nominal
frequency), and some can be opted in, but there is no feasible way to
present real backend hardware information to the front. In some
scenario, the users of virtual machines may not be happy to see an
unknown CPU model an
Vladimir Sementsov-Ogievskiy writes:
> No reason for local_err here, use errp directly instead.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Markus Armbruster
Vladimir Sementsov-Ogievskiy writes:
> No reason for local_err here, use errp directly instead.
Related: "[PATCH v6] hw/vfio/ap: drop local_err from vfio_ap_realize".
I'm surprised it's just two. Did you search for the anti-pattern
systematically?
> Signed-off-by: Vladimir Sementsov-Ogievskiy
Vladimir Sementsov-Ogievskiy writes:
> Rename Error ** parameter in check_only_migratable to common errp.
>
> In device_set_realized:
>
> - Move "if (local_err != NULL)" closer to error setters.
>
> - Drop 'Error **local_errp': it doesn't save any LoCs, but it's very
>unusual.
>
> Signed-of
Vladimir Sementsov-Ogievskiy writes:
> We don't need Error **, as all callers pass local Error object, which
> isn't used after the call, or NULL. Use Error * instead.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> ---
> ui/vnc.h | 2 +-
> ui/vnc.c | 20 +++-
> 2 files chang
Vladimir Sementsov-Ogievskiy writes:
> We don't need Error **, as all callers pass local Error object, which
> isn't used after the call. Use Error * instead.
>
> Signed-off-by: Vladimir Sementsov-Ogievskiy
> Acked-by: Dr. David Alan Gilbert
Reviewed-by: Markus Armbruster
Patchew URL:
https://patchew.org/QEMU/20191128141518.628245-1-marcandre.lur...@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH 0/2] RFC: add -mem-shared option
Type: series
Message-id: 20191128141518.628245-1-marcand
PAPR allows the interrupt controller used on a POWER9 machine (XICS or
XIVE) to be selected by the guest operating system, by using the
ibm,client-architecture-support (CAS) feature negotiation call.
Currently, if the guest selects an interrupt controller different from the
one selected at initial
spapr_h_cas_compose_response() handles the last piece of the PAPR feature
negotiation process invoked via the ibm,client-architecture-support OF
call. Its only caller is h_client_architecture_support() which handles
most of the rest of that process.
I believe it was place in a separate file origi
spapr_ovec_diff(ov, old, new) has somewhat complex semantics. ov is set
to those bits which are in new but not old, and it returns as a boolean
whether or not there are any bits in old but not new.
It turns out that both callers only care about the second, not the first.
This is basically equival
This series contains several cleanups to the handling of the
ibm,client-architecture-support firmware call used for boot time
feature negotiation between the guest OS and the firmware &
hypervisor.
Mostly it's just internal polish, but one significant user visible
change is that we no longer gener
Previously, spapr_build_fdt() constructed the device tree in a fixed
buffer of size FDT_MAX_SIZE. This is a bit inflexible, but more
importantly it's awkward for the case where we use it during CAS. In
that case the guest firmware supplies a buffer and we have to
awkwardly check that what we gene
Patchew URL:
https://patchew.org/QEMU/20191128141518.628245-1-marcandre.lur...@redhat.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT
On 11/28/2019 7:53 PM, Thomas Huth wrote:
On 28/11/2019 12.49, Markus Armbruster wrote:
Tao Xu writes:
Check configuring HMAT usecase
Reviewed-by: Igor Mammedov
Suggested-by: Igor Mammedov
Signed-off-by: Tao Xu
---
Changes in v19:
- Add some fail cases for hmat-cache when level=0
Hi David, Zhang,
Thanks for replying my question.
We know why will occur this issue.
As you said, the COLO VM's network needs
colo-proxy to control packets, so the guest's
interface should set the filter to solve the problem.
But we found another question, when we set the
fault-tolerance feature
On 11/28/2019 7:50 PM, Markus Armbruster wrote:
Tao Xu writes:
From: Liu Jingqi
Add -numa hmat-lb option to provide System Locality Latency and
Bandwidth Information. These memory attributes help to build
System Locality Latency and Bandwidth Information Structure(s)
in ACPI Heterogeneous Me
Patchew URL: https://patchew.org/QEMU/20191128082109.30081-1-tao3...@intel.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#
On 11/28/2019 7:50 PM, Markus Armbruster wrote:
Tao Xu writes:
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in ACPI Heterogeneous Memory Attribute Table (HMAT).
Before u
On Thu, Nov 28, 2019 at 02:46:55PM +0100, Cédric Le Goater wrote:
> From: Suraj Jitindar Singh
>
> The Processor Utilisation of Resources Register (PURR) and Scaled
> Processor Utilisation of Resources Register (SPURR) provide an estimate
> of the resources used by the thread, present on POWER7 a
On Thu, Nov 28, 2019 at 02:46:54PM +0100, Cédric Le Goater wrote:
> From: Suraj Jitindar Singh
>
> The virtual timebase register (VTB) is a 64-bit register which
> increments at the same rate as the timebase register, present on POWER8
> and later processors.
>
> The register is able to be read/
Move the calculation of the Real Mode Area (RMA) size into a helper
function. While we're there clean it up and correct it in a few ways:
* Add comments making it clearer where the various constraints come from
* Remove a pointless check that the RMA fits within Node 0 (we've just
clamped
On 11/28/2019 9:57 PM, Igor Mammedov wrote:
On Thu, 28 Nov 2019 12:50:36 +0100
Markus Armbruster wrote:
Tao Xu writes:
From: Liu Jingqi
Add -numa hmat-cache option to provide Memory Side Cache Information.
These memory attributes help to build Memory Side Cache Information
Structure(s) in
This function calculates the maximum size of the RMA as implied by the
host's page size of structure of the VRMA (there are a number of other
constraints on the RMA size which will supersede this one in many
circumstances).
The current interface takes the current RMA size estimate, and clamps it
t
The Real Mode Area (RMA) needs to fit within Node 0 in NUMA configurations.
We use a helper function spapr_node0_size() to calculate this.
But that function doesn't actually get the size of Node 0, it gets the
minimum size of all nodes, ever since b082d65a300 "spapr: Add a helper for
node0_size ca
PAPR guests have a certain "Real Mode Area" - a subsection of memory
which can be accessed when in guest real mode (that is, with the MMU
"off" from the guest point of view). This is advertised to the guest
in the device tree.
We want to make the RMA as large as we can, to allow for flexibility
i
The Real Mode Area (RMA) is the part of memory which a guest can access
when in real (MMU off) mode. Of course, for a guest under KVM, the MMU
isn't really turned off, it's just in a special translation mode - Virtual
Real Mode Area (VRMA) - which looks like real mode in guest mode.
The mechanics
On 2019/11/28 21:36, Stefano Garzarella wrote:
> On Thu, Nov 28, 2019 at 08:09:31PM +0800, pannengy...@huawei.com wrote:
>> From: PanNengyuan
>>
>> In currently implementation there will be a memory leak when
>> nbd_client_connect() returns error status. Here is an easy way to
>> reproduce:
>>
>>
Ping?
Yu-Chen Lin 於 2019年11月23日 週六 11:43 寫道：
> noVNC doesn't use 'binary' protocol by default after
> commit c912230309806aacbae4295faf7ad6406da97617.
>
> It will cause qemu return 400 when handshaking.
>
> To overcome this problem and remain compatibility of
> older noVNC client.
>
> We treat '
Patchew URL:
https://patchew.org/QEMU/1574935984-16910-1-git-send-email-pmo...@linux.ibm.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v1 0/1] s390x: protvirt: SCLP interpretation
Type: series
Message-id: 1574935984-16910
On Thu, 28 Nov 2019, at 19:16, Cédric Le Goater wrote:
> On 28/11/2019 06:45, Andrew Jeffery wrote:
> > Prepare for SoCs such as the ASPEED AST2600 whose firmware configures
> > CNTFRQ to values significantly larger than the static 62.5MHz value
> > currently derived from GTIMER_SCALE. As the OS
On Thu, Nov 28, 2019 at 06:37:06PM +0100, Cornelia Huck wrote:
> On Tue, 12 Nov 2019 11:48:11 +0100
> Cornelia Huck wrote:
>
> > Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
> >
> > For i440fx and q35, unversioned cpu models are still translated
> > to -v1; I'll leave changing this (if
Hi
On Thu, Nov 28, 2019 at 8:48 PM Felipe Franciosi wrote:
>
> Traditionally, the uint-specific property helpers only offer getters.
> When adding object (or class) uint types, one must therefore use the
> generic property helper if a setter is needed (and probably duplicate
> some code writing t
On 11/27/19 6:52 PM, Michael Rolnik wrote:
Include AVR maintaners in MAINTAINERS file
Signed-off-by: Michael Rolnik
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5e5e3e52d6..d7bfb62791 100644
--- a/MAINTAINERS
+++ b/MAINTAINE
On Wed, Nov 27, 2019 at 09:14:01AM +, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@redhat.com) wrote:
On 11/26/19 10:19 AM, no-re...@patchew.org wrote:
> Patchew URL:
https://patchew.org/QEMU/20191126085936.1689-1-pbonz...@redhat.com/
>
> This series failed the docker-quic
It is a pain to re-compile when you need to debug and tracepoints are
a fairly low impact way to instrument QEMU.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 51 +++--
linux-user/trace-events | 1 +
2 files changed, 30 insertions(+), 22 deletions
Convert the final bit of DEBUG_MMAP to a tracepoint and remove the
last remanents of the #ifdef hackery.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 9 ++---
linux-user/trace-events | 1 +
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/linux-user/mmap.c b/linux-u
Vladimir Sementsov-Ogievskiy writes:
> 28.11.2019 17:23, Markus Armbruster wrote:
>> Vladimir Sementsov-Ogievskiy writes:
>>
>>> Error **errp is almost always OUT-argument: it's assumed to be NULL, or
>>> pointer to NULL-initialized pointer, or pointer to error_abort or
>>> error_fatal, for cal
Am 28.11.19 um 22:06 schrieb Stefan Weil:
> Am 28.11.19 um 16:35 schrieb Thomas Huth:
>
>> So far we only have compile coverage for tci. But since commit
>> 2f160e0f9797c7522bfd0d09218d0c9340a5137c ("tci: Add implementation
>> for INDEX_op_ld16u_i64") has been included now, we can also run the
>>
Hi,
While debugging some wierd ELF loading bugs I realised our mmap debug
code could do with a little clean-up so I removed the DEBUG_MMAP in
favour of some tracepoints and extending the information that -d page
gives you.
Alex Bennée (5):
linux-user: convert target_mprotect debug to tracepoint
On 11/28/19 4:35 PM, Thomas Huth wrote:
It's now possible to run some TCG-based tests with our Tiny Code
Generator Interpreter (TCI), too. These two patches enable the
testing on Travis.
Alex Bennée (1):
configure: allow disable of cross compilation containers
Thomas Huth (1):
travis.yml:
It is a pain to re-compile when you need to debug and tracepoints are
a fairly low impact way to instrument QEMU.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 17 +
linux-user/trace-events | 3 +++
2 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/linux
Am 28.11.19 um 16:35 schrieb Thomas Huth:
> So far we only have compile coverage for tci. But since commit
> 2f160e0f9797c7522bfd0d09218d0c9340a5137c ("tci: Add implementation
> for INDEX_op_ld16u_i64") has been included now, we can also run the
> "tcg" and "qtest" tests with tci, so let's enable
Hi,
We seem to have a bit of a mess with libcap and libcap-ng; and I'm not
sure if we should try and untangle it.
a) Our configure script has tests for both libcap and libcap-ng
for libcap it says $cap, for libcap-ng it says $cap_ng (ok)
If $cap is set - nothing happens?
If $cap_ng is set
Patchew URL:
https://patchew.org/QEMU/20191128064350.20727-1-aaron.zakh...@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGI
Am 28.11.19 um 16:35 schrieb Thomas Huth:
> From: Alex Bennée
>
> Our docker infrastructure isn't quite as multiarch as we would wish so
> lets allow the user to disable it if they want. This will allow us to
s/lets/let's/ ?
Otherwise fine, thank you.
Reviewed-by: Stefan Weil
Hi
On Thu, Nov 28, 2019 at 9:25 PM Igor Mammedov wrote:
>
> On Thu, 28 Nov 2019 18:15:18 +0400
> Marc-André Lureau wrote:
>
> > Add an option to simplify shared memory / vhost-user setup.
> >
> > Currently, using vhost-user requires NUMA setup such as:
> > -m 4G -object memory-backend-file,id=me
On 11/28/19 5:45 PM, Cornelia Huck wrote:
> On Thu, 28 Nov 2019 17:38:19 +0100
> Janosch Frank wrote:
>
>> On 11/21/19 4:11 PM, Thomas Huth wrote:
>>> On 20/11/2019 12.43, Janosch Frank wrote:
Secure guests no longer intercept with code 4 for an instruction
interception. Instead they
* Marc-André Lureau (marcandre.lur...@redhat.com) wrote:
> Hi,
>
> Setting up shared memory for vhost-user is a bit complicated from
> command line, as it requires NUMA setup such as: m 4G -object
> memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on -numa
> node,memdev=mem.
>
> Instead
On 28/11/2019 17.10, Janosch Frank wrote:
> On 11/28/19 4:28 PM, Thomas Huth wrote:
>> On 20/11/2019 12.43, Janosch Frank wrote:
>>> IO instruction data is routed through SIDAD for protected guests, so
>>> adresses do not need to be checked, as this is kernel memory.
>>>
>>> Signed-off-by: Janosch
On Thursday, November 28, 2019, Philippe Mathieu-Daudé
wrote:
> On 11/28/19 2:46 PM, Michael Rolnik wrote:
>
>> I will rename them.
>>
>
> Please wait comments from Richard before a version respin.
>
>
Everything went well last 10 or so days, Michael and Sarah were responsive,
the code and series
This was one of my first attempts, and so I was sure to miss something.. I've
incorporated all the updates in this patch.. Let me know what you think about
this..
net/cadence_gem: Updating the GEM MAC IP to properly filter out the multicast
addresses.
The current code makes a bad assumption t
For full details we also want to see where the mmaps end up.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 2 +-
linux-user/trace-events | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index c81fd85fbd2..a2c7037f1b6 100644
---
The CPU_LOG_PAGE flag is woefully underused and could stand to do
extra duty tracking page changes. If the user doesn't want to see the
details as things change they still have the tracepoints available.
Signed-off-by: Alex Bennée
---
linux-user/mmap.c | 11 +++
1 file changed, 7 inserti
On Thu, 28 Nov 2019 at 17:27, Igor Mammedov wrote:
>
> On Thu, 28 Nov 2019 16:00:06 +
> Peter Maydell wrote:
> > Once a device is hot-unplugged (and thus unrealized) is it valid
> > for it to be re-hot-plugged, or is the assumption that it's then
> > destroyed and a fresh device is created if
On Thursday, November 28, 2019, Alex Bennée wrote:
>
> Aleksandar Markovic writes:
>
> > On Thursday, November 28, 2019, Michael Rolnik
> wrote:
> >
> >> I don't see why you say that the peripherals are inside the chip, there
> is
> >> CPU within target/avr directory and then there are some per
When QOM APIs were added to ich9 in 6f1426ab, the getter for sci_int was
written using uint32_t. However, the object property is uint8_t. This
fixes the getter for correctness.
Signed-off-by: Felipe Franciosi
---
hw/isa/lpc_ich9.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff
Thanks for the pointers.. I will incorporate all these changes and post an
updated thread asap..
-Original Message-
From: Edgar E. Iglesias [mailto:edgar.igles...@gmail.com]
Sent: Thursday, November 28, 2019 10:32 PM
To: Wasim, Bilal
Cc: qemu-devel@nongnu.org; alist...@alistair23.me; p
On Tue, 19 Nov 2019 18:50:03 -0600
Michael Roth wrote:
[..]
> I.e. the calling code is only scheduling a one-shot BH for
> virtio_blk_data_plane_stop_bh, but somehow we end up trying to process
> an additional virtqueue entry before we get there. This is likely due
> to the following check in vir
On Wed, 27 Nov 2019 19:38:06 +0100
Janosch Frank wrote:
> On 11/27/19 7:25 PM, Janosch Frank wrote:
> >
> > There's 0 (initiated), busy and operational and as far as I know we
> > implement neither.
>
> That came out wrong...
> s/operational/not operational/
>
> We only implement "command in
Hi Cornelia,
On 11/28/19 19:11, Cornelia Huck wrote:
> The Posix implementation of guest-set-time invokes hwclock to
> set/retrieve the time to/from the hardware clock. If hwclock
> is not available, the user is currently informed that "hwclock
> failed to set hardware clock to system time", which
On Thu, 28 Nov 2019 17:38:19 +0100
Janosch Frank wrote:
> On 11/21/19 4:11 PM, Thomas Huth wrote:
> > On 20/11/2019 12.43, Janosch Frank wrote:
> >> Secure guests no longer intercept with code 4 for an instruction
> >> interception. Instead they have codes 104 and 108 for secure
> >> instructio
On Thu, 28 Nov 2019 15:30:14 +0100
Boris Fiuczynski wrote:
> Signed-off-by: Boris Fiuczynski
> Reviewed-by: Eric Farman
> ---
> hw/vfio/ccw.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c
> index 6863f6c69f..3b5520ae75 100644
> --- a/hw
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
>
> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> EL2, and that HCR_EL2.TID0 does the same for reads of FPSID.
> In order to handle this, introduce a new TCG helper function that
> checks for these control bits before execu
The Posix implementation of guest-set-time invokes hwclock to
set/retrieve the time to/from the hardware clock. If hwclock
is not available, the user is currently informed that "hwclock
failed to set hardware clock to system time", which is quite
misleading. This may happen e.g. on s390x, which has
On Thu, Nov 28, 2019 at 05:48:00PM +0100, Halil Pasic wrote:
> On Tue, 19 Nov 2019 18:50:03 -0600
> Michael Roth wrote:
>
> [..]
> > I.e. the calling code is only scheduling a one-shot BH for
> > virtio_blk_data_plane_stop_bh, but somehow we end up trying to process
> > an additional virtqueue en
On Thu, 28 Nov 2019 at 17:49, Marc Zyngier wrote:
>
> Hi Peter,
>
> Thanks for having a look at this.
>
> On 2019-11-28 16:43, Peter Maydell wrote:
> > On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
> >>
> >> HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
> >> EL2, and th
Hi Peter,
Thanks for having a look at this.
On 2019-11-28 16:43, Peter Maydell wrote:
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and that HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, i
Do binaries have to be page size aware? I thought it was a runtime thing.
However if the aarch64-linux-user is hardwired to 4k it might explain it's
confusion on a 64k machine.
On Thu, 28 Nov 2019, 16:33 Peter Maydell, wrote:
> If you objdump the binary and the offending library what do they see
Aleksandar Markovic writes:
> On Thursday, November 28, 2019, Michael Rolnik wrote:
>
>> I don't see why you say that the peripherals are inside the chip, there is
>> CPU within target/avr directory and then there are some peripherals in hw
>> directory, CPU does not depend on them. what am I
Currently, ich9_lpc_initfn simply serves as a caller to
ich9_lpc_add_properties. This simplifies the code a bit by eliminating
ich9_lpc_add_properties altogether and executing its logic in the parent
object initialiser function.
Signed-off-by: Felipe Franciosi
---
hw/isa/lpc_ich9.c | 15 +---
Yes, I do have a reason for delaying this LP until after 4.2.0 is out.
When I filed this ticket (on 2019-Nov-12), QEMU had already entered the
4.2.0 soft feature freeze (on 2019-Oct-29). Despite possible
appearances, this LP is actually a feature addition -- that's why I also
set "Tags: feature-re
Patchew URL:
https://patchew.org/QEMU/20191128064350.20727-1-aaron.zakh...@gmail.com/
Hi,
This series failed the docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN
This improves the family of object_property_add_uintXX_ptr helpers by enabling
a default getter/setter only when desired. To prevent an API behavioural change
(from clients that already used these helpers and did not want a setter), we
add a OBJ_PROP_FLAG_RD flag that allow clients to only have a g
On Thu, 28 Nov 2019 17:10:38 +0100
Janosch Frank wrote:
> On 11/28/19 4:28 PM, Thomas Huth wrote:
> > Would it make sense to hide all these changes in decode_basedisp_s()
> > instead? ... so that decode_basedisp_s() returns 0 if env->pv == true ?
> > ... or are there still cases where we need re
On Thu, 28 Nov 2019 07:32:53 +0100
Thomas Huth wrote:
> On 27/11/2019 18.50, Janosch Frank wrote:
> > Let's start moving the cpu reset functions into a single function with
> > a switch/case, so we can use fallthroughs and share more code between
> > resets.
>
> Nit: I'd add a "later" in above
HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, naking it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).
Do the right thing by trappi
On 11/21/19 4:11 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> Secure guests no longer intercept with code 4 for an instruction
>> interception. Instead they have codes 104 and 108 for secure
>> instruction interception and secure instruction notification
>> respectively.
>>
On Tue, 12 Nov 2019 11:48:11 +0100
Cornelia Huck wrote:
> Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.
>
> For i440fx and q35, unversioned cpu models are still translated
> to -v1; I'll leave changing this (if desired) to the respective
> maintainers.
>
> Signed-off-by: Cornelia Huck
HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making impossible for hypervisors to
virtualize the cache hierarchy.
Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.
Signed-off-b
On 2019-11-28 16:30, Peter Maydell wrote:
On Thu, 28 Nov 2019 at 16:17, Marc Zyngier wrote:
I started looking the rest of the missing TIDx handling,
and this resulted in the following patches.
There is still one thing I'm a bit puzzled by though:
HCR_EL2.TID0 mandates trapping of the AArch32
On Thu, Nov 28, 2019 at 05:02:00PM +, Wasim, Bilal wrote:
> This was one of my first attempts, and so I was sure to miss something.. I've
> incorporated all the updates in this patch.. Let me know what you think about
> this..
>
> net/cadence_gem: Updating the GEM MAC IP to properly filter
On 11/28/19 4:28 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> IO instruction data is routed through SIDAD for protected guests, so
>> adresses do not need to be checked, as this is kernel memory.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> target/s390x/ioinst.c | 46
On Thu, Nov 28, 2019 at 04:00:06PM +, Peter Maydell wrote:
> Hi; this is a question which came up in Damien's reset series
> which I don't know the answer to:
>
> What is the interaction of the QOM device lifecycle (instance_init/realize/
> unrealize/instance_finalize) with hotplug and hot-unp
On Thu, 28 Nov 2019 16:00:06 +
Peter Maydell wrote:
> Hi; this is a question which came up in Damien's reset series
> which I don't know the answer to:
>
> What is the interaction of the QOM device lifecycle (instance_init/realize/
> unrealize/instance_finalize) with hotplug and hot-unplug ?
On Thu, 28 Nov 2019 18:15:18 +0400
Marc-André Lureau wrote:
> Add an option to simplify shared memory / vhost-user setup.
>
> Currently, using vhost-user requires NUMA setup such as:
> -m 4G -object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on
> -numa node,memdev=mem
>
> As th
On 11/28/19 4:28 PM, Thomas Huth wrote:
> On 20/11/2019 12.43, Janosch Frank wrote:
>> IO instruction data is routed through SIDAD for protected guests, so
>> adresses do not need to be checked, as this is kernel memory.
>>
>> Signed-off-by: Janosch Frank
>> ---
>> target/s390x/ioinst.c | 46
Traditionally, the uint-specific property helpers only offer getters.
When adding object (or class) uint types, one must therefore use the
generic property helper if a setter is needed (and probably duplicate
some code writing their own getters/setters).
This enhances the uint-specific property he
+Igor
On Thu, Nov 28, 2019 at 06:15:18PM +0400, Marc-André Lureau wrote:
> Add an option to simplify shared memory / vhost-user setup.
>
> Currently, using vhost-user requires NUMA setup such as:
> -m 4G -object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on
> -numa node,memdev=me
So far we only have compile coverage for tci. But since commit
2f160e0f9797c7522bfd0d09218d0c9340a5137c ("tci: Add implementation
for INDEX_op_ld16u_i64") has been included now, we can also run the
"tcg" and "qtest" tests with tci, so let's enable them in Travis now.
Since we don't gain much additi
On 28.11.19 15:12, Kevin Wolf wrote:
> Am 27.11.2019 um 14:15 hat Max Reitz geschrieben:
>> This enum will supplement BdrvChildClass when it comes to what role (or
>> combination of roles) a child takes for its parent.
>>
>> Because empty enums are not allowed, let us just start with it filled.
>>
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