Patchew URL:
https://patchew.org/QEMU/20190922035458.14879-1-richard.hender...@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20190922035458.14879-1-richard.hender...@linaro.org
Subject: [PATCH v3 00/20] Move rom and no
Fixes the previous TLB_WATCHPOINT patches because we are currently
failing to set cpu->mem_io_pc with the call to cpu_check_watchpoint.
Pass down the retaddr directly because it's readily available.
Fixes: 50b107c5d61
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.h | 2 +-
accel/t
All callers pass false to this argument. Remove it and pass the
constant on to tb_invalidate_phys_page_range__locked.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.h | 3 +--
accel/tcg/translate-all.c | 6 ++
exec.c| 4 ++--
3 files changed, 5 insertions(+
On 9/21/19 8:54 PM, Richard Henderson wrote:
> Richard Henderson (20):
> exec: Use TARGET_PAGE_BITS_MIN for TLB flags
> exec: Split out variable page size support to exec-vary.c
> exec: Use const alias for TARGET_PAGE_BITS_VARY
> exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_T
Rather than rely on cpu->mem_io_pc, pass retaddr down directly.
Within tb_invalidate_phys_page_range__locked, the is_cpu_write_access
parameter is non-zero exactly when retaddr would be non-zero, so that
is a simple replacement.
Recognize that current_tb_not_found is true only when mem_io_pc
(and
We can use notdirty_write for the write and
return a valid host pointer for this case.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 26 +-
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6f685cb93a.
With the merge of notdirty handling into store_helper,
the last user of cpu->mem_io_vaddr was removed.
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2 --
accel/tcg/cputlb.c| 2 --
hw/core/cpu.c | 1 -
3 files changed, 5 deletions(-)
diff --git a/include/hw/core/cpu.h
Pages that we want to track for NOTDIRTY are RAM. We do not
really need to go through the I/O path to handle them.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 2 --
accel/tcg/cputlb.c| 26 +---
exec.c| 50
There is only one caller, tlb_set_page_with_attrs. We cannot
inline the entire function because the AddressSpaceDispatch
structure is private to exec.c, and cannot easily be moved to
include/exec/memory-internal.h.
Compute is_ram and is_romd once within tlb_set_page_with_attrs.
Fold the number of
Since 9458a9a1df1a, all readers of the dirty bitmaps wait
for the rcu lock, which means that they wait until the end
of any executing TranslationBlock.
As a consequence, there is no need for the actual access
to happen in between the _prepare and _complete. Therefore,
we can improve things by mer
The memory_region_tb_read tracepoint is unreachable, since notdirty
is supposed to apply only to writes. The memory_region_tb_write
tracepoint is mis-named, because notdirty is not only used for TB
invalidation. It is also used for e.g. VGA RAM updates and migration.
Replace memory_region_tb_wri
It does not require going through the whole I/O path
in order to discard a write.
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h| 5 -
include/exec/cpu-common.h | 1 -
accel/tcg/cputlb.c| 35 +++--
exec.c| 41 +---
Add a function parameter to perform the actual load/store to ram.
With optimization, this results in identical code.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 159 +++--
1 file changed, 83 insertions(+), 76 deletions(-)
diff --git a/accel/
There are some uint64_t uses that expect TARGET_PAGE_MASK to
extend for a 32-bit, so this must continue to be a signed type.
Define based on TARGET_PAGE_BITS not TARGET_PAGE_SIZE; this
will make a following patch more clear.
This should not have a functional effect so far.
Reviewed-by: Paolo Bonz
This forced inlining can result in missing symbols,
which makes a debugging build harder to follow.
Reviewed-by: David Hildenbrand
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/qemu/compiler.h | 11 +++
accel/tcg/cputlb.c | 4 ++--
2 files changed, 13 in
Handle bswap on ram directly in load/store_helper. This fixes a
bug with the previous implementation in that one cannot use the
I/O path for RAM.
Fixes: a26fc6f5152b47f1
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 4 +-
accel/tcg/cputlb.c | 108 +-
Use TARGET_PAGE_MASK twice instead of TARGET_PAGE_SIZE once.
This is functionally identical, but will help a following patch.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/exec
This eliminates a set of runtime shifts. It turns out that we
require TARGET_PAGE_MASK more often than TARGET_PAGE_SIZE, so
redefine TARGET_PAGE_SIZE based on TARGET_PAGE_MASK instead of
the other way around.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.
Using a variable that is declared "const" for this tells the
compiler that it may read the value once and assume that it
does not change across function calls.
For target_page_size, this means we have only one assert per
function, and one read of the variable.
This reduces the size of qemu-system
This reduces the size of a release build by about 10k.
Noticably, within the tlb miss helpers.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/inc
The next patch will play a trick with "const" that will
confuse the compiler about the uses of target_page_bits
within exec.c. Moving everything to a new file prevents
this confusion.
No functional change so far.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Paolo Bonzini
Signed-off-by: Ric
These bits do not need to vary with the actual page size
used by the guest.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
---
include/exec/cpu-all.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.
Ok! Third time is the charm, because this time it works.
New to v3:
* Covert io_mem_rom with a new TLB_ROM bit.
* This in turn means that there are no longer any special RAM
case along along the MMIO path -- they all have devices on
the other end.
* This in turn means that we can
On Sat, Sep 21, 2019 at 6:12 AM Alistair Francis wrote:
>
> On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> >
> > On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis
> > wrote:
> > >
> > > Add a property that when set to true QEMU will jump from the ROM code to
> > > the start of flash memory in
On Sat, Sep 21, 2019 at 6:16 AM Alistair Francis wrote:
>
> On Thu, Sep 19, 2019 at 10:15 PM Bin Meng wrote:
> >
> > On Fri, Sep 20, 2019 at 6:36 AM Alistair Francis
> > wrote:
> > >
> > > Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash
> > > from the ARM Virt board and th
On 9/18/19 11:02 AM, Richard Henderson wrote:
> However this time the changes are extremely minimal, and now
> I really *really* don't understand why they don't work, because
> as far as I can tell the new locking is *identical* with the
> current i/o path.
The difference was failing to set cpu->m
On 9/21/19 3:34 AM, Philippe Mathieu-Daudé wrote:
> IEC binary prefixes ease code review: the unit is explicit.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/boot.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 9/21/19 2:17 AM, Thomas Huth wrote:
> Coverity currently complains that the "if (0x00 & (0x80 >> (phase - 8))"
> in next-cube.c can never be true. Right it is. The "0x00" is meant as value
> of the control register of the RTC, which is currently not implemented yet.
> Thus, let's add a register
We are going to make CONFIG_ARM_V7M optional, so the related cortex-m
CPUs should only be created if the switch is enabled. This can best
be done if the code resides in a separate file, thus move the related
functions to a new file v7m.c which only gets compiled if CONFIG_ARM_V7M
is enabled.
Signe
qemu-system-arm/-aarch64 currently can't be built without setting the
switch CONFIG_ARM_V7M=y - which we currently always do in the config file
default-configs/arm-softmmu.mak. This is because the code in target/arm/
calls many functions from this armv7m_nvic.c, and thus linking fails
without this
Move the common set_feature() and unset_feature() functions from cpu.c and
cpu64.c to internals.h, and make cpu_register() (renamed to arm_cpu_register())
available from there, too, so we can register CPUs also from other files
in the future.
Signed-off-by: Thomas Huth
---
target/arm/cpu.c
The arm builds can now be done without CONFIG_ARM_V7M, so do not
enforce this config switch anymore, it's getting selected in
hw/arm/Kconfig automatically if needed.
Signed-off-by: Thomas Huth
---
default-configs/arm-softmmu.mak | 3 ---
1 file changed, 3 deletions(-)
diff --git a/default-confi
We've got CONFIG_ARM_V7M, but it currently can't be disabled.
Here are some patches that should allow to disable the switch
(if the corresponding boards are disabled, too).
RFC -> v1:
- Move the definitions into internals.h instead of cpu.h in the 1st patch
- Instead of creating an ugly stubs fi
On 21/09/2019 10.54, Andrei Borzenkov wrote:
> USB card reader emulated by QEMU announces presence of PIN pad. OpenSC
> will not request PIN from user in this case and assumes PIN is being
> entered off-band on external device. Unfortunately QEMU does not seem to
> offer PIN entry and access to car
On Wednesday, September 4, 2019 1:13 PM, Philippe Mathieu-Daudé wrote:
>Esteban wrote me over the weekend asking about raspi4 progress.
>I cleaned up my patches/notes to pass him. Other help is also welcomed :)
>I got scared trying to understand how to use the GIC, and wire the various
>IRQs.
>
>Mo
USB card reader emulated by QEMU announces presence of PIN pad. OpenSC
will not request PIN from user in this case and assumes PIN is being
entered off-band on external device. Unfortunately QEMU does not seem to
offer PIN entry and access to card always fails.
Changing device to not announce non-
Hi, Sergio,
> For this reason, the v2 personality is disabled, keeping the legacy
> behavior as default. Machine types willing to use v2, can enable it
> using MachineClass's compat_props.
...
> + DEFINE_PROP_BOOL("force-legacy", VirtIOMMIOProxy, legacy, true),
Currently, I am not enable to s
Hi Philippe,
On Sat, Sep 21, 2019 at 4:51 PM Philippe Mathieu-Daudé
wrote:
>
> Hi Bin,
>
> On 9/21/19 7:41 AM, Bin Meng wrote:
> > The "clock-frequency" property of cpu nodes isn't required. Drop it.
> >
> > This is to keep in sync with Linux kernel commit below:
> > https://patchwork.kernel.org/
Apologies, it looks like I ran into two separate bugs, one with XFS, and
one with BTRFS, that had the same symptom, initially making me to think
this must be a QEMU issue.
Using blktrace, I was able to see within the VM, that the virtio block
device wasn't getting the writes that were going into u
IEC binary prefixes ease code review: the unit is explicit.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/boot.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index bf97ef3e33..59bb2fa0d3 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.
If the period is too big, the 'delta * period' product result
might overflow, resulting in a negative number, then the
next_event ends before the last_event. This is buggy, as there
is no forward progress. Assert this can not happen.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/ptimer.c | 3
Hi John,
On 9/20/19 2:14 AM, John Snow wrote:
> These are listed as "partial" images, but have no user.
> Remove them.
>
> Signed-off-by: John Snow
> ---
> tests/docker/Makefile.include| 4 +--
> tests/docker/dockerfiles/debian-ports.docker | 36
> tests/do
Coverity currently complains that the "if (0x00 & (0x80 >> (phase - 8))"
in next-cube.c can never be true. Right it is. The "0x00" is meant as value
of the control register of the RTC, which is currently not implemented yet.
Thus, let's add a register variable for this now. However, the RTC
registe
On 6/14/19 8:44 PM, Alex Bennée wrote:
> Laszlo Ersek writes:
>> On 06/13/19 18:59, Philippe Mathieu-Daudé wrote:
>>> Hi Laszlo,
>>>
>>> On 3/12/19 5:29 PM, Laszlo Ersek wrote:
On 03/11/19 01:30, Philippe Mathieu-Daudé wrote:
> Add a job to build and install the EDK2 platform firmware bin
On 9/18/19 1:22 AM, Alistair Francis wrote:
> From: Palmer Dabbelt
>
> We directly access physical memory while walking the page tables on
> RISC-V, but while doing so we were using cpu_ld*() which does not report
> bus errors. This patch converts the page table walker over to use
> address_spac
On 9/18/19 1:23 AM, Alistair Francis wrote:
> From: Palmer Dabbelt
>
> This converts our port over from cpu_do_unassigned_access to
> cpu_do_transaction_failed, as cpu_do_unassigned_access has been
> deprecated.
>
> Signed-off-by: Palmer Dabbelt
> Signed-off-by: Alistair Francis
> ---
> targe
On 9/20/19 1:29 AM, Richard Henderson wrote:
> This reduces the size of a release build by about 10k.
> Noticably, within the tlb miss helpers.
>
> Signed-off-by: Richard Henderson
> ---
> include/exec/cpu-all.h | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/inclu
On 9/20/19 1:29 AM, Richard Henderson wrote:
> The next patch will play a trick with "const" that will
> confuse the compiler about the uses of target_page_bits
> within exec.c. Moving everything to a new file prevents
> this confusion.
>
> No functional change so far.
>
> Signed-off-by: Richard
On 9/21/19 6:32 AM, Richard Henderson wrote:
> Remove a redundant masking of ignore. Once that's gone it is
> obvious that the system-mode inner test is redundant with the
> outer test. Move the fpcr_exc_enable masking up and tidy.
>
> No functional change.
>
> Signed-off-by: Richard Henderson
On 9/21/19 6:32 AM, Richard Henderson wrote:
> Tidy the computation of the value; no functional change.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/alpha/helper.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/tar
On 9/21/19 6:32 AM, Richard Henderson wrote:
> This is a bit more straight-forward than using a switch statement.
> No functional change.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/alpha/helper.c | 24
> 1 file changed, 8 i
On 9/21/19 7:41 AM, Bin Meng wrote:
> U-Boot expects this alias to be in place in order to fix up the mac
> address of the ethernet node.
>
> This is to keep in sync with Linux kernel commit below:
> https://patchwork.kernel.org/patch/11133033/
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair
Hi Bin,
On 9/21/19 7:41 AM, Bin Meng wrote:
> The "clock-frequency" property of cpu nodes isn't required. Drop it.
>
> This is to keep in sync with Linux kernel commit below:
> https://patchwork.kernel.org/patch/11133031/
What happens if you run a older kernel that doesn't contain the
referenced
On 9/21/19 12:12 AM, John Snow wrote:
> As part of the push to drop python2 support, replace any explicit python2
> dependencies with python3 versions.
>
> For centos, python2 still exists as an implicit dependency, but by adding
> python3 we will be able to build even if the configure script begi
On 9/21/19 12:12 AM, John Snow wrote:
> We don't have a debian8-mxe dockerfile anymore.
>
> Signed-off-by: John Snow
> Message-id: 20190920001413.22567-3-js...@redhat.com
^ remove?
Fixes: 67bd36beda1ae
Reviewed-by: Philippe Mathieu-Daudé
> ---
> tests/docker/Makefile.include | 2 +-
> 1 fi
On 9/21/19 12:12 AM, John Snow wrote:
> debian8 partial base is also not consumed by any image, so remove it.
Reviewed-by: Philippe Mathieu-Daudé
>
> Signed-off-by: John Snow
> ---
> tests/docker/Makefile.include | 3 +--
> tests/docker/dockerfiles/debian8.docker | 33 -
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