On 7/9/19 03:03, Dr. David Alan Gilbert wrote:
* Brad Campbell (lists2...@fnarfbargle.com) wrote:
On 2/9/19 6:23 pm, Brad Campbell wrote:
Here is the holdup :
11725@1567416625.003504:qxl_ring_command_check 0 native
11725@1567416625.102653:qxl_io_write 0 native addr=0 (QXL_IO_NOTIFY_CMD)
val
From: Pierre Morel
To have a clean separation between s390-pci-bus.h
and s390-pci-inst.h headers we export the PCI CLP
instructions in a dedicated header.
Signed-off-by: Pierre Morel
Reviewed-by: Collin Walling
---
hw/s390x/s390-pci-bus.h | 1 +
hw/s390x/s390-pci-clp.h | 211 +
From: Pierre Morel
We use the VFIO_REGION_SUBTYPE_ZDEV_CLP subregion of
PCI_VENDOR_ID_IBM to retrieve the CLP information the
kernel exports.
To be compatible with previous kernel versions we fall back
on previous predefined values, same as the emulation values,
when the region is not found or w
From: Pierre Morel
We use a ClpRspQueryPci structure to hold the information
related to zPCI Function.
This allows us to be ready to support different zPCI functions
and to retrieve the zPCI function information from the host.
Signed-off-by: Pierre Morel
---
hw/s390x/s390-pci-bus.c | 22
Note: These patches by Pierre got lost in the ether a few months back
as he has been unavailable to carry them forward. I've made changes
based upon comments received on the kernel part of his last version.
This patch implement the QEMU part to retrieve ZPCI specific
information from the host.
Th
From: Pierre Morel
We use a S390PCIGroup structure to hold the information
related to zPCI Function group.
This allows us to be ready to support multiple groups and to retrieve
the group information from the host.
Signed-off-by: Pierre Morel
---
hw/s390x/s390-pci-bus.c | 42 +
From: Pierre Morel
This should be copied from Linux kernel UAPI includes.
The version used here is Linux 5.3.0
We define a new device region in vfio.h to be able to
get the ZPCI CLP information by reading this region from
userland.
We create a new file, vfio_zdev.h to define the structure
of th
I was playing with the new objects, etc, and found if the user
specifies -sgx-epc, and a memory device, but does not specify -cpu
host, +sgx, the vm runs without any warnings, while obviously not doing
anything to the memory. Perhaps some warnings if not everything which
is required is provided?
O
Alright, I couldn't reproduce this yet, I'm running same test case in a
24 cores box and causing lots of context switches and CPU migrations in
parallel (trying to exhaust the logic).
Will let this running for sometime to check.
Unfortunately this can be related QEMU AIO BH locking/primitives and
On Fri, Sep 6, 2019 at 9:20 AM Bin Meng wrote:
>
> Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
> added "hw/hw.h" to sifive_prci.c and sifive_test.c.
>
> Another inclusion of "hw/hw.h" was later added via
> commit 650d103d3ea9 ("Include hw/hw.h exactly where needed"), that
> r
On Fri, 2019-09-06 at 23:10 +0200, Stefano Garzarella wrote:
> On Fri, Sep 06, 2019 at 04:17:12PM +, Dmitry Fomichev wrote:
> > On Fri, 2019-09-06 at 10:11 +0200, Stefano Garzarella wrote:
> > > On Wed, Sep 04, 2019 at 05:00:57PM -0400, Dmitry Fomichev wrote:
> > > > This commit adds Zoned Devi
On Fri, Sep 06, 2019 at 04:17:12PM +, Dmitry Fomichev wrote:
> On Fri, 2019-09-06 at 10:11 +0200, Stefano Garzarella wrote:
> > On Wed, Sep 04, 2019 at 05:00:57PM -0400, Dmitry Fomichev wrote:
> > > This commit adds Zoned Device Model (as defined in T10 ZBC and
> > > T13 ZAC standards) as a blo
Le 06/09/2019 à 18:57, Max Filippov a écrit :
> QEMU_STRACE and QEMU_RAND_SEED are handled by the parse_args, no need to
> do it again in main.
>
> Signed-off-by: Max Filippov
> ---
> linux-user/main.c | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff --git a/linux-user/main.c b/linux-user
Now we do all our checking and use a common EXCP_SEMIHOST for
semihosting operations we can make helper code a lot simpler.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v2
- fix re-base conflicts
- hoist EXCP_SEMIHOST check
- comment cleanups
v5
- move CONFIG_TCG ifdefs
Hi Peter,
Hopefully this is the final version of the semihosting at translate
time patches. I've applied Richard's IS_USER changes and gated the SVN
for !M profile.
Alex Bennée (3):
target/arm: handle M-profile semihosting at translate time
target/arm: handle A-profile semihosting at translat
From: "Emilio G. Cota"
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
accel/tcg/atomic_template.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.
As for the other semihosting calls we can resolve this at translate
time.
Signed-off-by: Alex Bennée
---
v2
- update for change to gen_exception_internal_insn API
v3
- update for decode tree, merge T32 & A32 commits
- dropped r-b due to changes
v4
- !IS_USER and !arm_dc_feature(s, ARM_FE
We do this for other semihosting calls so we might as well do it for
M-profile as well.
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
---
v2
- update for change to gen_exception_internal_insn API
v3
- update for decode tree
v4
- use !IS_USER
---
target/arm/m_helper.c | 18 ++
Signed-off-by: Maxim Levitsky
---
tests/qemu-iotests/263 | 75 ++
tests/qemu-iotests/263.out | 19 ++
tests/qemu-iotests/group | 1 +
3 files changed, 95 insertions(+)
create mode 100755 tests/qemu-iotests/263
create mode 100644 tests/qemu-iote
Commit 8ac0f15f335 accidently broke the COW of non changed areas
of newly allocated clusters, when the write spans multiple clusters,
and needs COW both prior and after the write.
This results in 'after' COW area being encrypted with wrong
sector address, which render it corrupted.
Bugzilla: https
This fixes subtle corruption introduced by luks threaded encryption
in commit 8ac0f15f335
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1745922
The corruption happens when we do a write that
* writes to two or more unallocated clusters at once
* doesn't fully cover the first sector
This commit tries to clarify few function arguments,
and add comments describing the encrypt/decrypt interface
Signed-off-by: Maxim Levitsky
---
block/qcow2-cluster.c | 10 +++
block/qcow2-threads.c | 61 ++-
2 files changed, 53 insertions(+), 18 delet
Markus Armbruster writes:
> Alex Bennée writes:
>
>> Hi,
>>
>> This is the latest iteration of the plugins series. The main changes
>> from the last version are:
>>
>> - dropped passing of haddr to plugins
>>
>> This makes the code for handling the plugins less invasive in the
>> softmmu pat
On Fri, 2019-09-06 at 14:17 -0500, Eric Blake wrote:
> On 9/6/19 12:32 PM, Maxim Levitsky wrote:
> > This fixes subltle corruption introduced by luks threaded encryption
>
> subtle
I usually put the commit messages to a spellchecker, but this time
I forgot to do this. I will try not to in the fut
Aaron Lindsay OS writes:
> One thing I would find useful is the ability to access register values
> during an execution-time callback. I think the easiest way to do that
> generically would be to expose them via the gdb functionality (like
> Pavel's earlier patchset did [1]), though that (curre
On 9/6/19 2:20 PM, Eric Blake wrote:
> On 9/6/19 2:12 PM, Moger, Babu wrote:
>> Introduce cpu core complex id(ccx_id) in x86CPU topology.
>> Each CCX can have upto 4 cores and share same L3 cache.
>> This information is required to build the topology in
>> new apyc mode.
>>
>> Signed-off-by: Babu
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f25491a029..f8b1fc5c07 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4094,9 +4094,10 @@ void cpu
Adds new epyc property in PCMachineState and also in MachineState.
This property will be used to initialize the mode specific handlers
to generate apic ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 23 +++
include/hw/boards.h |2 ++
include/hw/i386/pc.h |
Introduce following handlers for new epyc mode.
x86_apicid_from_cpu_idx_epyc: Generate apicid from cpu index.
x86_topo_ids_from_apicid_epyc: Generate topo ids from apic id.
x86_apicid_from_topo_ids_epyci: Generate apicid from topo ids.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 +
1 f
On 9/6/19 2:12 PM, Moger, Babu wrote:
> Introduce cpu core complex id(ccx_id) in x86CPU topology.
> Each CCX can have upto 4 cores and share same L3 cache.
> This information is required to build the topology in
> new apyc mode.
>
> Signed-off-by: Babu Moger
> ---
> +++ b/qapi/machine.json
> @@
Current topology id match will not work for epyc mode when setting
the node id. In epyc mode, ids like smt_id, thread_id, core_id,
ccx_id, socket_id can be same for more than one CPUs with across
two numa nodes.
For example, we can have two CPUs with following ids on two different node.
1. smt_id=
hw/i386: Introduce topo_ids_from_apicid handler PCMachineState
Add function pointer topo_ids_from_apicid in PCMachineState.
Initialize with correct handler based on mode selected.
x86_apicid_from_cpu_idx will be the default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 13
Add function pointers in PCMachineState to handle apic id specific
functionalities. This will be used to initialize with correct
handlers based on mode selected.
x86_apicid_from_cpu_idx will be default handler.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |5 -
include/hw/i386/pc.
On 9/6/19 12:32 PM, Maxim Levitsky wrote:
> This fixes subltle corruption introduced by luks threaded encryption
subtle
> in commit 8ac0f15f335
>
> Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1745922
>
> The corruption happens when we do
>* write to two or more unallocated cluster
Introduce initialize_topo_info to initialize X86CPUTopoInfo
data structure to build the topology. No functional change.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
ind
Use the new epyc mode functions and delete the unused code.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 171 +++--
1 file changed, 48 insertions(+), 123 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ca02bc21ec..f2549
Introduce cpu core complex id(ccx_id) in x86CPU topology.
Each CCX can have upto 4 cores and share same L3 cache.
This information is required to build the topology in
new apyc mode.
Signed-off-by: Babu Moger
---
hw/core/machine-hmp-cmds.c |3 +++
hw/core/machine.c | 13 ++
Add function pointer apic_id_from_topo_ids in PCMachineState.
Initialize with correct handler based on the mode selected.
Also rename the handler apicid_from_topo_ids to x86_apicid_from_topo_ids
for consistency. x86_apicid_from_topo_ids will be the default handler.
Signed-off-by: Babu Moger
---
Some parameters are unnecessarily passed for offset/width
calculation. Remove those parameters from function prototypes.
No functional change.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 45 ++--
target/i386/cpu.c | 12 -
This is an effort to re-arrange few data structure for better
readability. Add X86CPUTopoInfo which will have all the topology
informations required to build the cpu topology. There is no
functional changes.
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 40
These functions add support for building new epyc mode topology
given smp details like numa nodes, cores, threads and sockets.
Subsequent patches will use these functions to build the topology.
The topology details are available in Processor Programming Reference (PPR)
for AMD Family 17h Model 01h
Store the smp Sockets in CpuTopology. Socket information
is required to build the cpu topology in new epyc mode.
Signed-off-by: Babu Moger
---
hw/core/machine.c |1 +
hw/i386/pc.c|1 +
include/hw/boards.h |2 ++
vl.c|1 +
4 files changed, 5 insertions(+
Rename few data structures related to X86 topology.
X86CPUTopoIDs will have individual arch ids. Next
patch introduces X86CPUTopoInfo which will have all
topology information(like cores, threads etc..).
Adds node_id and ccx_id. This will be required to support
new epyc mode mode. There is no funct
To support new epyc mode, we need to know the number of numa nodes
in advance to generate apic id correctly. So, split the numa
initialization into two. The function parse_numa initializes numa_info
and updates nb_numa_nodes. And then parse_numa_node does the numa node
initialization.
Signed-off-b
These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166
This is the second pass to give an idea of the changes required to address
the issue. First pass is availabe at
https://patchwork.kernel.org/cover/11069785/
Currently, ap
04.09.2019. 23.59, "Alex Bennée" је написао/ла:
>
> Now Buster is released we can stop relying on the movable feast that
> is Sid for our cross-compiler for building tests.
>
> Signed-off-by: Alex Bennée
> ---
Reviewed-by: Aleksandar Markovic
> tests/docker/Makefile.include
* Brad Campbell (lists2...@fnarfbargle.com) wrote:
> On 2/9/19 6:23 pm, Brad Campbell wrote:
>
> >
> > Here is the holdup :
> >
> > 11725@1567416625.003504:qxl_ring_command_check 0 native
> > 11725@1567416625.102653:qxl_io_write 0 native addr=0 (QXL_IO_NOTIFY_CMD)
> > val=0 size=1 async=0
> >
>
On Fri, 2019-09-06 at 14:00 -0500, Eric Blake wrote:
> On 9/6/19 1:55 PM, Maxim Levitsky wrote:
>
> > > > +/*
> > > > + * qcow2_co_encrypt()
> > > > + *
> > > > + * Encrypts a sector size aligned contiguous area
> > > > + *
> > > > + * @host_cluster_offset - on disk offset of the cluster in which
On 9/6/19 1:55 PM, Maxim Levitsky wrote:
>>> +/*
>>> + * qcow2_co_encrypt()
>>> + *
>>> + * Encrypts a sector size aligned contiguous area
>>> + *
>>> + * @host_cluster_offset - on disk offset of the cluster in which
>>> + *the buffer resides
>>> + *
>>> + * @guest_offset -
Hi Shu-Chun Weng via Qemu-devel!
We received your email, but were unable to deliver it because it
contains content which has been blacklisted by the list admin. Please
remove your application/pkcs7-signature attachments and send again.
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On Fri, 2019-09-06 at 13:00 -0500, Eric Blake wrote:
> On 9/6/19 12:31 PM, Maxim Levitsky wrote:
> > This commit tries to clarify few function arguments,
> > and add comments describing the encrypt/decrypt interface
> >
> > Signed-off-by: Maxim Levitsky
> > ---
> > block/qcow2-cluster.c | 8 +++
Hi Shu-Chun Weng via Qemu-devel!
We received your email, but were unable to deliver it because it
contains content which has been blacklisted by the list admin. Please
remove your application/pkcs7-signature attachments and send again.
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Ping. Patchwork links:
http://patchwork.ozlabs.org/patch/1151884/
http://patchwork.ozlabs.org/patch/1151883/
On Thu, Aug 22, 2019 at 4:14 PM Shu-Chun Weng wrote:
> Shu-Chun Weng (2):
> linux-user: add missing UDP and IPv6 setsockopt options
> linux-user: time stamping options for setsockopt
Ping. Any comments on this? Patchwork:
http://patchwork.ozlabs.org/patch/1151167/
On Wed, Aug 21, 2019 at 1:19 PM Shu-Chun Weng wrote:
> Besides /proc/self|, files under /proc/thread-self and
> /proc/self|/task/ also expose host information to the guest
> program. This patch adds them to the hij
On 9/6/19 12:31 PM, Maxim Levitsky wrote:
> This commit tries to clarify few function arguments,
> and add comments describing the encrypt/decrypt interface
>
> Signed-off-by: Maxim Levitsky
> ---
> block/qcow2-cluster.c | 8 +++
> block/qcow2-threads.c | 53
On Fri, 2019-09-06 at 20:31 +0300, Maxim Levitsky wrote:
> Commit 8ac0f15f335 accidently broke the COW of non changed areas
> of newly allocated clusters, when the write spans multiple clusters,
> and needs COW both prior and after the write.
> This results in 'after' COW area beeing encrypted with
This fixes subltle corruption introduced by luks threaded encryption
in commit 8ac0f15f335
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1745922
The corruption happens when we do
* write to two or more unallocated clusters at once
* write doesn't fully cover nether first nor last cl
This commit tries to clarify few function arguments,
and add comments describing the encrypt/decrypt interface
Signed-off-by: Maxim Levitsky
---
block/qcow2-cluster.c | 8 +++
block/qcow2-threads.c | 53 ++-
2 files changed, 46 insertions(+), 15 delet
Commit 8ac0f15f335 accidently broke the COW of non changed areas
of newly allocated clusters, when the write spans multiple clusters,
and needs COW both prior and after the write.
This results in 'after' COW area beeing encrypted with wrong
sector address, which render it corrupted.
Bugzilla: http
Signed-off-by: Maxim Levitsky
---
tests/qemu-iotests/263 | 76 ++
tests/qemu-iotests/263.out | 19 ++
tests/qemu-iotests/group | 1 +
3 files changed, 96 insertions(+)
create mode 100755 tests/qemu-iotests/263
create mode 100644 tests/qemu-iote
Hi!
I just had a very fun rabbit hole dive, and I want to share it with you.
I notice for some time that iotest 162 fails with that:
-qemu-img: Could not open 'json:{"driver": "nbd", "host": 42}': Failed to
connect socket: Invalid argument
+qemu-img: Could not open 'json:{"driver": "nbd", "host
Le 06/09/2019 à 18:55, Max Filippov a écrit :
> On Fri, Sep 6, 2019 at 2:33 AM Laurent Vivier wrote:
>> Le 26/08/2019 à 21:58, Max Filippov a écrit :
>>> +#if defined(TARGET_XTENSA)
>>> +if (getenv("QEMU_XTENSA_ABI_CALL0")) {
>>> +xtensa_set_abi_call0();
>>> +}
>>
>> Not needed, th
QEMU_STRACE and QEMU_RAND_SEED are handled by the parse_args, no need to
do it again in main.
Signed-off-by: Max Filippov
---
linux-user/main.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index c9d97d2b1fc6..22ae2b3e65d1 100644
--- a/linux-user
Xtensa binaries built for call0 ABI don't rotate register window on
function calls and returns. Invocation of signal handlers from the
kernel is therefore different in windowed and call0 ABIs.
There's currently no way to determine xtensa ELF binary ABI from the
binary itself. Add handler for the -x
On Fri, Sep 6, 2019 at 2:33 AM Laurent Vivier wrote:
> Le 26/08/2019 à 21:58, Max Filippov a écrit :
> > +#if defined(TARGET_XTENSA)
> > +if (getenv("QEMU_XTENSA_ABI_CALL0")) {
> > +xtensa_set_abi_call0();
> > +}
>
> Not needed, this is done by parse_args() that checks
> getenv(arg
With the support of heterogeneous harts and PRCI model, it's now
possible to use the OpenSBI image (PLATFORM=sifive/fu540) built
for the real hardware.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Chang
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating
chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will
use this information to locate the serial node and probe its driver.
However currently we generate the UART node name as "/soc/uart@...",
causing U-Boot fail to f
To keep in sync with Linux kernel device tree, generate hfclk and
rtcclk nodes in the device tree, to be referenced by PRCI node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes
Ping at the load moment:
ping 192.168.152.25
PING 192.168.152.25 (192.168.152.25) 56(84) bytes of data.
64 bytes from 192.168.152.25: icmp_seq=1 ttl=128 time=0.300 ms
64 bytes from 192.168.152.25: icmp_seq=2 ttl=128 time=0.495 ms
64 bytes from 192.168.152.25: icmp_seq=3 ttl=128 time=0.442 ms
64 by
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Cha
At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.
Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000M
Hello,
On Fri, Sep 6, 2019 at 11:22 PM Bin Meng wrote:
>
> On Fri, Sep 6, 2019 at 11:09 PM Bin Meng wrote:
> >
> > Commit a27bd6c779ba ("Include hw/qdev-properties.h less") wrongly
> > added "hw/hw.h" to sifive_prci.c and sifive_test.c.
> >
> > Another inclusion of "hw/hw.h" was later added via
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed
Public bug reported:
I have issue with qemu and winxp guest on i5-8350U.
First of all, if i run same vm with same config on i5 9660k i do not see such
issue.
Both pc have ubuntu 19.04 x86_64.
Guest is winxp64, tried:
1) stable guest drivers, latest drivers
2) all virtio, only network r18169, br
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-by: Bin Meng
Rev
Current SiFive PRCI model only works with sifive_e machine, as it
only emulates registers or PRCI block in the FE310 SoC.
Rename the file name to make it clear that it is for sifive_e.
This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables
and functions.
Signed-off-by: Bin Meng
Reviewe
This implements a simple model for SiFive FU540 OTP (One-Time
Programmable) Memory interface, primarily for reading out the
stored serial number from the first 1 KiB of the 16 KiB OTP
memory reserved by SiFive for internal use.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes
This updates model and compatible strings to use the same strings
as used in the Linux kernel device tree (hifive-unleashed-a00.dts).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Ch
On 9/6/19 6:19 PM, Bin Meng wrote:
> Like other binary files, the executable attribute of opensbi images
> should not be set.
Ideally we'd have checkpatch warning for incorrect permissions when
adding blobs under pc-bios/.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Reviewed-b
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and
SIFIVE_E_PRCI_HFXOSCCFG_EN should be used.
Signed-off-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Chan
This adds an OTP memory with a given serial number to the sifive_u
machine. With such support, the upstream U-Boot for sifive_fu540
boots out of the box on the sifive_u machine.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: Non
This updates the UART base address and IRQs to match the hardware.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Acked-by: Alistair Francis
Reviewed-by: Chih-Min Chao
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- fix incorrectly indented comment lines
- re
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- new patch to remove the unnecessary include of target/riscv/cpu.h
Change
Currently riscv_harts_realize() creates all harts based on the
same cpu type given in the hart array property. With current
implementation it can only create homogeneous harts. Exact the
hart realize to a separate routine in preparation for supporting
multiple hart arrays.
Note the file header say
It is not useful if we only have one management CPU.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- use management cpu count + 1 for the min_cpus
Changes in v2:
- up
Add PRCI mmio base address and size mappings to sifive_u machine,
and generate the corresponding device tree node.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- create sifive_u_prci block directly in the m
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...)
Use create_unimplemented_device() instead.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8:
- select UNIMP in sifive_e Kconfig due to applied commit
"hw/misc: Add a config switch for the "unimplemented" device"
in latest qemu/master
Changes in v7: None
Changes in v
Group SiFive E and U cpu type defines into one header file.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
As of today, the QEMU 'sifive_u' machine is a special target that does
not boot the upstream OpenSBI/U-Boot firmware images built for the real
SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform
"qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced
in the OpenSB
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifi
Some of the properties only have 1 cell so we should use
qemu_fdt_setprop_cell() instead of qemu_fdt_setprop_cells().
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Currently the PRCI register block size is set to 0x8000, but in fact
0x1000 is enough, which is also what the manual says.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Change
This removes "reg-names" and "riscv,max-priority" properties of the
PLIC node from device tree.
Signed-off-by: Bin Meng
Reviewed-by: Jonathan Behrens
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes i
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- remove 2 more "linux,phand
There is no need to return fdt at the end of create_fdt() because
it's already saved in s->fdt.
Signed-off-by: Bin Meng
Reviewed-by: Chih-Min Chao
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.
Signed-off-by: Bin Meng
Reviewed-by: Palmer Dabbelt
---
Changes in v8:
- newly included in v8 to ease patch inter dependencies
hw/riscv/sifive_test.c | 4
include/hw/riscv/sifive_test.
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